RU2522930C2 - Method of thin film transistor manufacturing - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: method of thin film transistor manufacturing involves heavy-doped monocrystalline silicon plates of n⁺ conductivity type as a substrate, silicon dioxide layer of 110 nm thickness grown by thermal oxidation in dry oxygen as gate isolator, further forming of amorphous silicon film of 430 nm thickness in HF glow discharge in silane at substrate temperature of 250°C and implanting fluorine ions with 25 keV energy and 10¹⁴-5·10¹⁵ cm^-2 dose rate. After implanting, samples are annealed in nitrogen medium at 200-220°C for 60 minutes, passivating silicon oxide layer of 150 nm is applied in SiH₄ and N₂O plasma mix, and phosphorus ions with 30 keV energy and 10¹⁶ cm^-2 dose rate are implanted to form thin amorphous silicon layer of n⁺ type.

EFFECT: reduced flaw density, improved fabricability, instrument parameters and quality, increased percentage yield of serviceable devices.

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Description

The invention relates to the field of technology for the production of semiconductor devices, in particular to the technology of manufacturing thin-film transistors with a reduced density of defects.

A known method of manufacturing a thin-film transistor [Application 1276765 Japan, MKI H01L 29/78] by creating on a glass substrate a quantum-well heterostructure Si / Ge / Si, which is coated with an insulating layer. The side parts of the structure are doped with phosphorus to reduce the series resistance, and the gate made of a polycrystalline n-layer of silicon is insulated with a layer of silicon dioxide. In such devices, due to the mismatch of the crystal lattices, defects are formed that worsen the parameters of semiconductor devices.

A known method of manufacturing a thin-film transistor [Application 225037 Japan, MKI H01L 21/336] by sequentially creating on the dielectric substrate, with the gate electrodes formed on it, a gate dielectric layer of silicon nitride, an amorphous silicon layer, and on a portion of the gate electrode on top of the amorphous silicon layer a silicon nitride region is formed. Then, without breaking the vacuum, a layer of amorphous silicon 100 nm and a silicon layer 30 nm thick doped with phosphorus are deposited. Source and drain electrodes are formed by removing part of the silicon layers.

The disadvantages of this method are:

- increased density of defects in structures;

- low manufacturability;

- the formation of mechanical stresses.

The problem solved by the invention: reducing the density of defects in semiconductor devices, ensuring manufacturability, improving the parameters of devices, improving quality and increasing the percentage of yield.

The problem is solved by forming an amorphous silicon film with a thickness of 430 nm in an RF glow discharge in silane at a substrate temperature of 250 ° C and subsequent implantation of fluorine ions with an energy of 25 keV, a dose of 10 ¹⁴ -5 · 10 ¹⁵ cm ^-2 and annealing in a nitrogen atmosphere at temperature of 200-220 ° C for 60 minutes Fluorine atoms act as interstitial acceptors, compensating for the n-impurity of phosphorus atoms in the contact areas and suppresses diffusion of aluminum during activation annealing.

The technology of the method consists in the following: in the manufacture of a thin-film transistor, highly doped single-crystal n ⁺ -type silicon wafers were used as a substrate. Then, a 110 nm thick silicon dioxide layer grown by thermal oxidation in dry oxygen at 1000 ° C was used as a gate insulator. Subsequently, films of amorphous silicon with a thickness of 430 nm were formed in an RF glow discharge in silane at a substrate temperature of 250 ° C and fluorine ions with an energy of 25 keV and a dose of 10 ¹⁴ -5 · 10 ¹⁵ cm ^{-2 were} implanted. After implantation, the samples were annealed in a nitrogen atmosphere at a temperature of 200-220 ° C for 60 min, and a passivating layer of silicon oxide with a thickness of 150 nm was deposited in a plasma of a gas mixture of SiH ₄ and N ₂ O at a temperature of 250 ° C in a ratio of gas flows of 15:85 . In this layer, the windows for the contacts of the source and drain were etched. Then, to create a thin n ⁺ amorphous silicon layer, phosphorus ions were implanted with an energy of 30 keV and a dose of 10 ¹⁶ cm ^-2 , the plates were metallized with aluminum and contacts were formed on them using photolithography. To form ohmic contacts, implantation annealing was performed at a temperature of 200 ° C for 30 min.

According to the proposed method, semiconductor devices were manufactured and investigated. The processing results are presented in the table.

Parameters of p / p structures made by standard technology Parameters of p / p structures made by the proposed technology Drift mobility, cm ² / V · s defect density, cm ^-2 Drift mobility, cm ² / V · s defect density, cm ^-2 2,3 4.8 · 10 ⁶ 4.7 2.5 · 10 ⁴ 3,1 4.110 ⁶ 6.0 2.210 ⁴ 4,5 2,810 ⁶ 8.8 1,110 ⁴ 2.7 4,510 ⁶ 5.3 2.7 · 10 ⁴ 4.2 3.0 · 10 ⁶ 8.1 1.3 · 10 ⁴ 3,7 3.9 · 10 ⁶ 7.2 1.7 · 10 ⁴ 2.9 4.210 ⁶ 5.5 2.0 · 10 ⁴ 4.4 2.7 · 10 ⁶ 8.3 1.2 · 10 ⁴ 3.8 3.7 · 10 ⁶ 7.5 1.8 · 10 ⁴ 2,4 4.7 · 10 ⁶ 4.6 2.4 · 10 ⁴ 4.1 3.1 · 10 ⁶ 7.9 1.610 ⁴ 3.9 4.210 ⁶ 7.4 2.210 ⁴ 2.6 4,510 ⁶ 4.8 2.5 · 10 ⁴ 3.3 4.0 · 10 ⁶ 6.5 1.9 · 10 ⁴

Experimental studies have shown that the yield of suitable devices on a batch of plates formed in the optimal mode increased by 17.8%.

Effect: reducing the density of defects, ensuring manufacturability, improving the parameters of devices, improving quality and increasing the percentage of yield.

The stability of the parameters over the entire operational temperature range was normal, and met the requirements.

The proposed method of manufacturing a thin-film transistor by forming an amorphous silicon film 430 nm thick in an RF glow discharge in a silane at a substrate temperature of 250 ° C, followed by implantation of fluorine ions with an energy of 25 keV, a dose of 10 ¹⁴ -5 · 10 ¹⁵ cm ^-2 and annealing in nitrogen atmosphere at a temperature of 200-220 ° C for 60 minutes allows you to increase the percentage of suitable devices and improve their reliability.

Claims (1)

A method of manufacturing a thin film transistor, including the formation of gate electrodes, source and drain contacts, isolating the gate with a layer of silicon dioxide, characterized in that highly doped single crystal silicon wafers n are used as a substrate⁺-type, then 110 nm thick silicon dioxide layer grown by thermal oxidation in dry oxygen at 1000 ° C is used as a gate insulator, then films of amorphous silicon 430 nm thick are formed in the RF glow discharge in silane at a substrate temperature of 250 ° C and ions are implanted fluorine with an energy of 25 keV and a dose of 10^fourteen-5 · 10^fifteen cm^-2 after implantation, the samples are annealed in a nitrogen atmosphere at a temperature of 200-220 ° C for 60 min, a passivating layer of silicon oxide with a thickness of 150 nm is deposited in a plasma of a SiH gas mixture_four and N₂O at a temperature of 250 ° C in a ratio of gas flows of 15:85, then to create a thin n⁺ amorphous silicon layer implantation of phosphorus ions with an energy of 30 keV and a dose of 10¹⁶ cm^-2.