RU2541899C1 - Phase discriminator - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: introduction of hysteresis into discriminator curve of proportional channels excludes the situation when permit and inhibit to transfer data from proportional outputs of the discriminator is given at the same difference of phases. The phase discriminator comprises input of reference oscillation In2 and input of analysed oscillation In1; the proportional outputs are Out1 and Out2, while sign outputs are Out3 and Out4. Diagram of the discriminator includes the following: AND-NO gates 1-5, 13-16, RS-triggers 6, 7, 17, delay elements 8, 9, inverter 10, differentiating circuit 11 and pulse generators 12, 18, 19.

EFFECT: improved accuracy of phase difference at simultaneous use of sign and proportional outputs.

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Description

The invention relates to radio engineering and can also be used in discrete automation systems to obtain information about the sign and magnitude of the phase difference of two pulsed oscillations of close frequencies. The invention can find the greatest application in phase-locked loop systems (PLL) as a determinant of the phase mismatch of the reference and adjustable oscillations.

There are discriminators that generate information about the sign or magnitude (module) of the phase mismatch of oscillations, as well as information about both of these parameters at the same time. As sign discriminators of pulsed oscillations with digital logic levels, you can use the D-trigger, triggered by the difference in the reference oscillation at the C-input, to the D-input of which the analyzed oscillation is applied, or discriminator [1], performed on logic elements. Digital discriminators that generate information about the magnitude of the phase mismatch of two pulsed oscillations are performed on an asynchronous RS-trigger [2], an unequal scheme (adder modulo 2) [3]. As a rule, modular discriminators generate information only on the magnitude of the phase difference, but do not reflect information on its sign.

Discriminators that form information about the sign and magnitude of the phase difference of pulsed oscillations include digital phase discriminators [4, 5]. These discriminators generate information about both the sign (at the sign outputs) and the magnitude of the phase mismatch of the oscillations (at the modular (proportional) outputs). Moreover, the signals at the proportional outputs of such discriminators contain information about both the magnitude and sign of the measured phase difference. The value of the phase difference is determined by the duration of the pulses generated at the proportional outputs of the discriminator, and the sign is determined by the one on which of the two proportional outputs these pulses appear.

The discriminator described in [5] has modular outputs with an adjustable deadband. In it, with large values of the phase mismatch of oscillations, information is generated both on the sign and proportional discriminator outputs. With a small value of the phase difference due to the influence of the dead zone, there is an automatic prohibition of the issuance of information from the proportional outputs of the discriminator. In this case, the voltage at the sign outputs continues to reflect the sign of the phase difference. The discriminator [5], having a deadband in the formation of proportional values of the phase mismatch of the signals, is selected as a prototype.

When using a discriminator with a dead zone in the PLL system, the control loop of which simultaneously uses information from both the sign and the proportional outputs of the phase discriminator, an error arises in estimating the phase difference Δφ.

The causes of the error are as follows.

With large values of the measured phase difference, the discriminator generates signals at both its sign and proportional outputs. Moreover, if the sign of Δφ does not change, but only the magnitude of the phase difference changes, a change in the duration of the pulses reflecting the value of Δφ occurs at the proportional outputs of the discriminator, and the voltage generated at the sign outputs remains unchanged. With the simultaneous use of voltages from the discriminant sign and proportional outputs, the contribution of the sign output voltage to the combined signal reflecting the phase difference can be compensated only for a certain Δφ value by introducing a specific deadband into the characteristic of the proportional channels. If after this the value of the phase difference changes, then the total signal will no longer accurately reflect the real value of Δφ.

In addition, in order to ensure a wide capture bandwidth of the PLL system, in which the discriminator is used [5], the effect generated in the control loop based on signals from proportional outputs is made more intense than the effect generated on the basis of signals from sign outputs. As the magnitude of the phase mismatch of the oscillations analyzed by the discriminator decreases, the influence of signals from the proportional outputs decreases, since the duration of the pulses carrying information about the magnitude of the phase difference decreases. When Δφ reaches the value determined by the deadband Δφ of the _{SC of the} proportional channel of the phase discriminator, the modular discriminator outputs are disabled, that is, information from them is not output. Further control in the PLL system is carried out only under the influence of signals generated at the sign outputs. In order to obtain a small steady-state phase error, they try to make the influence of signals from sign outputs significantly less than the effects of signals from proportional outputs. This is ensured by the transmission of signals from the sign outputs through the link with a transmission coefficient substantially less than unity [6].

Let us assume that at the moment when the phase difference Δφ reaches the boundary value of the dead band (| Δφ | = | Δφ _ZN |) in the PLL, the frequency detuning becomes equal to kul. If the filtering link of the PLL system does not have astatism, then further phase adjustment to the value Δφ → 0 does not occur, since the voltage at the output of the filtering link does not change at a constant value of the sign of the phase difference. The latter is due to the fact that there is no signal at the proportional output, and the voltage reflecting the sign of Δφ is constant.

If the filter used in the PLL system has astatism, then even with full compensation of the frequency detuning between the analyzed oscillations to the moment when | Δφ | = | Δφ _ЗН |, further phase adjustment from | Δφ | = | Δφ _ЗН | up to Δφ = 0 will cause the formation of an additional frequency detuning in the system. Subsequent compensation of the generated frequency detuning due to the action of signals of the discriminator sign outputs can cause the phase difference Δφ to go beyond the [-Δφ _ZN , Δφ _ZN ] deadband. The increase | Δφ |> | Δφ _ZN | will enable the proportional outputs to work. The impact from the proportional outputs again compensates for the frequency detuning at | Δφ | = | Δφ _ZN | to zero. Further, the process can take a cyclic character, which does not lead to a decrease in the phase error Δφ to a value tending to 0. That is, an additional disadvantage of the discriminator [5] is that the prohibition and resolution of the proportional outputs occur at the same value of the phase difference.

Thus, the disadvantage of the prototype is that in it, at large values of the measured phase difference, the simultaneous output of information is realized both on the proportional and symbolic outputs of the discriminator. This leads to an error in the estimation of Δφ. In addition, the disconnection and connection of the proportional outputs occurs at the same value | Δφ | = Δφ _ZN , which, when using a discriminator in the control loop, can cause oscillatory processes.

The invention consists in the following.

- характеристика сигнала, формируемого на пропорциональном выходе, при положительной разности фаз (фиг.1, а) и $$x_{мод}^{-}$$

- характеристика сигнала, формируемого на пропорциональном выходе, при отрицательной разности фаз (фиг.1, б). Активные уровни выходных сигналов дискриминатора соответствуют уровню логического пуля. Отключенное состояние пропорциональных выходов соответствует установке на них уровней логической единицы. Ширину гистерезиса |Δφ_ЗН_₂-Δφ_ЗН_₁| можно выбрать в соответствии с параметрами системы ФАПЧ, в которой фазовый дискриминатор применяется.To increase the accuracy of the estimation of the phase difference while using the sign and proportional outputs of the discriminator, it is proposed for | Δφ |> | Δφ _ZN | allow only proportional outputs of the discriminator to work (sign outputs must be turned off), and when | Δφ | ≤ | Δφ _ZN | disable proportional outputs and connect sign outputs. Also, so that in the process of holding the phase by the control loop (PLL) near | Δφ _ЗН | there was no inclusion of proportional outputs, in the characteristic of switching the outputs of the discriminator it was necessary to introduce a hysteresis that would ensure that the proportional outputs are switched off at | Δφ | <| Δφ _ЗН _ ₁ |, and their reconnection at | Δφ | = | Δφ _ЗН _ ₂ |, and | Δφ _ZN _ ₁ | <| Δφ _ZN _ ₂ |. The hysteresis of the proportional output characteristics is shown in FIG. 1, where $$x_{m\mathrm{about}d}^{+}$$

- the characteristic of the signal generated at the proportional output, with a positive phase difference (Fig. 1, a) and $$x_{m\mathrm{about}d}^{-}$$

- the characteristic of the signal generated at the proportional output, with a negative phase difference (Fig. 1, b). The active levels of the discriminator output signals correspond to the level of the logical bullet. The disconnected state of the proportional outputs corresponds to the setting of logical unit levels on them. The width of the hysteresis | Δφ _ZN _ ₂ -Δφ _ZN _ ₁ | can be selected in accordance with the parameters of the PLL system in which the phase discriminator is used.

The simultaneous use of the proportional and symbolic outputs of the discriminator with the properties described above in the PLL allows reducing the value of Δφ to the value | Δφ | <| Δφ _ЗН _ ₁ | due to the influence of signals from the proportional outputs of the discriminator, and further tuning using signals from the discriminant output . The use in the process of adjusting signals only from significant outputs is able to lead to the complete development of the existing phase mismatch to a value Δφ tending to 0 [6].

The aim of the invention is:

1) improving the accuracy of evaluating the discriminator of the phase difference with the integrated use of significant and modular outputs of the discriminator;

2) an exception to the situation in which the permission and prohibition of the issuance of information from the proportional outputs of the discriminator is performed at the same value of the phase difference.

These goals are achieved by improving the invention according to copyright certificate No. 1568207 [5] by introducing into its circuit two additional pulse shapers, four additional AND-NOT circuits, an additional trigger and corresponding additional connections.

Consider the structure and principle of operation of the proposed device. Figure 2 shows the electrical circuit of the proposed phase discriminator, and figure 3 is a timing diagram explaining its operation when Δφ> 0.

The phase discriminator shown in figure 2, contains the first, second, third, fourth and fifth elements NAND 1-5, the first and second triggers 6 and 7, the first and second delay elements 8 and 9, the inverter 10, the differentiating circuit 11 , pulse shaper 12, first, second, third and fourth additional AND-NOT elements 13-16, additional trigger 17, first and second additional pulse shapers 18 and 19.

Phase discriminator works as follows.

(сигнал на инверсном выходе $$x_Z^{-}=0$$

), если передний фронт импульсов сигнала х_А опережает передний фронт импульсов сигнала х_Б. Когда передний фронт импульсов сигнала х_А отстает от переднего фронта импульсов сигнала х_Б, на инверсном выходе второго триггера 7 формируется сигнал $$x_Z^{-}=1(x_Z^{+}=0)$$

. На Фиг.3 представлен случай, когда передний фронт импульсов сигнала х_А опережает передний фронт импульсов х_Б. В этом случае имеет место фазовое рассогласование одного знака, отображаемое на прямом выходе второго триггера как $$x_Z^{+}=1$$

(фиг.3, с).The input signal of the first AND-NOT 1 element receives a pulse signal x _A (Fig. 3, a), and the second pulse signal x _B (Fig. 3, b) is used as the reference signal at the input of the first delay element 8. Both of these signals have the same frequencies. From the output of the first delay element 8, the signal x _n (FIG. 3, c) is supplied to the second input of the first AND-NOT 1 element and the input of the second delay element 9. The output of the first AND-NOT 1 element is connected to the S-input of the first trigger 6, and The R-input of the trigger is connected to the input of the first delay element 8 and the first inputs of the second 2 and third 3 elements AND NOT. The second inputs of elements 2 and 3 are connected to the direct and inverse outputs of trigger 6, respectively. The third inputs of the AND-NOT 2 and 3 elements are connected to the output of the second delay element 9. The output of the second AND-NOT 2 element is connected to the S-input of the second trigger 7, and the output of the third AND-NOT 3 element to the R-input of the second trigger. A signal is generated at the direct output of the second trigger 7 $$x_Z^{+}=\mathrm{one}$$

(signal at inverse output $$x_Z^{-}=0$$

) if the leading edge of the signal pulses x _{A is} ahead of the leading edge of the signal pulses x _B. When the leading edge of the signal pulses x _A lags behind the leading edge of the signal pulses x _B , a signal is generated at the inverse output of the second trigger 7 $$x_Z^{-}=\mathrm{one}(x_Z^{+}=0)$$

. Figure 3 presents the case when the leading edge of the pulses of the signal x _{A is} ahead of the leading edge of the pulses x _B. In this case, there is a phase mismatch of one sign, displayed on the direct output of the second trigger as $$x_Z^{+}=\mathrm{one}$$

(Fig. 3, c).

At the output of the first AND-NOT 1 element with the simultaneous interaction of the signals x _A and x _n , a sequence of pulses x _{B is formed} (Fig. 3, d) with a logic zero level, the duration of which τ _{Ф is} proportional to the phase mismatch Δφ of the pulses x _A and x _B. The signal x _B from the output of the first AND-NOT 1 element is fed to the inputs of the inverter 10 and the differentiating circuit 11. At the output of the differentiating circuit, short pulses x _dts are generated (Fig. 3, g), which are a reaction to changes from 1 to 0 of the pulse oscillation x _B . Pulses are formed at the beginning of each of the pulses x _In . But based on the pulses x _{dts, the} circuit of the first pulse shaper 12 produces pulses x _f1 (Fig. 3, h) with a logic zero level of duration τ ₁ . Also, on the basis of pulses x _dts , using the first 18 and second 19 additional pulse shapers, pulses x _f2 (Fig. 3, i) and x _f3 (Fig. 3, k) with durations of τ ₂ and τ _{3 are} generated. The duration τ ₂ pulses x _f2 determines the value of the dead zone of the modular characteristics of the discriminator. Impulses x _f2 have a logical unit level, and pulses x _f3 have a logical zero level. The durations of the pulses generated by the shapers are correlated as follows: τ ₁ <τ ₂ <τ ₃ .

The signal x _m (Fig.3, d), obtained by inverting the signal x _In , is fed to the first inputs of the fourth 4 and fifth 5 elements AND NOT. The second inputs of the fourth and fifth elements are NOT connected to the direct and inverse outputs of the second trigger 7, which generates information about the sign of the phase mismatch of the pulses x _A and x _B ). The third inputs of the elements AND 4 and 5 are connected to the output of the first pulse shaper 12.

(фиг.3, п) $$x_{мод}^{-}$$

(фиг.3, р) четвертого 4 и пятого 5 элементов И-НЕ, являющихся модульными выходами фазового дискриминатора.The inputs of the first additional AND-NOT 13 element are connected to the outputs of the first AND-NOT 1 element and the first additional pulse shaper 18. At the output of the AND-NOT 13 element, a pulse x _d3 is generated (Fig. 3, l) with a logic level of zero, when for duration τ _{F x} pulse condition ₁ τ <τ _F <τ _2. This corresponds to the fact that the pulse duration does not exceed the width of the hysteresis zone. The inputs of the second additional AND-NOT 14 element are connected to the outputs of the inverter 10 and the second additional pulse shaper 19. At the output of the AND-NOT 14 element, pulses x _d4 are generated (Fig. 3, m) with a logic level of zero, when the duration τ _F pulses x _m (Fig. 3, e), which are the inversion of pulses x _B (Fig. 3, d), exceeds the duration τ ₃ pulses x _f3 generated by the second additional pulse shaper 19. Pulses x _d4 switch the additional trigger 17 to a state in which inverse output signal x set _n (Fig.3, n) with the level of a logical unit. This allows the generation of signals at the outputs. $$x_{m\mathrm{about}d}^{+}$$

(figure 3, p) $$x_{m\mathrm{about}d}^{-}$$

(Fig. 3, p) of the fourth 4 and fifth 5 NAND elements, which are modular outputs of the phase discriminator.

(фиг.3, с) и $$x_{zn}^{-}$$

(фиг.3, т). Активные значения сигналов соответствуют уровням логического нуля.The pulses X _d3 (figure 3, l), formed when the condition τ ₁ <τ _Ф <τ ₂ is fulfilled, switch the additional trigger 17 to a state in which a signal x _{З is} set on its direct output (figure 3, o) s logical unit level. This signal permits the operation of the third 15 and fourth 16 additional NAND elements, the outputs of which are the discriminator's significant outputs. Signals are formed on them. $$x_{zn}^{+}$$

(figure 3, c) and $$x_{zn}^{-}$$

(Fig. 3, t). Active signal values correspond to logical zero levels.

Timing diagrams explaining the operation of the phase discriminator with negative phase mismatches (Δφ <0) are presented in Fig.4. The processes of the same name in FIGS. 3 and 4 are denoted by the same letters.

BIBLIOGRAPHIC LIST

1. A.S. 1279047 USSR, MKI H03D 13/00, G01R 25/00. Phase discriminator / V.F. Lonely. No. 3909009 / 24-09; claimed 04/30/85; publ. 12/23/86 in BI No. 47.

2. Digital phase synchronization systems / Ed. M.I. Zhodzishsky. - M .: Owls. Radio, 1980 .-- 208 p.

3. Shilo V.L. Functional analog integrated circuits. - M .: Radio and communications, 1982. - 128 p.

4. A.S. 1432724 USSR, MKI H03D 13/00, G01R 25/00. Phase discriminator / V.F. Odinokov, S.I. Slaves. No. 4212180 / 24-09; claimed March 19, 87; publ. 10.23.88 in BI No. 39.

5. A.S. 1568207 USSR, MKI H03D 13/00. Phase discriminator / V.F. Odinokov, S.I. Slaves. No. 4,374,505; claimed 05.02.88; publ. 05/30/90 in BI No. 20.

6. Kholopov S.I. Analysis of the PLL relay system with resettable integrators // Bulletin of the Ryazan State Radio Engineering University. 2011. No4 (issue 38). S.50-54.

Claims (1)

A phase discriminator containing the first AND-NOT element, the first input of which is the first input of the phase discriminator, and the output is connected to the S-input of the first trigger, whose R input, connected to the second input of the phase discriminator, is connected to the first inputs of the second and third AND elements -NOT and the input of the first delay element, the output of the first delay element is connected to the second input of the first AND element and the input of the second delay element, the output of the second delay element is connected to the second inputs of the second and third elements AND , the third inputs of the second and third elements AND are NOT connected to the direct and inverse outputs of the first trigger, respectively, the output of the second element is NOT connected to the S-input, and the output of the third element is NOT connected to the R-input of the second trigger, the output of the first element AND-NOT is also connected to the inputs of the inverter and the differentiating circuit, the output of which is connected to the input of the pulse shaper, the output of the shaper is connected to the first inputs of the fourth and fifth AND-NOT elements, the outputs of which are the first and second (modular) discriminant outputs and accordingly, the second inputs of the fourth and fifth AND-NOT elements are connected to the inverter output, the third input of the fourth AND-NOT element is connected to the direct output, and the third input of the fifth AND-NOT element is connected to the inverse output of the second trigger, characterized in that the first and second additional pulse shapers are introduced, the inputs of which are connected to the output of the differentiating chain, the first additional NAND element, the first input of which is connected to the output of the first NAND element, and the second input is connected to the output of the first additional pulse shaper, the second additional NAND element, the first input of which is connected to the output of the inverter, and the second input is connected to the output of the second additional pulse shaper, an additional trigger, the S-input of which is connected to the output of the first additional NAND element, and R- the input is connected to the output of the second additional AND-NOT element, the inverse output of the additional trigger is connected to the fourth inputs of the fourth and fifth AND-NOT elements, and the direct output of the additional trigger is connected to the first inputs the third and fourth additional AND-NOT elements, the second inputs of which are connected to the direct and inverse outputs of the second trigger, respectively, the outputs of the third and fourth additional AND-NOT elements are the third and fourth (sign) discriminator outputs.

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