RU2439744C1 - Manufacturing method of shf ldmos transistors - Google Patents

Abstract

FIELD: electricity. ^ SUBSTANCE: manufacturing method of SHF LDMOS transistors includes growth of thick field dielectric at surface of high-ohmic epitaxial p- -layer of source silicone p-p+-substrate at periphery of transistor configurations, formation of source p+-junctions and p-wells of transistor cells in epitaxial p- -layer of substrate not covered with field dielectric, growth of gate dielectric and formation of polysilicone electrodes of transistor cells gate in the form of narrow lengthwise teeth of rectangular section with close adjoining tapped contact pads from source side over p-wells, creation of high-alloy n+-areas of sink, source and low-alloy n-area of transistor cells by introduction and further diffusion redistribution of donor dopant using gate electrodes as protective mask, formation of metal electrodes of sinking, source, screens and buses shunting gate electrodes of transistor cells through tapped contact pads at substrate face and common metal source electrode of transistor configuration at backside, the first degree of low-alloy multistage n-area of transistor cell source is formed after formation of source p+-junctions by introduction of donor dopant to epitaxial p--layer of substrate without usage of protective masks, p-wells, sink and source areas of transistor cells are created with use of additional dielectric protective mask identical in configuration and location of lengthwise teeth of polysilicone gate electrode without tapped contact pads adjoining to them, simultaneously with p-wells similar areas are formed at edges of low-alloy n-area of transistor cells sink and gate electrodes with tapped contact pads adjoining to teeth are formed after removal of additional dielectric protective mask and subsequent growth of gate dielectric, at that width of polysilicone gate electrode teeth are selected so that it exceeds length of transistor cell induced channel per overlay error value. ^ EFFECT: improvement in electric parameters of powerful silicone generating SHF LDMOS transistors, increase of their resistance to ionising radiation exposure and increase of production output in percents. ^ 7 dwg

Description

The invention relates to electronic semiconductor technology, in particular to methods for manufacturing microwave microwave power silicon field LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistors, and can be used to create a new generation of electronic equipment based on them.

A known method of manufacturing microwave LDMOS transistors, selected as an analogue (US patent No. US 6707102 B2 "Semiconductor device including an insulated gate type field effect transistor and method for fabricating the same", published March 16, 2004), including growing a thick field dielectric on the surface of the high-resistance epitaxial p ^- layer of the initial silicon p ^- p ⁺ substrate on the periphery of transistor structures, the creation of the source p ⁺ jumper of transistor cells in the volume of the epitaxial p ^- layer of the substrate not covered by a field dielectric, growing a gate insulator on the surface of the epitaxial layer of the substrate, the formation of a layer of polysilicon and tungsten silicide (polycide) electrodes of the gate electrodes of transistor cells in the form of narrow longitudinal teeth of rectangular cross section, previously created on the gate dielectric, creating a p-channel (p-pocket), highly doped n ⁺ drain regions, and a lightly doped n-region of the drain of transistor cells by sequentially introducing acceptor and donor impurities into the substrate using gate electrodes as a protective mask and subsequent diffusion redistribution of embedded impurities, the formation of metal screens, drain electrodes and the source of transistor cells on the front side of the substrate and a common metal source electrode on its back side.

One of the main drawbacks that limit the operating frequency range of LDMOS transistors manufactured in this way is the gate circuit time constant due to the rather high resistance of silicides of tungsten, titanium, cobalt, and other refractory metals (1 ÷ 2 Ohm / □) used for shielding polysilicon.

There is another method for manufacturing microwave power silicon LDMOS transistors (Philips BLF2022-90 power MOSFET structural analysis. 3685 Richmond Road, Suite 500, Ottawa, ONK2H587, Canada, 06/17/2004), according to which the lightly doped n-region of the drain instead of a homogeneous cell, a multistage one was made, and narrow (0.82 μm) polycide (WSi / Si ^∗ ) gate teeth 0.44 μm thick and 330 μm long through contact windows 0.35 open in a thick (~ 1 μm) dielectric μm × 330 μm to reduce the gate circuit constant along the entire length are coated with a three-layer metal coating: Ti (0.08 μm) / TiW (0.14 μm) / Au (1.24 μm). This made it possible to implement devices with a working frequency range of up to 2.0 ÷ 2.2 GHz and breakdown drain voltages U _{from samples} = 65 V. However, the implementation of the second analogue method in industrial production is significantly limited due to the need to have expensive precision technological equipment and exclusive ”technological operations for the formation of a gate assembly of transistor cells with a percentage of suitable structures on the wafer acceptable for organizing cost-effective production of products, which is its main drawback.

As a prototype, a method for manufacturing microwave LDMOS transistors (Isao Yoshida, "2-GHz Si power MOSFET technology" - International Electron Devices Meeting, 1997, Washington, Technical Digest, 7-10 Dec. 1997), including the formation of source p ⁺ jumpers, was selected and p-pockets of transistor cells in a high-resistance epitaxial p ^- layer of the initial silicon p ^- p ⁺ substrate, growing a gate dielectric on the surface of the epitaxial layer, forming polycide (WSi / Si ^* ) gate electrodes of transistor cells in the form of narrow longitudinal teeth of rectangular cross section with adjacent to them from the side the source of the branched contact pads above the p-pockets, the formation of a lightly doped n-region of the drain of transistor cells by overcompensating acceptor impurities in the gate of the peripheral part of the p-pocket extending beyond the polycide electrode of the gate, the creation of highly doped n ⁺ regions of the drain and the source of transistor cells by introducing a donor impurity into the substrate using polycide gate electrodes and photoresist layers as a protective mask and subsequent iffuzionnogo redistribution of the implanted impurity, the formation of metal electrodes the drain and source buses shunt tine polycide gate transistor cells through the adjacent branched from the source pads on the front side of the metal substrate and the common source electrode of the transistor structure at its rear side. In a similar fashion, samples of silicon microwave LDMOS transistors were made, which had threshold voltages of V _pores ≤0.5 V, breakdown voltage of the drain U _{with samples} = 16 V and a frequency f = 2.0 GHz with a supply voltage of drain U _{with pit} = 3.6 V delivered power to the load P _{o out} = 1 W with a power gain K _ur = 6.5 dB and a drain coefficient of the drain circuit η _c = 34% [3].

The main disadvantages of the prototype method are:

- the impossibility of realizing the values of U _{z pores} , U _{c samples} , U _{c pits} characteristic of high-power silicon microwave LDMOS transistors;

- the inability to implement the optimal for high-power microwave LDMOS transistors multi-stage configuration of a lightly doped n-region drain of transistor cells;

- the impossibility of realizing the same length of the induced n-channel over the entire length of the gate teeth of transistor cells (in the region of dislocation of branch contact pads adjacent to the gate teeth, the channel is longer);

- low resistance made by the prototype method of devices to the effects of ionizing radiation.

The technical result of the present invention is the creation of high-power silicon microwave LDMOS transistors with improved electrical parameters, increased resistance to ionizing radiation and a higher yield of suitable structures.

The technical result is achieved by the fact that in the known method of manufacturing microwave LDMOS transistors, including growing a thick field dielectric on the surface of a high-resistance epitaxial p ^- layer of the original silicon p ^- p ⁺ substrate on the periphery of the transistor structures, the formation of source p ⁺ jumpers and p-pockets transistor cells in the epitaxial p ^- layer of the substrate not coated with a field dielectric, growing a gate dielectric and forming polysilicon gate electrodes of transistor cells in the form of narrow longitudinal teeth of rectangular cross section with a number of branched contact pads adjacent to them from the source side above the p-pockets, creation of highly doped n ⁺ -regions of the drain, source and lightly doped n-region of the drain of transistor cells by incorporating into the substrate and subsequent diffusion redistribution of the donor impurity using electrodes shutter as a protective mask, the formation of metal electrodes of drain, source, shields and buses shunting the gate electrodes of transistor cells through the response lennye contact pads on the front side of the metal substrate and the common source electrode of the transistor structure at its rear side, a first stage multi lightly doped n-drain region of transistor cells is formed after the formation of source p ⁺ -peremychek by introducing a donor impurity in the epitaxial p ^- -layer substrate without using protective masks, p-pockets, stock and source regions of transistor cells are created using an additional dielectric protective mask identical in configuration radios and the location of the longitudinal teeth of the polysilicon gate electrode without branching contact pads adjacent to them, simultaneously with p-pockets form similar regions at the ends of the lightly doped n-region of the drain of transistor cells adjacent to the thick field dielectric of the transistor structure, and the gate electrodes of transistor cells with to the teeth, branched contact pads are formed after removal of an additional dielectric protective mask and subsequent cultivation of the subterfuge polar dielectric, wherein the width of the polysilicon gate electrode teeth is selected such that it by the amount of error induced alignment exceed the channel length of transistor cells.

Comparative analysis with the prototype shows that the claimed method is characterized by the presence of a new set and sequence of technological operations: the use of an additional dielectric protective mask of a given configuration, formed at a certain stage of the technological route at a specific place in the created transistor LDMOS structure to form a p-pocket, source and drain areas of transistor cells; the formation of a polysilicon gate electrode with a regulated width of the longitudinal gate teeth above the induced n-channel after creating the channel, source, drain areas of the transistor cells and the subsequent removal of an additional dielectric protective mask and growing a gate dielectric on the surface of the epitaxial layer of a silicon p ^- p ⁺ substrate; the formation of the first step of a multistage lightly doped n-region of the drain of transistor cells to create p-pockets by overcompensating the acceptor impurity by the introduced donor impurity in the epitaxial p ^- layer of the substrate, and not in the p-pocket; simultaneous formation with p-pockets of similar regions at the ends of lightly doped n-regions of the drain of transistor cells adjacent to the thick field dielectric of the transistor structure. Thus, the claimed method meets the criteria of the invention of "novelty."

The creation of the channel, source, and drain regions of transistor cells using an additional dielectric protective mask formed at the site of a future dislocation in the transistor LDMOS structure of gate teeth of a polysilicon gate electrode without branch contact pads adjacent to them and having a configuration identical to the gate teeth and comparable topological dimensions, allows in contrast to the prototype method, to realize the same length of the induced n-channel along the entire length of the gate teeth, in t m including in the areas where the adjacent pendent pads.

The formation in the inventive method at the beginning of the first stage of a lightly doped multistage n-region of the drain of transistor cells by introducing a donor impurity into the epitaxial p ^- layer of the substrate without the use of protective masks, and then p-pockets and at the same time similar regions at the ends of lightly doped n-regions the drain of transistor cells adjacent to the thick field dielectric of the transistor structure by overcompensating the donor impurity introduced into the substrate by an acceptor impurity allows to read independently the optimum level of doping of the p-pocket and the lightly doped multi-stage sink n-region of transistor cells required to realize the values of U _pores , U _{c samples} , U _c pits typical for high-power microwave LDMOS transistors, and also significantly simplify compared to prototype and methods-analogues technological process of manufacturing transistor structures.

The formation of the gate dielectric and polysilicon electrodes of the gate of the transistor cells in the present method after creating the channel (pocket), drain and source areas allows you to:

- to use as a gate electrode not only polysilicon and polycides, but also refractory metals (Mo and others) and their silicides;

- improve the quality of the gate dielectric and increase, in comparison with the prototype and analogous methods, the percentage of yield of suitable structures on the wafer and resistance to ionizing radiation.

In the manufacture of transistor structures according to the claimed method, the width of the longitudinal teeth of a polysilicon or polycide gate electrode of transistor cells must exceed the length of the induced channel by the value of the alignment error, which ensures the formation of the induced n-channel under the gate teeth along their entire length when a positive voltage is applied to the gate electrode of the transistor structure .

In the present invention, the new combination and the sequence of technological operations allows, in contrast to the prototype method, to provide breakdown drain voltage U _{c samples} = 40 ... 120 V, threshold voltage U s _pore = 2 ... 6 V, supply voltage U drain _p = 12, 5 ... 50 V and power delivered to the load P _o = 5 ... 200 W, inherent to high-power microwave LDMOS transistors with operating frequency ranges up to 2.0 ... 3.5 GHz, that is, it exhibits a new technical property. Therefore, the claimed method meets the criterion of "inventive step".

In figures 1 ... 7 shows the main stages of the manufacture of microwave LDMOS transistor structures according to the invention, where the following notation is introduced:

1 - initial silicon p ^- p ⁺ substrate;

2 - a thick field dielectric at the periphery of transistor structures;

3 - diffusion source p ⁺ jumper of transistor cells in a high-resistance p ^- layer of the substrate;

4, 5, 6 - the first, second and third steps of a lightly doped n-region of the drain of transistor cells, respectively;

7 - an additional dielectric protective mask formed on the surface of the epitaxial p ^- layer of the substrate;

8 - a protective layer of photoresist over a lightly doped n-region of the drain of transistor cells;

9, 9 ′ - p-pockets of transistor cells after the introduction of acceptor impurity ions into the high-resistance p ^- layer of the substrate and, accordingly, after diffusion acceleration of the introduced impurity;

10 — regions similar to p-pockets, formed simultaneously with them at the ends of a lightly doped n-region of the drain of transistor cells in contact with a thick field dielectric of a transistor structure;

11 - a protective layer of photoresist;

12, 13 - contact windows of the drain and source, opened in the protective layer of the photoresist (11);

14, 15 — highly doped n ⁺ regions of the drain and source of transistor cells, respectively;

16 - gate dielectric;

17 - longitudinal teeth of a polysilicon or polycide gate electrode of transistor cells;

18 - branching contact pads adjacent to the longitudinal bolt teeth from the source side;

19 - interlayer dielectric;

20, 21, 22 — contact windows opened in an interlayer dielectric, respectively, over highly doped n ⁺ regions of the drain, source, and branch sites of a polysilicon or polycide gate electrode of transistor cells;

23, 24 - metal electrodes of the drain and source of transistor cells;

25 - metal tires shunting the longitudinal teeth of a polysilicon or polycide gate electrode of transistor cells through branch pads adjacent to them from the source side;

26 - metal shielding electrodes of transistor cells;

27 is a common metal electrode of the source of the transistor structure on the back side of the substrate;

28 - induced n-channel.

Example

Using a specially designed set of photomasks, samples of transistor structures were manufactured according to the claimed method with a size of 1.0 mm × 4.2 mm with an induced n-channel and a lightly doped three-stage n-region of the drain of transistor cells of length L _k = 0.75 μm and L _n- - = 4.5 μm, respectively, and the total length (width) of the channel W _k = 78.7 mm, which are the basis of high-power silicon microwave LDMOS transistors designed for the operating frequency range up to 2.0 GHz.

The method is as follows:

1. On the surface of the high-resistance epitaxial p ^- layer (ρ _ρ- = 8 ... 12 Ohm · cm, h _ρ- = 6 ... 8 μm) of the initial silicon p ^- p ⁺ substrate (1) a thick field dielectric is formed by local thermal oxidation of silicon (2) at the periphery of the transistor structures, implantation of boron ions and subsequent diffusion redistribution of the embedded impurity create through source p ⁺ jumper wires (3) transistor cells in the volume of the epitaxial p ^- layer of the substrate, not covered with a thick field dielectric (2), and subsequent implementation phosphorus ions in the epitaxial layer th substrate without the use of protective masks form the first stage of the lightly doped n-region of the drain (4) of transistor cells - figure 1.

2. By introducing phosphorus ions into the substrate with a sequentially increasing dose, using the photoresist layers as a protective mask, create the second (5) and third (6) steps of the lightly doped n-region of the drain of transistor cells, silicon dioxide is grown by thermal oxidation of silicon on the surface of the epitaxial layer, form from grown silicon dioxide by photolithography at the site of the future dislocation of the longitudinal teeth of a polysilicon or polycide gate electrode of transistor cells an additional dielectric protection mask (7), cover the lightly doped n-region of the drain of transistor cells with a photoresist protective layer (8), p-pockets of transistor cells (9) are formed by implanting boron ions into the substrate and at the same time similar p-regions (10) at the ends of the lightly doped n-region of the drain of transistor cells adjacent to a thick field dielectric (2) of the transistor structure - figure 2, 3.

3. After removing the protective layer of the photoresist (8) from the front surface of the substrate, diffusion acceleration of the acceptor impurity is carried out in p-pockets (9 ′) - Fig. 4, a new layer of photoresist (11) is applied to the front side of the substrate, contact contacts are opened in it by photolithography windows (12) and (13) and implantation of a donor impurity (P, As,) into the substrate through the contact windows create highly doped n ⁺ regions of the drain (14) and the source (15) of transistor cells - Fig. 5.

4. The photoresist (11) and an additional dielectric protective mask (7) are removed from the front surface of the substrate, the gate dielectric (16) is grown on the surface of the epitaxial layer of the substrate by thermal oxidation of silicon, the gate dielectric is coated with a phosphorus doped polysilicon layer and formed from it by photolithography over with the ends of the p-pockets (9 ′), the longitudinal gate teeth of the transistor cells (17) together with the branching contact pads adjacent to the gate teeth from the source side (18), are deposited on faces the interlayer dielectric (19) by the photolithography method, the contact windows (20), (21), (22) are opened in the interlayer dielectric above the highly doped n ⁺ regions of the drain, source, and branch contact pads (18) of the polysilicon gate electrode of transistor cells - Fig.6.

5. A single-layer or multi-layer metal coating is applied to the interlayer dielectric (19) and the drain electrodes (23), source (24), shunt bus bars of a polysilicon gate electrode (25) and shields (26) of transistor cells are formed from it by photolithography. A common source electrode of the transistor structure (27) on the back side of the substrate was created when the crystal was soldered to the heat-removing surface of the ceramic-metal case using a gold gasket, and the induced n-channel (28) was formed at the ends of the p-pockets (9 ') adjacent to the gate dielectric ( 16) when a positive voltage is applied to the gate electrode of the transistor structure.

The yield of transistor structures (crystals) on the wafer made by the present method was about 40%. Suitable crystals mounted in a KT-25 type ceramic-metal casing had the following parameters: breakdown drain voltage U _{with sample} = 80 V (U _si = 0, I _s = 2 mA); drain current I _s = 8.0 A (U _si = 15 V, U _si = 10 V); threshold voltage U s _pore = 2.8 ... 5.0 V (U _s = 10 V, I _s = 20 mA); communicating capacity C ₁₂ = 1.82 pF (f = 1 MHz, U = 0 _bonds, U _B = 30); energy parameters, measured at a frequency of 2000 MHz, in class AB mode with a supply voltage across the drain U _{c pit} = 40 V - output power R _o = 38 W, power gain K _ur = 9.5 dB, the efficiency of the drain circuit η _c = 39%; shift of the threshold voltage when exposed to gamma radiation with a dose of D _γ = 10 ⁵ rad - ΔU for _pores ≤0.4 V.

Comparing the above parameters with the similar parameters of the known microwave LDMOS transistors having approximately the same structural and electrophysical parameters of the base crystal and designed for the same operating frequency range and power supplied to the load, we can draw the following conclusions:

1. The inventive method allows you to create powerful silicon microwave LDMOS transistors that are comparable with modern foreign analogues in basic electrical parameters, but with higher breakdown drain voltages and higher resistance to ionizing radiation.

2. The formation in the present method simultaneously with p-pockets of similar regions at the ends of lightly doped n-regions of the drain of transistor cells adjacent to the thick field dielectric of the transistor structure allows, other things being equal, to increase the breakdown breakdown voltage of the drain of microwave LDMOS transistors, and therefore, to ensure the possibility of their operation at supply voltages U drain _{c pit} = 40 V and higher.

3. The inventive method can significantly simplify the process of manufacturing high-power silicon microwave LDMOS transistors and more affordable technological equipment to provide a high percentage of yield structures on the plate.

The technical and economic efficiency of the proposed method consists in the possibility of improving the electrical parameters, increasing the breakdown voltage of the drain, increasing the supply voltage of the drain, radiation resistance and the percentage of suitable transistor structures on the wafer of commercially available high-power silicon LDMOS microwave transistors and creating a new generation of electronic equipment on their basis with higher technical and economic characteristics.

Claims (1)

A method of manufacturing microwave LDMOS transistors, including growing a thick field dielectric on the surface of a high-resistance epitaxial p ^- layer of an initial silicon p ^- p ⁺ substrate on the periphery of transistor structures, forming source p ⁺ jumpers and p-pockets of transistor cells in an epitaxial p ^- layer substrates with an uncovered field dielectric, growing a gate dielectric and forming polysilicon electrodes of the gate of transistor cells in the form of narrow longitudinal teeth of rectangular cross section with a row adjacent them thereto from the side of branch source contact pads of the p-pockets, the creation of high n ⁺ -regions drain lightly doped source drain region n-transistor cells by introducing into the substrate and subsequent redistribution donor impurity diffusion using the gate electrodes as a protective mask, forming metal electrodes of drain, source, shields and buses shunting the gate electrodes of transistor cells through branched contact pads on the front side of the substrate and of its metal electrode, the source of the transistor structure on its back side, characterized in that the first step of the lightly doped multi-stage n-region of the drain of transistor cells is formed after the formation of the source p ⁺ jumper by introducing a donor impurity into the epitaxial p ^- layer of the substrate without the use of protective masks, p -pockets, stock and source regions of transistor cells are created using an additional dielectric protective mask, identical in configuration and location to longitudinal teeth of a polysilicon gate electrode without branching contact pads adjacent to them, simultaneously with p-pockets they form similar regions at the ends of the lightly doped n-region of the drain of transistor cells adjacent to the thick field dielectric of the transistor structure, and the gate electrodes of transistor cells with branching contact adjacent to the teeth pads are formed after removal of an additional dielectric protective mask and subsequent growth of the gate dielectric, while the tooth width The gate polysilicon electrode is selected such that it exceeds the length of the induced channel of the transistor cells by the value of the alignment error.

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