RU2411579C1 - Device to generate and verify electronic image certified with digital water mark - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: device comprises Fourier transformation unit at the transmitting side, unit of electronic image division, generator of unit authenticator, unit of memory of authentication key, generator of digital water mark of unit, unit of integration of digital water mark and unit of transmission, on receiving side - unit of reception, generator of authenticator of received unit and unit of memory of authentication key. Proposed device may be used to establish authenticity of electronic images transmitted in up-to-date information-telecommunication systems.

EFFECT: increased security of electronic image verified with digital water mark against deliberate actions of violator to change content of electronic image.

18 dwg

Description

The invention relates to the field of telecommunications and information technologies, in particular to a technique for protecting the authenticity of electronic images, compressed by compression algorithms for electronic images, such as JPEG, MPEG-2, etc., and transmitted by the sender to the recipient through public transmission channels in which the intruder can take actions to impose false electronic images on the recipient. The claimed device can be used to establish the authenticity of electronic images transmitted in modern information and telecommunication systems.

Known devices for verifying the authenticity of electronic images based on the calculation and verification of the authenticator from the essential characteristics of the authenticated image, for example, the device for verifying the authenticity of electronic images according to US patent 6532541, IPC ⁷ H04L 9/00, 03/11/2003. This device includes a transmitting side and a receiving side. The transmitting side of the device is designed to form an electronic image authenticator (EI) and transmitting the EI and its authenticator over the transmission channel. The transmitting side of the device contains a separator into EI blocks, a first block for extracting essential characteristics, an authenticator generation unit, and an authentication key memory unit.

The input of the separator into EI blocks is the information input of the transmitting side of the device. The output of the separator into EI blocks is connected to the input of the first essential characteristics extraction unit, the output of which is connected to the first input of the authenticator forming unit, the second input of which is connected to the output of the authentication key memory block. The output of the authenticator forming unit is the output of the transmitting side of the device, and the separator into EI blocks, the first essential characteristics extraction unit, the authenticator forming unit and the authentication key memory unit are provided with control inputs to which corresponding control signals are received.

The receiving side of the device is designed to receive and verify the authenticity of the received EI. The receiving side of the device comprises a second essential characteristics extraction unit, an authenticator verification unit, an authentication verification key memory unit and a comparison unit. The first information input of the authenticator verification unit is the information input “received authenticator” of the receiving side of the device, the second input of the authenticator verification unit is connected to the output of the authentication key memory unit. The output of the authenticator check block is connected to the first input of the comparison block, the second input of which is connected to the output of the second block of extraction of essential characteristics, the information input of which is the information input “received electronic image” of the receiving side of the device. The output “confirmation of authenticity” of the comparison unit is the same output of the receiving side of the device, and the output of “non-authentication” of the unit of comparison is the same output of the receiving side of the device, the authenticator verification unit, the authentication verification key memory unit, the comparison unit and the second extraction unit are equipped with control inputs to which the corresponding control signals are received.

The disadvantages of this analogue are the need for additional transmission of the authenticator EI, as well as the low formalizability of the permissible difference in the essential characteristics of the EI when making a decision in the comparison unit on the authenticity of the accepted EI.

Also known is a device for generating and verifying a digitally watermarked EI, described, for example, in the book: Marvel L., Boncelet C., Retter J. Reliable Blind Information Hiding for Images // Proceedings of 2nd Workshop on Information Hiding. Lecture Notes in Computer Science. 1998, p. 89-94. A device for generating and verifying an electronic image certified by a digital watermark (CEH) comprises a transmitting side and a receiving side. The transmitting side of the device is designed to generate an electronic image verified by a digital watermark by calculating the digital watermark from the EI and integrating it into the same EI, as well as transmitting the EI verified by the digital watermark through the transmission channel. The transmitting side of the device comprises a first digital watermark memory block, a transmission conversion block, a first authentication key memory block, a first coding block, a modulator, an embedder key memory block, a modulating sequence generator, an interleaver, an interleaver key memory block, an adder, a quantizer, and a transmission block, moreover, the transmission conversion unit, the first coding unit, modulator, modulating sequence generator, interleaver and quantizer are provided with control inputs, which matured receives appropriate control signals.

The receiving side of the device is designed to receive EI and verify its authenticity. The receiving side of the device comprises a reception unit, a correlation decoder, a second digital watermark memory unit, a reception conversion unit, a second encoding unit, a second authentication key memory unit, a demodulator, an extraction key memory unit, a demodulating sequence generator, a de-interleaver, a de-interleaving key memory unit, and a block forming a solution, wherein the correlation decoder, a reception conversion unit, a second coding unit, a demodulator, a demodulating sequence former, deperam inhabitant and solutions forming unit provided with control inputs which receive respective control signals.

The specified analogue provides increased resistance to the effects of transmission channel errors on an electronic image certified by a digital watermark, but does not provide authentication of electronic images compressed using compression algorithms such as JPEG, MPEG-2, etc. This disadvantage of the known device for generating and verifying an electronic image verified by a digital watermark is due to the fact that embedding the digital watermark is carried out in the brightness values of the pixels of the electronic image, and when the Fourier transform and quantization of the Fourier coefficients are performed during the compression of the electronic image, the digital watermark is distorted, which leads to to non-recognition of the electronic image certified by a digital watermark as accepted by the recipient.

The closest in technical essence to the claimed device for generating and verifying an electronic image authenticated with a digital watermark is a device for generating and verifying an electronic image authenticated with a digital watermark according to US patent 7280669, IPC ⁸ G06K 9/00, dated 09.10.07. A prototype device for the formation and verification of an electronic image certified by a digital watermark consists of a transmitting side and a receiving side. The transmitting side of the device comprises an electronic image separation unit, a first Fourier transform unit, a first Fourier coefficient separation unit, a first authentication key memory unit, a unit authenticator driver, a digital watermark generator unit, an adder, a digital watermark embedding unit, a Fourier coefficient combination unit, a unit inverse Fourier transform, electronic image combining unit and transmission unit.

The receiving side of the device includes a receiving unit, a separation unit for a received electronic image, a second Fourier transform unit, a second Fourier coefficient separation unit, a second authentication key memory unit, a received unit authenticator driver, a digital watermark extraction unit, a correlator, and a decision generating unit.

The information input of the electronic image separation unit is the information input of the transmitting side of the device. The M-bit output of the electronic image separation unit is connected to the M-bit input of the first Fourier transform unit, where M≥2, the output of which is connected to the input of the Fourier coefficient separation unit. The output of the “first Fourier coefficients” of the Fourier coefficient separation unit is connected to the input of the “first Fourier coefficients” of the adder and the input of the “first Fourier coefficients” of the Fourier coefficient combination unit, and the output of the “second Fourier coefficients” of the Fourier coefficient separation unit is connected to the first information input of the embedding unit digital watermark. The output of the first memory block of the authentication key is connected to the information input “authentication key” of the unit authenticator, the output of which is connected to the information input “unit authenticator” of the digital watermark generator of the block, the output of which is connected to the input of the “CEH block” of the adder. The output of the adder is connected to the information input “summed CEH” of the digital watermark embedding unit, the output of which is connected to the input of the “integrated CEH” of the Fourier coefficient combining unit. The output of the Fourier coefficient combining unit is connected to the input of the inverse Fourier transform unit, the output of which is connected to the input of the electronic image combining unit. The output of the electronic image combining unit is connected to the input of the transmission unit, the output of which is the output of the transmitting side of the device, the electronic image separation unit, the unit authenticator and the digital watermark embedding unit are provided with read control inputs, the digital watermark unit of the block is equipped with a write control input, and the electronic image separation unit and the digital watermark embedding unit are also provided with recording control inputs, to which orye receives appropriate control signals.

The input of the receiving unit, connected through the transmission channel to the output of the transmitting side of the device, is the input of the receiving side of the device. The output of the receiving unit is connected to the information input of the separation unit of the received electronic image, the output of which is connected to the input of the second Fourier transform unit. The output of the second Fourier transform unit is connected to the input of the second Fourier coefficient separation unit, the output of the “first Fourier coefficients” and the output of the “second Fourier coefficients” of which are connected respectively to the same information inputs of the digital watermark extraction unit. The output of the digital watermark extraction unit is connected to the first input of the correlator. The output of the second memory block of the authentication key is connected to the information input “authentication key” of the authenticator of the received block, the output of which is connected to the second input of the correlator. The correlator output is connected to the information input of the decision-making unit, the “true electronic image” output and the “non-genuine electronic image” output of which are the corresponding outputs of the receiving side of the device, and the received electronic image splitting unit, the received authenticator authenticator and the decision forming unit are provided with read control inputs , and the digital watermark extraction unit is equipped with a control input of the recording, to which the corresponding th control signals.

The disadvantage of the closest analogue (prototype) of the claimed device for generating and checking an electronic image certified by a digital watermark is the relatively low security of the image verified by the sender's digital watermark from imposing a false electronic image on the intruder who knows at least one electronic image certified by the sender. This is because the intruder, for whom the value of the secret authentication key is unknown, is able to extract the digital watermark embedded in it from the sender of the electronic image verified by a digital watermark, then embed the extracted digital watermark into the false electronic image block, which, when verified by the recipient, will be mistakenly recognized as genuine. To extract the digital watermarked sender of the electronic image of its digital watermark embedded in the block, the intruder performs the Fourier transform on the pixel brightness values of this block and, like the receiver, calculates the digital watermark of the electronic image block from the Fourier coefficients belonging to the first and second frequency areas of this block. Therefore, the intruder is able, without knowing the secret authentication key, to extract the digital watermark from the electronic image verified by the sender and embed the extracted digital watermark into a false electronic image, which the recipient will erroneously recognize as authentic.

The technical result of the proposed solution is to increase the security of an electronic image certified by a digital watermark from the deliberate actions of the violator to change the content of the electronic image by using the dependence of the digital watermark on the electronic image, unknown to the violator.

The specified technical result is achieved by the fact that in the known device for generating and verifying an electronic image verified with a digital watermark, it contains a Fourier transform unit on the transmitting side, the M-bit input of which is connected to the M-bit output of the electronic image separation unit, where M≥2, information the input of which is the information input of the device, the generator of the authenticator of the block, the information input “authentication key” and the output of which are connected respectively to the output the first memory block of the authentication key and to the information input “block authenticator” of the digital watermark generator of the block, the output of which is connected to the input of the “CEH block” of the adder, the output of which is connected to the information input “summed CEH” of the digital watermark embedding unit, the output of which is connected to the input of the transmission unit, the output of which is the output of the transmitting side of the device, the electronic image separation unit, the authenticator of the unit and the digital embedding unit the watermark is provided with read control inputs, the digital watermark driver of the block is equipped with a write control input, and the electronic image separation unit and the digital watermark embedment unit are also equipped with write control inputs to which corresponding control signals are received, at the receiving side of the device, a receive unit, the input of which through the transmission channel is connected to the output of the transmitting side of the device, the shaper of the authenticator of the received block, information input “key authentic of identification ”of which is connected to the output of the second memory block of the authentication key, the digital watermark extraction unit and the decision-making unit, the outputs of which“ genuine electronic image ”and“ non-authentic electronic image ”are the corresponding outputs of the device, and the authenticator of the received block and the decision forming unit are provided control inputs of reading, and the digital watermark extraction unit is equipped with a control input of records, to which the corresponding control needles, a first quantizer, a Huffman encoder, a first matching sequence extractor, a first sequence pair memory block, a first matching sequence counter, a second quantizer, a block sequence generator and a first embedding key memory block, the output of which is connected to the “key” input, are additionally introduced on the transmitting side embedding ”adder. The M-bit output of the electronic image separation unit is connected to the M-bit information input of the second quantizer, the G-bit output of which is connected to the G-bit information input of the block sequence former, where 2≤G≤M, the output of which is connected to the information input “block sequence ”Of the block authenticator driver, the M-bit output of the Fourier transform block is connected to the M-bit information input of the first quantizer, the G-bit output of which is connected to the G-bit info the Huffman encoder’s input, whose Q-bit output is connected to the Huffman’s Q-bit information input of the first selector of matching sequences and to the same-name information input of the digital watermark embedding unit, where Q≥2. S-bit output “coincidence number” of the first highlighter of matching sequences is connected to the same S-bit information input of the digital watermark embedding unit, where S≥2, the “presence of coincidence” output of the first highlighter of matching sequences is connected to the same information input of the digital watermark embedding unit and to the input of the first counter of matching sequences, the R-bit output of which is connected to the R-bit information input, the "number of matches" is formed A digital water mark block where R≥log ₂ (N × N). From the first to the Sth, the Q-bit outputs of the first block of memory pairs of sequences are connected to the corresponding Q-bit information inputs of the “sequence of pairs” of the first highlighter of matching sequences and the embedding unit of a digital watermark, the first quantizer, Huffman encoder, the first highlighter of matching sequences, the first block memory of pairs of sequences, the second quantizer and the block sequence generator are equipped with read control inputs, and the sequence generator telnosti unit is further provided with a control input record, which are supplied with respective control signals.

On the receiving side, a Huffman sequence extractor of a received block, a Huffman decoder, a dequantizer, an inverse Fourier transform block, a third quantizer, a sequence generator of a received block, a second memory block of pairs of sequences, a second allocator of matching sequences, a second counter of matching sequences, an adder, a second memory block are additionally introduced the embedding key and the comparison unit, the information inputs are “authenticator of the received block” and “extracted CEH” which о are connected to the outputs of the shaper of the authenticator of the received block and the digital watermark extraction block, respectively. The R-bit information input “number of matches” of the digital watermark extraction unit is connected to the R-bit output of the second counter of matching sequences, the input of which is connected to the “presence of coincidence” output of the second selector of matching sequences, the Q-bit information input of “Huffman sequence” and with the first on the S-th Q-bit information inputs of the “sequence of pairs” of which are connected respectively to the Q-bit output of the Huffman sequence isolator of the received block ka and to the corresponding Q-bit outputs of the second block of memory pairs of sequences. The “identification” output of the second selector of matching sequences is connected to the adder of the same name, the “embed key” input of which is connected to the output of the second embed key memory block. The output of the reception block is connected to the information input of the Huffman sequence extractor of the received block, the Q-bit output of which is connected to the Q-bit information input of the Huffman decoder, the G-bit output of which is connected to the G-bit information input of the dequantizer, the M-bit output of which is connected to M -digit input of the inverse Fourier transform block, the M-bit output of which is connected to the M-bit information input of the third quantizer, the G-bit output of which is connected to the G-bit inf rmatsionnomu input of the sequence of a received block whose output is connected to the data input of the "block sequence of the received" authenticator shaper received block. The output of the adder is connected to the information input “summed signal” of the digital watermark extraction unit, the output of the comparison unit is connected to the information input of the decision forming unit. Moreover, the Huffman sequence extractor of the received block, the Huffman decoder, the dequantizer, the third quantizer, the sequence generator of the received block, the second memory block of the pairs of sequences, the second highlighter of matching sequences and the comparison unit are equipped with read control inputs, and the Huffman sequence extractor of the received block and the sequence generator of the received block are provided Additionally, the control inputs of the recording, which receive the corresponding signals equalization.

The specified new set of essential features due to the unpredictable dependence of the digital watermark of a block of an electronic image authenticated by a digital watermark on the brightness values of the pixels of this block and the secret authentication key makes it impossible for an intruder who does not know any electronic image authenticated by a digital watermark to form a digital watermark mark for embedding in a false electronic image, which will be recognized by the recipient when it is processed verka authentic. When an intruder intercepts one or several electronic watermarked electronic images due to the unpredictability of the digital watermark of the certified electronic image block on the value of the secret embed key, the intruder is not able to extract the built-in digital watermark in order to embed it in a false electronic image, which ensures an increase security of an electronic image certified by a digital watermark from the deliberate actions of the violator an understanding of its content.

The claimed device is illustrated by drawings, which show:

- figure 1 is a General diagram of a device for the formation and verification of a digital watermarked electronic image;

- figure 2 is a structural diagram of the transmitting side 1 of the device for the formation and verification of a digital watermark certified electronic image;

- figure 3 is a structural diagram of the receiving side 2 of the device for the formation and verification of a digital watermark certified electronic image;

- figure 4 is an example of constructing a first quantization function in a table form;

- figure 5 is an example of the numbering of the Fourier coefficients of the electronic image block;

- figure 6 is a structural diagram of the first quantizer 1.3;

- Fig.7 is a structural diagram of a Huffman encoder 1.4;

- Fig. 8 is a structural diagram of a first isolator of matching sequences 1.5;

- figure 9 is a structural diagram of a second quantizer 1.8;

- figure 10 is a structural diagram of the shaper authenticator block 1.10;

- figure 11 is a structural diagram of the shaper digital watermark block 1.12;

- Fig. 12 is a block diagram of a digital watermark embedding unit 1.15;

- Fig.13 is a structural diagram of a Huffman sequence extractor of a received block 2.2;

- Fig.14 is a structural diagram of a dequantizer 2.4;

- Fig.15 is a structural diagram of a second highlighter of matching sequences 2.11;

- in Fig.16 is a block diagram of a digital watermark extraction unit 2.14;

- on Fig - timing diagrams of the formation and verification of a digital watermark certified electronic image;

- Fig. 18 is a graph showing the effect of the inventive device.

The inventive device shown in figure 1, consists of a transmitting side 1 of the device and a receiving side 2 of the device, which interact through a transmission channel. The transmitting side 1 of the device is designed to calculate from a certified electronic image a digital watermark using a secret authentication key and embed it in the same image using a secret embed key, as well as transmitting the electronic image thus certified by a digital watermark over the transmission channel. On the transmitting side 1 of the device receives a certified electronic image, an authentication secret key and an embed secret key. The output of the transmitting side 1 of the device through the transmission channel is connected to the input of the receiving side 2 of the device. In the transmission channel, the intruder can intercept the electronic image certified by a digital watermark transmitted by the sender. The intruder tries to extract the digital watermark from the certified electronic image and embed the extracted digital watermark into a false electronic image, after which the intruder transmits the false electronic image to the recipient through the transmission channel. The receiving side 2 of the device is intended for receiving an electronic image from a transmission channel, extracting a digital watermark from the received electronic image using the embed secret key and verifying its authenticity using the secret authentication key. The authentication secret key and the embed secret key are received on the receiving side 2 of the device. The authentication result of the received electronic image is read from the outputs of the receiving side 2 of the device “genuine electronic image” and “non-genuine electronic image”.

The transmitting side 1 of the device (Fig. 2) consists of an electronic image separation unit 1.1, a Fourier transform unit 1.2, a first quantizer 1.3, a Huffman encoder 1.4, a first matching sequences extractor 1.5, a first memory block of pairs of sequences 1.6, a first counter of matching sequences 1.7, and a second a quantizer 1.8, a shaper of a block 1.9, a shaper of an authenticator of a block 1.10, a first memory block of an authentication key 1.11, a shaper of a digital watermark of a block 1.12, an adder 1. 13, a first embeddance key memory unit 1.14, a digital watermark embedder 1.15, and a transfer unit 1.16.

The M-bit input of the Fourier transform unit 1.2 is connected to the M-bit output of the electronic image separation unit 1.1, where M≥2, the information input of which is the information input of the device. The information input “authentication key” and the output of the generator of the authenticator of block 1.10 are connected respectively to the output of the first memory block of the authentication key 1.11 and to the information input “authenticator of the block” of the driver of the digital watermark of block 1.12, the output of which is connected to the input of the “CEH block” of adder 1.13, the output which is connected to the information input “summarized digital watermark" block embedding digital watermark 1.15, the output of which is connected to the input of the transmission block 1.16, the output of which is the output before guide apparatus side. The output of the first memory block of the embed key 1.14 is connected to the input "embed key" of the adder 1.13. The M-bit output of the electronic image separation unit 1.1 is connected to the M-bit information input of the second quantizer 1.8, the G-bit output of which is connected to the G-bit information input of the sequence generator of block 1.9, where 2≤G≤M, the output of which is connected to the information input “Block sequence” of the shaper of the authenticator of the block 1.10. The M-bit output of the Fourier transform block 1.2 is connected to the M-bit information input of the first quantizer 1.3, the G-bit output of which is connected to the G-bit information input of the Huffman encoder 1.4, the Q-bit output of which is connected to the Q-bit information input “Huffman sequence ”Of the first extractor of matching sequences 1.5 and to the same information input of the digital watermark embedding unit 1.15, where Q≥2. S-bit output “coincidence number" of the first selector of matching sequences 1.5 is connected to the same S-bit information input of the digital watermark embedding unit 1.15, where S≥2. The “presence of coincidence” output of the first extractor of matching sequences 1.5 is connected to the same information input of the digital watermark embedding unit 1.15 and to the input of the first counter of matching sequences 1.7, whose R-bit output is connected to the R-bit information input “number of matches” of the digital watermark generator block 1.12, where R≥log ₂ (N × N). From the first to the Sth, the Q-bit outputs of the first memory block of pairs of sequences 1.6 are connected to the corresponding Q-bit information inputs of the “sequence of pairs” of the first extractor of matching sequences 1.5 and the digital watermark embedding block 1.15. Moreover, the electronic image separation unit 1.1, the first quantizer 1.3, the Huffman encoder 1.4, the first allocator of matching sequences 1.5, the first memory block of pairs of sequences 1.6, the second quantizer 1.8, the sequence generator of block 1.9, the authenticator of block 1.10 and the digital watermark embedding unit 1.15 are equipped with control read inputs, the digital watermark driver of block 1.12 is equipped with a recording control input, and the electronic image separation unit 1.1, the driver after The sequences of block 1.9 and the embedding unit of the digital watermark 1.15 are also equipped with recording control inputs, to which corresponding control signals from the control unit (not shown) are supplied.

The receiving side 2 of the device (Fig. 3) consists of a receiving block 2.1, a Huffman sequence extractor of a received block 2.2, a Huffman decoder 2.3, a dequantizer 2.4, an inverse Fourier transform block 2.5, a third quantizer 2.6, a sequence shaper of a received block 2.7, an authenticator of a received block 2.8 , the second memory block of the authentication key 2.9, the second memory block of pairs of sequences 2.10, the second allocator of matching sequences 2.11, the second counter of matching sequences 2.12, sum Ator 2.13, the block extracting digital watermark 2.14, the second memory block embedding key 2.15, 2.16 comparator unit and 2.17 unit forming solutions.

On the receiving side of the device, the input of the receiving unit 2.1 through the transmission channel is connected to the output of the transmitting side of the device. The information input “authentication key” of the authenticator of the received block 2.8 is connected to the output of the second memory block of the authentication key 2.9. The outputs “genuine electronic image” and “non-genuine electronic image” of the decision-making unit 2.17 are the corresponding outputs of the device. The information inputs “authenticator of the received block” and “extracted CEH” of the comparison block 2.16 are connected to the outputs of the shaper of the authenticator of the received block 2.8 and the digital watermark extraction unit 2.14, the R-bit information input “number of matches” of which is connected to the R-bit output of the second counter matching sequences 2.12, the input of which is connected to the “presence of coincidence” output of the second highlighter of matching sequences 2.11, the Q-bit information input “sequence Huffman ”and the first through Sth Q-bit information inputs of the“ sequence of pairs ”of which are connected respectively to the Q-bit output of the Huffman sequence extractor of the received block 2.2 and to the corresponding Q-bit outputs of the second block of memory of the pairs of sequences 2.10. The “identification” output of the second selector of matching sequences 2.11 is connected to the input of the adder 2.13 of the same name, the “embed key” input of which is connected to the output of the second memory block of the embed key 2.15. The output of the receiving unit 2.1 is connected to the information input of the Huffman sequence extractor of the received block 2.2, the Q-bit output of which is connected to the Q-bit information input of the Huffman decoder 2.3, the G-bit output of which is connected to the G-bit information input of the dequantizer 2.4, M-bit output which is connected to the M-bit input of the inverse Fourier transform block 2.5, the M-bit output of which is connected to the M-bit information input of the third quantizer 2.6, the G-bit output of which is connected to G-ra the row information input of the sequence shaper of the received block 2.7, the output of which is connected to the information input “sequence of the received block” of the shaper of the authenticator of the received block 2.8. The output of adder 2.13 is connected to the information input “summed signal” of the digital watermark extraction unit 2.14, the output of the comparison unit 2.16 is connected to the information input of the decision formation block 2.17. Moreover, the Huffman sequence extractor of the received block 2.2, the Huffman decoder 2.3, the dequantizer 2.4, the third quantizer 2.6, the sequence shaper of the received block 2.7, the authenticator of the received block 2.8, the second memory block of pairs of sequences 2.10, the second allocator of matching sequences 2.11, the comparison block 2.16 and the generation block 2.17 solutions are equipped with read control inputs, a digital watermark extraction unit 2.14 is equipped with a write control input, and sequence extractor affmana received block sequence generator 2.2 and 2.7 of the received block is further provided with control inputs of recording, which are supplied with respective control signals from the control unit (not shown in the diagram).

The electronic image separation unit 1.1 is intended for dividing the certified electronic image into disjoint blocks each of N × N pixels in size, where the N × N block size is, for example, 8 × 8, 16 × 16 or more pixels. It can be implemented as a dynamic random access memory unit with an address code multiplexer, in which the brightness values of the pixels of the electronic image are recorded sequentially in rows and columns at a time determined by the control signal of the record received at the control input of the record. By the read control signal received at its read control input, the block of the electronic image is read out, alternately from the first to the last block, each of which consists of a matrix of pixel brightness values consisting of N rows and N columns. The pixel values of the electronic image block are read over the M-bit parallel transmission bus. The block diagram of the separation of the electronic image 1.1 is known and is given, for example, in the book: O.N. Lebedev, A.K. Martsinkevichus, E.K. Bagdanskis, R.L. Poshyunas, B.V. Dragan and other Memory chips. DAC and ADC. - M.: KubK-a, 1996, pp. 91-94, Fig. 3.9.

The Fourier transform block 1.2 is designed to perform the Fourier transform of the electronic image block. Above the N × N brightness values of the pixels of the electronic image block in the Fourier transform block 1.2, the Fourier transform is performed, as a result of which N × N values of the Fourier coefficients of this block are formed. The scheme of the Fourier transform block 1.2 is known and is given, for example, in RF patent 2125290, Arithmetic device for performing fast Hartley-Fourier transform. It can be implemented, for example, on the Xilinx XCV100-4 programmable logic circuits of the Virtex series, containing 100 thousand valves (see Xilinx Electronic Product Catalog, 2003, pp. 129-133).

The first quantizer 1.3 is designed to quantize the values of the Fourier coefficients of the electronic image block. In the first quantizer 1.3, N × N values inverse to the corresponding values of the quantization coefficients of the Fourier coefficients of the electronic image block are pre-recorded. The value of each value inverse to the corresponding value of the quantization coefficient is determined as a positive number in the range of values from zero to unity by which the value of the corresponding Fourier coefficient of the block of the electronic image is multiplied when it is quantized. The quantization coefficients of an 8 × 8 pixel block of an electronic image in accordance with the MPEG-2 electronic image compression algorithm are described, for example, in the book by D.Vatolin, A. Ratushnyak, M. Smirnov, V.Yukin, Data compression methods. The device archivers, image and video compression. - M .: DIALOGUE-MEPhI, 2002, p. 308, and are presented in figure 4. The Fourier coefficients of the electronic image block are numbered from the first to the (N × N) -th. The order of numbering of the Fourier coefficients of an electronic image block is described, for example, in the book by D. Watolin, A. Ratushnyak, M. Smirnov, V. Yukin, Data compression methods. The device archivers, image and video compression. - M .: DIALOGUE-MEPhI, 2002, p. 309, and for a block of size 8 × 8 is shown in figure 5.

The first quantizer 1.3, shown in FIG. 6, consists of a memory block 1.3.1, a multiplier (MPL) 1.3.2, a counter 1.3.3, and a switch (MX) 1.3.4. The M-bit information input of the first quantizer 1.3, implemented in the form of a bus with parallel transmission, is the information input “Fourier coefficients” (X ₁ ) of the multiplier 1.3.2. The group of N × N outputs of the memory block 1.3.1, implemented in the form of M-bit buses with parallel transmission, is connected to the group N × N of the corresponding information inputs (X ₁ , X ₂ , ..., X _{N × N} ) of the switch 1.3.4. The output (Y) of the switch 1.3.4, implemented in the form of an M-bit bus with parallel transmission, is connected to the M-bit information input “inverse values of the quantization coefficients” (X ₂ ) of the multiplier 1.3.2. The output of the counter 1.3.3, implemented as a K-bit bus with parallel transmission, is connected to the control input (Address) of the switch 1.3.4. The control inputs of the reading of the memory block 1.3.1 and the multiplier 1.3.2, as well as the information input of the counter 1.3.3 are combined and are the control input of the reading of the first quantizer 1.3. The output of the multiplier 1.3.2, implemented in the form of a G-bit bus with parallel transmission, where 2≤G≤M, is the G-bit output of the first quantizer 1.3.

The memory block 1.3.1 is designed to store N × N values that are inverse to the corresponding values of the quantization coefficients of the Fourier coefficients of the electronic image block. The memory block 1.3.1 consists of N × N identical memory elements (ES) 1.3.1.1, 1.3.1.2, ..., 1.3.1. N × N. In these EPs, in accordance with their number, preliminary values are written that are inverse to the corresponding values of the quantization coefficients of the Fourier coefficients of the electronic image block. The control inputs for reading the electronic devices 1.3.1.1, 1.3.1.2, ..., 1.3.1. N × N are the control input of the reading of the memory block 1.3.1. ES scheme 1.3.1.1, 1.3.1.2, ..., 1.3.1. N × N is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 138, Fig. 5.28. They can be implemented, for example, on the KM1608RT1 ROM chip (see Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova, etc. Edited by S.V. Yakubovsky . - M.: Radio and Communications, 1989, p. 317).

The multiplier 1.3.2 is designed to multiply the values of the Fourier coefficients of the block of the electronic image by the corresponding values that are inverse to the value of the quantization coefficients of the Fourier coefficients of the block of the electronic image. The multiplier 1.3.2 has an information input “Fourier coefficients” (recording input X _{1 of the} first factor) and an information input “inverse values of quantization coefficients” (recording input X _{2 of the} second factor). The multiplication of the values supplied by these information inputs, and the reading of the result of the multiplication at the output of the multiplier are carried out by the control signal read to the input of the read control of the multiplier 1.3.2. The scheme of the multiplier 1.3.2 is known and is given, for example, in the book: G.I. Pukhalsky, T.Ya. Novoseltsev, Design of discrete devices on integrated circuits. - M.: Radio and Communications, 1990, pp. 152-157, Fig. 3.70. The multiplier 1.3.2 can be implemented on the 1802BP4 chip.

The counter 1.3.3 is designed to generate control signals that connect through the switch 1.3.4 the output of the selected from memory elements 1.3.1.1, 1.3.1.2, ..., 1.3.1. N × N memory element to the information input “inverse values of the quantization coefficients" of the multiplier 1.3.2. The counter scheme 1.3.3 is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 127, Fig. 5.18. The counter 1.3.3 can be implemented, for example, on the K155IE2 chip (see A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M .: Radio and communications, 1983, p. 126) .

Switch 1.3.4 is designed to connect in accordance with the control signals generated by the counter 1.3.3 output signals selected from memory elements 1.3.1.1, 1.3.1.2, ..., 1.3.1. N × N memory element to the information input “inverse values of the quantization coefficients" of the multiplier 1.3.2. Through the switch 1.3.4 to the information input “inverse values of the quantization coefficients” of the multiplier 1.3.2, in turn, from the first to the (N × N) th, the values are inverse to the corresponding values of the quantization coefficients of the Fourier coefficients of the electronic image block. The switch circuit 1.3.4 is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for the formation and processing of complex signals. - M.: Radio and Communications, 1983, p. 112, Fig. 5.11. It can be implemented, for example, on a 555KP7 multiplexer microcircuit (see G.I. Pukhalsky, T.Ya. Novoseltsev, Designing discrete devices on integrated circuits. - M.: Radio and communications, 1990, pp. 103-106, fig. .3.10).

The Huffman encoder 1.4 shown in FIG. 7 is intended to encode N × N values of the quantized Fourier coefficients of an electronic image block by replacing them with N × N predefined binary Huffman code sequences. The Huffman encoder 1.4 consists of a memory matrix (RT) 1.4.1. The information input (Address) of the memory matrix 1.4.1, implemented as a G-bit bus with parallel transmission, is the G-bit information input of the Huffman encoder 1.4, and the output of the memory matrix 1.4.1, implemented as a Q-bit bus with parallel transmission is the Q-bit output of the Huffman encoder 1.4. The read control input (Exercise) of the memory matrix 1.4.1 is the read control input of the Huffman encoder 1.4.

The binary sequences of the Huffman code are pre-recorded in the cells of the memory matrix 1.4.1. The addresses of the cells of the memory matrix 1.4.1 are the values of the quantized Fourier coefficients of the block of the electronic image corresponding to the pre-recorded binary sequences of the Huffman code. From the output of the first quantizer 1.3, the value of the quantized Fourier coefficient of the electronic image block is received to the information input (Address) of the memory matrix 1.4.1, and the corresponding binary sequence of the Huffman code is read from the output of the memory matrix. The read moment is determined by the read control signal received at the read control input (Exercise) of the memory matrix 1.4.1. The layout of the memory matrix 1.4.1 is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 138, Fig. 5.28. The memory matrix 1.4.1 can be implemented, for example, on the KM1608RT1 ROM chip (see Digital and analog integrated circuits: a reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova, etc. Ed. C .V. Yakubovsky. - M.: Radio and Communications, 1989, p. 317).

The first matching sequence extractor (PVSP) 1.5, shown in Figure 8, is designed to extract matching sequences from binary sequences of the Huffman code of the electronic image block read from the output of the Huffman encoder 1.4 and binary sequences included in one of the preformed pairs of binary sequences recorded in the first block of memory pairs of sequences 1.6.

PVSP 1.5 consists of Q-bit comparators 1.5.1, 1.5.2, ..., 1.5.S and the unit block 1.5.S + 1. The number S is equal to twice the number of preformed pairs of binary sequences recorded in the first memory block of pairs of sequences 1.6. The first inputs of the bits of the comparators 1.5.1, 1.5.2, ..., 1.5.S are implemented as a Q-bit bus with parallel transmission. The first inputs of the same name of the bits of the comparators 1.5.1, 1.5.2, ..., 1.5.S are combined and are the Q-bit information input of the “Huffman sequence” of the PVSP 1.5. The second inputs of Q bits of the comparator 1.5.1 are the first Q-bit information input of the “sequence of pairs” of the PVSP 1.5, the second inputs of the Q bits of the comparator 1.5.2 are the second Q-bit information input of the “sequence of pairs” of the PVSP 1.5, etc. The outputs of the comparators 1.5.1, 1.5.2, ..., 1.5.S are the S-bit output of the “coincidence number” of the PVSP 1.5. The outputs of the comparators 1.5.1, 1.5.2, ..., 1.5.S are also connected to the inputs of the unit of the same name 1.5.S + 1, the output of which is the “presence of coincidence” output of the PVSP 1.5. The control inputs for reading comparators 1.5.1, 1.5.2, ..., 1.5.S are combined and are the control input for reading PVSP 1.5.

The same comparators 1.5.1, 1.5.2, ..., 1.5.S are intended to identify matching binary sequences of the Huffman code of the electronic image block and S binary sequences included in one of the preformed pairs of binary sequences. When such a match is detected, the output of the corresponding comparator at a time determined by the read control signal at its read control input, a single binary signal appears. The circuit of comparators 1.5.1, 1.5.2, ..., 1.5.S is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 108, Fig. 5.6. They can be implemented, for example, on the K564IP2 chip (see A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 109).

The combination circuit 1.5.S + 1 is designed to combine the signals from the outputs of the comparators 1.5.1, 1.5.2, ..., 1.5.S. When any of the comparators is triggered, a single binary signal appears at the output of the 1.5.S + 1 combining circuit. The union scheme 1.5.S + 1 is known as the “OR” logical element and is given, for example, in the book: G.I. Pukhalsky, T.Ya. Novoseltsev, Design of discrete devices on integrated circuits. - M.: Radio and Communications, 1990, pp. 33-36, Fig. 2.1. It can be implemented, for example, on the 155LE7 chip (see G.I. Pukhalsky, T.Ya. Novoseltsev, Designing discrete devices on integrated circuits. - M.: Radio and Communications, 1990, p. 39, Fig. 2.3) .

The first block memory pair of sequences (PBPPP) 1.6 is designed to store binary sequences of pre-formed pairs. PBPPP 1.6 has S Q-bit outputs, numbered from first to Sth. The reading of binary sequences of pre-formed pairs from the output of PBPPP 1.6 is determined by the read control signal received at its read control input. The PBPPP 1.6 scheme is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 138, Fig. 5.28. It can be implemented on the KM1608RT1 ROM chip (see Digital and analog integrated circuits: a reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova, etc. Edited by S.V. Yakubovsky. - M. : Radio and Communications, 1989, p. 317).

The first matching sequence counter (PRSP) 1.7 is designed to count the number N _{1 of} matching sequences from binary sequences of the Huffman code of the electronic image block and binary sequences included in one of the preformed pairs of binary sequences. The calculated number N _{1 is} read from the output of the MSSP 1.7, implemented as an R-bit bus with parallel transmission, where R≥log ₂ (N × N). The PSSP 1.7 scheme is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 127, Fig. 5.18. It can be implemented, for example, on the K155IE2 microcircuit (see A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 126).

The second quantizer 1.8, shown in figure 9, is designed to quantize the brightness values of the pixels of the block of the electronic image. In the second quantizer 1.8, N × N values of the quantization coefficients of brightness of pixels of the electronic image block are pre-recorded. The procedure for establishing the values of the quantization coefficients of brightness of pixels of an electronic image block is described, for example, in the book A.Dilgin, P. Sementilli, M. Marcellin, Progressive image coding using trellis coded quantization / IEEE Trans. on Image Processing. No. 11, 1997, p.1240-1253.

The second quantizer 1.8 consists of a memory block 1.8.1, a multiplier (MPL) 1.8.2, a counter 1.8.3, and a switch (MX) 1.8.4. The M-bit information input of the second quantizer 1.8 is the M-bit information input of the “pixel brightness value” (input X ₁ ) of the multiplier 1.8.2. The group of N × N outputs of the memory block 1.8.1, implemented in the form of M-bit buses with parallel transmission, is connected to the group N × N of the corresponding information inputs (X ₁ , X ₂ , ..., X _{N × N} ) of the switch 1.8.4. The M-bit output (Y) of the 1.8.4 switch is connected to the M-bit information input of the “quantization coefficient value” (X ₂ ) of the 1.8.2 multiplier. The output of the counter 1.8.3, implemented as a K-bit bus with parallel transmission, is connected to the control input (Address) of the 1.8.4 switch. The control inputs of the reading of the memory block 1.8.1 and the multiplier 1.8.2, as well as the information input of the counter 1.8.3 are combined and are the control input of the reading of the second quantizer 1.8. The output of the multiplier 1.8.2, implemented in the form of a G-bit bus with parallel transmission, where G≤M, is the G-bit output of the second quantizer 1.8.

The memory block 1.8.1 is designed to store N × N values of the quantization coefficients of brightness of the pixels of the electronic image block. The circuit of the memory block 1.8.1 is similar to the circuit of the memory block 1.3.1 described earlier.

The multiplier 1.8.2 is designed to multiply the brightness values of the pixels of the block of the electronic image on the corresponding values of the quantization coefficients of the brightness of the pixels. The scheme of the multiplier 1.8.2 is similar to the scheme of the multiplier 1.3.2 described earlier.

Counter 1.8.3 is intended for generating control signals that connect through the switch 1.8.4 the output of the selected from memory elements 1.8.1.1, 1.8.1.2, ..., 1.8.1. N × N memory element to the information input “value of the quantization coefficients” of the multiplier 1.8.2. The counter scheme 1.8.3 is similar to the counter scheme 1.3.3 described earlier.

The switch 1.8.4 is intended for connection in accordance with the control signals generated by the counter 1.8.3 output signals selected from memory elements 1.8.1.1, 1.8.1.2, ..., 1.8.1. N × N memory element to the information input “value of the quantization coefficients” of the multiplier 1.8.2. Switch 1.8.4 is similar to switch 1.3.4 described earlier.

The block sequence generator (FPB) 1.9 is intended for generating a binary sequence of an electronic image block by concatenating binary sequences of quantized pixel brightness values of this block. In FPB 1.9, binary sequences of quantized pixel brightness values of an electronic image block are sequentially recorded from the first to the (N × N) th so that the beginning of the next binary sequence is written close to the end of the previous binary sequence. The sequential recording of binary sequences of quantized pixel brightness values of an electronic image block is controlled by recording control signals received at the recording control input of the FPB 1.9. The sequential reading of the binary sequence of the electronic image block is controlled by the read control signals received at the read control input of the FPB 1.9.

FPB 1.9 is physically a shift register with sequential write and sequential read of a binary sequence. The FPB 1.9 scheme is known and described, for example, in the book of A.V. Asoskov, M.A. Ivanov, A.A. Mirsky and other Stream ciphers. - M.: KUDITS-IMAGE, 2003, pp. 174-180, Fig. 5.5. It can be implemented, for example, on the K155IR8 chip (see Digital and analog integrated circuits: a reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova, etc. Edited by S. Yakubovsky. - M : Radio and Communications, 1989, p. 50).

Shaper authenticator block (FAB) 1.10, presented in figure 10, is intended to form a block authenticator of the electronic image. FAB 1.10 consists of switches 1.10.1 and 1.10.4, registers 1.10.2 and 1.10.5, adders 1.10.3, 1.10.6 and 1.10.7, an electronic key 1.10.8, a waiting multivibrator 1.10.9 and a pulse generator 1.10 .10. The information input “block sequence” FAB 1.10 is the information input “block sequence” of the switch 1.10.1, the information input “feedback signal” of which is connected to the output of the adder 1.10.3. The information input “authentication key” FAB 1.10 is the information input “authentication key” switch 1.10.4, the information input “feedback signal” which is connected to the output of the adder 1.10.6. The output of the waiting multivibrator 1.10.9 is connected to the input of the pulse generator 1.10.10, the output of which is connected to the control inputs “clock pulses” of the registers 1.10.2 and 1.10.5, the information inputs of which are connected respectively to the outputs of the switches 1.10.1 and 1.10.4. The first inputs of adders 1.10.7 and 1.10.3 are combined and connected to the output of the “recurrence sequence” of register 1.10.2. The second input of the adder 1.10.7 and the first input of the adder 1.10.6 are combined and connected to the output of the "recurrence sequence" of register 1.10.5. The second input of adder 1.10.3 is connected to the “shifted sequence” output of register 1.10.2, the second input of adder 1.10.6 is connected to the “shifted sequence” output of register 1.10.5. The output of adder 1.10.7 is connected to the information input of the electronic key 1.10.8, the output of which is the output of the FAB 1.10. The control input for reading the FAB 1.10 is the control input for reading the switches 1.10.1, 1.10.4, respectively, the waiting multivibrator 1.10.9 and the electronic key 1.10.8.

The switch 1.10.1 is intended for the initial connection of the information input “block sequence” of FAB 1.10 to the information input of register 1.10.2 to record the sequence of the electronic image block in it and the subsequent connection of the information input of register 1.10.2 to the output of adder 1.10.3. The circuit of such a switch is known and is given, for example, in the book of V.L.Shilo, Popular CMOS chips. Directory. - M .: Jaguar, 1993, p. 22. The switch 1.10.4 is intended for the initial connection of the information input “authentication key” FAB 1.10 to the information input of the register 1.10.5 for recording in it the sequence of the secret authentication key and the subsequent connection of the information input of the register 1.10.5 to the output of the adder 1.10.6. The circuit of the switch 1.10.4 is similar, for example, to the circuit of the switch 1.10.1 described earlier.

Registers 1.10.2 and 1.10.5 are similar and are designed for shifting under the control of clock pulses arriving at their control inputs “clock pulses”, the sequences of the electronic image block and the sequence of the secret authentication key, respectively, recorded in them. Register schemes are known and described, for example, in the book of A.V. Asoskov, M.A. Ivanov, A.A. Mirsky and other Stream ciphers. - M.: KUDITS-IMAGE, 2003, pp. 174-180, Fig. 5.5. They can be implemented, for example, on the K155IR2 chip (see Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova, etc. Edited by S.V. Yakubovsky. - M.: Radio and Communications, 1989, p. 50).

The same adders 1.10.3 and 1.10.6 are intended for modulo 2 summation of binary sequences coming from the “recurrence sequence” and “shifted sequence” outputs of registers 1.10.2 and 1.10.5, respectively. The adder circuit is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 108, Fig.5.5. They can be implemented, for example, on the KM155IM3 microcircuit (see Digital and analog integrated circuits: a reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova, etc. Edited by S.V. Yakubovsky. - M.: Radio and Communications, 1989, p. 50).

The adder 1.10.7 is intended for modulo 2 summation of binary sequences coming from the outputs of the “recurrence sequence” of registers 1.10.2 and 1.10.5. The output signal of the adder 1.10.7 is the authenticator of the electronic image block. The adder circuit 1.10.7 is similar, for example, to the adder circuit 1.10.3 described earlier.

The electronic key 1.10.8 is intended for reading the authenticator of the electronic image block from the output of the adder 1.10.7 to the output of the FAB 1.10 when the electronic control key receives the control read signal. By physical nature, the electronic key 1.10.8 is an elementary controlled switch. The electronic key circuit 1.10.8 is known and is given, for example, in the book of V.L.Shilo, Popular CMOS circuits, reference book. - M .: Jaguar, 1993, p. 22.

The standby multivibrator 1.10.9 is designed to generate a trigger signal that starts the pulse generator 1.10.10 when the corresponding control signal appears on the read control input of the waiting multivibrator 1.10.9. The circuit of the waiting multivibrator 1.10.9 is known and is given, for example, in the book A.S. Partin, V.G. Borisov, Introduction to Digital Technology. - M.: Radio and Communications, 1987, p. 13, Fig. 13. It can be implemented, for example, on the K155LA3 chip (see A.S.Partin, V.G. Borisov, Introduction to Digital Technology. - M.: Radio and Communications, 1987, p. 15).

The pulse generator 1.10.10 is designed to generate a sequence of clock pulses designed to shift the sequence of the electronic image block and the sequence of the secret authentication key in registers 1.10.2 and 1.10.5, respectively. The pulse generator circuit of 1.10.10 is known and is given, for example, in the book by A.S.Partin, V.G. Borisov, Introduction to Digital Technology. - M .: Radio and communications, 1987, p. 13, fig. 12. It can be implemented, for example, on the K155LA3 chip (see A.S.Partin, V.G. Borisov, Introduction to Digital Technology. - M.: Radio and Communications, 1987, p. 13).

The first memory block of the authentication key 1.11 is designed to store the value of the secret authentication key. The scheme of the first memory block of the authentication key 1.11 is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 138, Fig. 5.28. It can be implemented on a ROM chip KM1608RT1 (see Digital and analog integrated circuits: a reference / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova and others. Edited by S.V. Yakubovsky. - M .: Radio and communications, 1989, p. 317).

Shaper digital watermark block (FTsVZB) 1.12, shown in figure 11, is intended to generate a digital watermark block electronic image. To do this, through the information input “block authenticator” of the FCVZB 1.12, the authenticator of the block of the electronic image is read from the output of the generator of the authenticator of the block 1.10 and the number of matching sequences from the output of the PRSS 1.7 equal to N _{1 is} read through the R-bit information input “number of matches”. The first N ₁ bits of its authenticator are recorded in the binary sequence of the digital watermark of the electronic image block, and the remaining bits of the authenticator of the electronic image block are discarded. FTsVZB 1.12 consists of a shift register (RG) 1.12.1, electronic keys (EC) 1.12.2 and 1.12.5, counters (ST) 1.12.3 and 1.12.6 and a pulse generator 1.12.4.

The information input “block authenticator” of FTsVZB 1.12 is the information input of shift register 1.12.1, the output of which is the output of FTsVZB 1.12. The R-bit information input "number of matches" of the Federal Security and Commercial Bank 1.12 is the control input of the account coefficient setting (Set) of the counter 1.12.6. The control input of the record FTsVZB 1.12 is the control input of the record of the counter 1.12.6, as well as the information inputs of the electronic key 1.12.2 and the counter 1.12.3. The output of the electronic key 1.12.2 is connected to the control input of the shift register 1.12.1. The output of counter 1.12.3 is connected to the control input of the electronic key 1.12.2 and the control input of the pulse generator 1.12.4, the output of which is connected to the information input of the counter 1.12.6 and the information input of the electronic key 1.12.5. The output of the counter 1.12.6 is connected to the control input of the electronic key 1.12.5, the output of which is connected to the control input of reading the shift register 1.12.1.

The shift register 1.12.1 is intended for recording the authenticator of the electronic image block arriving at its information input, and then reading its first N ₁ bits to the output. Recording is carried out upon receipt of a write control signal for recording at its control input, reading is performed upon receipt of a read control signal at its read control input. The scheme of the shift register 1.12.1 is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 121, Fig. 5.16b. It can be implemented, for example, on the K144IR2 microcircuit (see A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 122).

The electronic key 1.12.2 is designed to connect a control signal supplied to the control input of the FCVZB 1.12 record to the control input of the shift register 1.12.1. During the transfer of control pulses of the FCVZB 1.12 N × N pulses to the control input of the electronic key 1.12.2 from the output of the counter 1.12.3, a control signal is received that allows writing to the shift register 1.12.1. The electronic key circuit 1.12.2 is known and is given, for example, in the book of V.L.Shilo, Popular digital microcircuits. Directory. - M .: Radio and communications, 1987, p. 226, fig. 2.27.

The counter 1.12.3 is intended for counting N × N pulses arriving at its information input. After counting N × N clock pulses, the signal at the output of counter 1.12.3 changes from allowing to prohibit the passage of pulses through the electronic switch 1.12.2, at the same time this output signal is fed to the input of the pulse generator 1.12.4, allowing pulse generation. The counter circuit 1.12.3 is known and is given, for example, in the book of V.L.Shilo, Popular digital microcircuits. Directory. - M.: Radio and Communications, 1987, p. 90, Fig. 1.67.

The pulse generator 1.12.4 is designed to generate at its output a sequence of clock pulses, which are counted by the counter 1.12.6 and simultaneously fed to the information input of the electronic key 1.12.5. Pulse generation starts from the moment the signal arrives from the output of the counter 1.12.3 to the input of the pulse generator 1.12.4. The pulse generator circuit is known and is given, for example, in the book by A.S.Partin, V.G. Borisov, Introduction to Digital Technology. - M .: Radio and communications, 1987, p. 13, fig. 12. It can be implemented, for example, on the K155LA3 chip (see A.S.Partin, V.G. Borisov, Introduction to Digital Technology. - M.: Radio and Communications, 1987, p. 13).

The electronic key 1.12.5 is designed to connect clock pulses from the output of the pulse generator 1.12.4 to the control input of the reading register 1.12.1 during the time when the signal of permission to pass them arrives at the control input of the electronic key 1.12.5 from the output of the counter 1.12.6. The electronic key diagram 1.12.5 is similar, for example, to the electronic key diagram 1.12.2 described earlier.

The counter 1.12.6 is designed to count N ₁ clock pulses arriving at its information input. During the counting of N ₁ clock pulses from the output of the counter 1.12.6 to the control input of the electronic key 1.12.5 receives an enable signal. The number _of clock pulses N ₁ to be counted is written to the counter 1.12.6 through its counter coefficient setting input, implemented as an R-bit bus with parallel transmission, and written to it upon receipt of a write control signal to its write control input. The information input of the counter 1.12.6 operates in the “subtracting input” mode, and when the next clock pulse enters the information input of the counter, the unit is subtracted from the number N ₁ written to the counter. Upon reaching the count of clock pulses, the enable signal at the output of the counter 1.12.6 is changed to a signal prohibiting the passage of clock pulses through the electronic key 1.12.5. The counter circuit 1.12.6 is known and is given, for example, in the book of V.L.Shilo, Popular digital microcircuits. Directory. - M.: Radio and Communications, 1987, p. 90, Fig. 1.67.

The adder 1.13 is designed to sum modulo 2 the sequence of the secret embed key coming from the output of the first memory block of the embed key 1.14 to the input “embed key”, and the sequence of the digital watermark of the electronic image block coming from the output of FCVZB 1.12 to the input of the “TsVZ block” with the formation of the output of the adder 1.13 summed digital watermark block of the electronic image. The adder circuit 1.13 is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 108, Fig.5.5. It can be implemented, for example, on the KM155IM3 microcircuit (see Digital and analog integrated circuits: a reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova, etc. Edited by S.V. Yakubovsky. - M.: Radio and Communications, 1989, p. 50).

The first embedding key memory block (PBPCV) 1.14 is designed to store and read the value of the embedding secret key in the form of a binary sequence. The PBPKV 1.14 scheme is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 138, Fig. 5.28. It can be implemented on a ROM chip KM1608RT1 (see Digital and analog integrated circuits: a reference / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova and others. Edited by S.V. Yakubovsky. - M .: Radio and communications, 1989, p. 317).

The digital watermark embedding unit (BVCVZ) 1.15 shown in FIG. 12 is intended to embed the summarized digital watermark of the electronic image block in the same block. BVCVZ 1.15 consists of shift registers (RG) 1.15.1 and 1.15.3, register block 1.15.2, multiplexer (MX) 1.15.4, switch block 1.15.5, parallel / serial register (RG) 1.15.6 and block select 1.15.7. The input of the shift register 1.15.1, implemented as a Q-bit bus with parallel transmission, is the Q-bit information input of the Huffman sequence of the BVCVZ 1.15, the information input of the register block 1.15.2, implemented as an S-bit bus with parallel transmission, It is an S-bit informational input “coincidence number” of BVVCVZ 1.15, the informational input of shift register 1.15.3 is an informational input of “coincidence number” of BVCVZ 1.15. S Q-bit information inputs of the selection block 1.15.7 are the corresponding Q-bit information inputs of the “sequence of pairs” of the BVCVZ 1.15. The control input “selection of the least significant bit of the address” (A ₁ ) of the multiplexer 1.15.4 is the information input “summed TsVZ” BVVSVZ 1.15. The control input “address high order bits” of multiplexer 1.15.4 (A ₂ , A ₃ , ..., A _{S + 1} ), implemented as an S-bit bus with parallel transmission, is connected to the S-bit output of the register block 1.15.2. The first information input of the switching block 1.15.5, implemented as a Q-bit bus with parallel transmission, is connected to the output of the shift register 1.15.1. The output of the multiplexer 1.15.4, implemented as a Q-bit bus with parallel transmission, is connected to the second information input of the switching unit 1.15.5. The output of the selection block 1.15.7, implemented as a Q-bit bus with parallel transmission, is connected to the Q-bit information input of the 1.15.4 multiplexer. The control input of the switching block 1.15.5 is connected to the output of the shift register 1.15.3. The output of the switching block 1.15.5, implemented as a Q-bit bus with parallel transmission, is connected to the information input of the parallel / serial register 1.15.6, the output of which is the output of the BVCVZ 1.15. The control input of the BVCVZ 1.15 record is the control input of the shift registers 1.15.1, 1.15.3, block register 1.15.2 and parallel / serial register 1.15.6. The control input for reading BVVVZ 1.15 is the control input for reading the shift registers 1.15.1, 1.15.3, the block of registers 1.15.2 and the parallel / serial register 1.15.6.

Shift register 1.15.1 is intended for recording binary sequences of the Huffman code of an electronic image block arriving at its information input, and then reading them to the output. Writing is performed when a recording control signal is received at its control input; reading is performed when a reading control signal is received at its reading control input. The scheme of the shift register 1.15.1 is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 121, Fig. 5.16b. It can be implemented, for example, on the K144IR2 microcircuit (see A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M .: Radio and communications, 1983, p. 122).

The block of registers 1.15.2 is designed to record the numbers of the matched sequences of the Huffman code of the electronic image block, arriving at its information input, and then reading them to the output. Recording is carried out upon receipt of a recording signal recording at its control input, reading is performed upon receipt of a read signal at its reading control input. The block of registers 1.15.2 consists of S identical shift registers (RG) 1.15.2.1, 1.15.2.2, ..., 1.15.2.S. The control inputs of the record and the control inputs of reading the shift registers 1.15.2.1, 1.15.2.2, ..., 1.15.2.S are connected to the corresponding control inputs of the block of registers 1.15.2. The scheme of the shift registers 1.15.2.1, 1.15.2.2, ..., 1.15.2.S is similar, for example, to the scheme of the shift register 1.15.1 described earlier.

The shift register 1.15.3 is intended for writing the sequence of binary values coming from its information input “presence of coincidence” from the output of the same name PVSP 1.5 and then reading it to the output. Writing is performed when a recording control signal is received at its control input; reading is performed when a reading control signal is received at its reading control input. The shift register scheme 1.15.3 is known and is given, for example, in the book by A.A. Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 121, Fig. 5.16b. It can be implemented, for example, on the K144IR2 microcircuit (see A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M .: Radio and communications, 1983, p. 122).

The multiplexer 1.15.4 is designed to select a binary sequence from pairs of binary sequences received at its Q-bit information input. The selection is carried out in accordance with the address signals, consisting of the signal for selecting the least significant bit of the address (A ₁ ) received at the control input "selection of the least significant bit of the address" of the multiplexer 1.15.4, and signals for the selection of the most significant bits of the address (A ₂ , A ₃ , ..., A _{S + 1} ) arriving at the control input “address high order bits” of this multiplexer. The selected binary sequence from the output of the 1.15.4 multiplexer, implemented as a Q-bit bus with parallel transmission, is fed to the second information input of the switching unit 1.15.5. The multiplexer 1.15.4 circuit is known and is given, for example, in the book: G.I. Pukhalsky, T.Ya. Novoseltsev, Design of discrete devices on integrated circuits. - M: Radio and communications, 1990, pp. 99-110, Fig. 3.8. It can be implemented, for example, on a 555KP2 chip (see G.I. Pukhalsky, T.Ya. Novoseltsev, Designing discrete devices on integrated circuits. - M: Radio and communications, 1990, p. 105, Fig. 3.10).

The switching block 1.15.5 is designed to connect one of its two information inputs to the output in accordance with the value of the control signal supplied to its control input. If the control signal has a zero binary value, then the first information input of the switching block 1.15.5 is connected to the output. If the control signal has a single binary value, then the second information input is connected to the output. The switching block 1.15.5 consists of Q identical managed switches (UP) 1.15.5.1, 1.15.5.2, ..., 1.15.5.Q. The scheme of such controlled switches is known and is given, for example, in the book of V.L.Shilo, Popular CMOS chips. Directory. - M .: Jaguar, 1993, p. 22.

Parallel / serial register 1.15.6 is intended for converting parallel-readable binary signals at its Q-bit information input into a serial binary signal at its output. Writing to parallel / serial register 1.15.6 is performed when a write control signal is received at its control input, and reading is received when a read control signal is received at its control input. The parallel / serial register circuit is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for the formation and processing of complex signals. - M.: Radio and Communications, 1983, p. 121, Fig. 5.16a. It can be implemented, for example, on the K155IR13 microcircuit (see A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 122).

The selection block 1.15.7 is used to select from S Q-bit information inputs the “sequence of pairs” of the BVCVZ 1.15 in accordance with the signal on the S-bit output of the block of registers 1.15.2 and connect the selected Q-bit information input of the “sequence of pairs” of the BVCVZ 1.15 to Q-bit information input of the multiplexer 1.15.4. The selection block 1.15.7 consists of S identical selection modules 1.15.7.1, ..., 1-15.7.S and Q of the same combining schemes 1.15.7.S + 1, ..., 1.15.7.S + Q. The Q-bit information input of the selection module 1.15.7.1 is connected to the first Q-bit information input of the “sequence of pairs” of the BVCVZ 1.15, and so on, the Q-bit information input of the selection module 1.15.7.S is connected to the S-th Q-bit information input “Sequence of pairs” BVCVZ 1.15, etc. The control input of the selection module 1.15.7.1 is connected to the output of the shift register 1.15.2.1 of the block of registers 1.15.2 and so on, the control input of the selection module 1.15.7.S is connected to the output of the shift register 1.15.2.S of the block of registers 1.15.2. The first outputs of the selection modules 1.15.7.1, ..., 1.15.7.S are connected to the inputs of the same circuit of the combining circuit 1.15.7.S + 1 and so on, the Qth outputs of the selection modules 1.15.7.1, ..., 1.15.7.S are connected to the inputs of the same name combining circuit 1.15.7.S + Q.

Each selection module 1.15.7.1, ..., 1.15.7.S consists of Q electronic keys (EC) 1.15.7.1.1, ..., 1.15.7.1.Q, ..., 1.15.7.S.1, ..., 1.15. 7.SQ, designed to connect the corresponding bit of the corresponding Q-bit information input of the “sequence of pairs” BVVVZ 1.15. The information inputs of electronic keys 1.15.7.1.1, ..., 1.15.7.1.Q are the Q-bit information input of the selection module 1.15.7.1, etc. Interconnected control inputs of electronic keys 1.15.7.1.1, ..., 1.15.7.1.Q are the control input of the selection module 1.15.7.1, etc. The schemes of these electronic keys are similar, for example, to the electronic key scheme 1.12.2 described earlier.

The combining circuit 1.15.7.S + 1 is intended for combining the signals from the outputs of the electronic keys 1.15.7.1.1, ..., 1.15.7.S.1 and connecting the output signal to the first bit of the Q-bit information input of the multiplexer 1.15.4 and so on further, the combining circuit 1.15.7.S + Q is intended for combining the signals from the outputs of Q-x in its module for selecting electronic keys 1.15.7.1.Q, ..., 1.15.7.SQ and connecting the output signal to the Qth digit Q- bit information input of the same multiplexer. The union schemes 1.15.7.S + 1, ..., 1.15.7.S + Q are similar, for example, to the union scheme 1.5.S + 1 described earlier.

The transmission unit 1.16 is designed to transmit an electronic image certified by a digital watermark over the transmission channel. The transmission block diagram 1.16 is known and described, for example, in the book: Information Security in Mobile Communication Systems: A Textbook for High Schools / A.A. Chekalin, A.V. Zaryaev, S.V. Skryl, V.A. Vokhmintsev, etc. . - 2nd ed., Rev. and add. - M .: Hot line - Telecom, 2005, p. 15, Fig. 1.2.2.

The receiving unit 2.1 is intended for receiving from an electronic image transmission channel. The scheme of the receiving unit 2.1 is known and described, for example, in the book Information Protection in Mobile Communication Systems: a textbook for universities / A.A. Chekalin, A.V. Zaryaev, S.V. Skryl, V.A. Vokhmintsev, etc. - 2nd ed., Rev. and add. - M .: Hot line - Telecom, 2005, p. 15, Fig. 1.2.2.

The Huffman sequence extractor of the received block (VPHPB) 2.2 shown in FIG. 13 is intended to extract from the received electronic image of binary sequences the Huffman code of the received block of the electronic image.

VPHPB 2.2 consists of a shift register (RG) 2.2.1, a coincidence block 2.2.2, a memory block 2.2.3, a pulse generator (GI) 2.2.4, a read control unit 2.2.5, a counter (ST) 2.2.6, and a decoder (DT) 2.2.7. The input of the shift register 2.2.1 is the information input of the VPHPB 2.2, the output of this register, implemented as a Q-bit bus with parallel transmission, is the Q-bit output of the VPHPB 2.2 and is simultaneously connected to the first group of information inputs of the matching block 2.2.2. The output of the memory block 2.2.3, implemented as a Q-bit bus with parallel transmission, is connected to the second group of information inputs of the block 2.2.2 matches. The output of the pulse generator 2.2.4 is connected to the information input of the reading control unit 2.2.5, the output of which is connected to the control input of the reading of the shift register 2.2.1. The output of the coincidence block 2.2.2, implemented as a Q-bit bus with parallel transmission, is connected to the group of control inputs of the read control block 2.2.5. The information input of the counter 2.2.6 is the control input of the read VPHPB 2.2. The output of the counter 2.2.6, implemented as an L-bit bus with parallel transmission, where L = log ₂ Q, is connected to the inputs of the same name as the decoder 2.2.7, the output of which, implemented as a Q-bit bus with parallel transmission, is connected to the group control inputs of the memory block 2.2.3. The control input of the shift register entry 2.2.1, the control inputs of the coincidence block 2.2.2, the pulse generator 2.2.4 and the counter 2.2.6 are the control input of the recording of the ICPF 2.2.

The shift register 2.2.1 is intended for sequential recording of the received electronic image in the form of a binary sequence and subsequent parallel reading to the Q-bit output of the VPHPB 2.2 of the binary sequences of the Huffman code of the received block of the electronic image extracted from it. Writing is performed when a recording control signal is received at its control input; reading is performed when a reading control signal is received at its reading control input. In essence, the shift register 2.2.1 is a serial-parallel shift register. The scheme of the shift register 2.2.1 is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 121, Fig. 5.16b. It can be implemented, for example, on the K155IR1 microcircuit (see V.M.Shilo, Popular Digital Microcircuits: Reference Book. - M.: Radio and Communications, 1987, pp. 104-106, Fig. 1.75).

Coincidence block 2.2.2 is intended to highlight the binary sequences of the Huffman code of the received block of the electronic image matching the binary sequences included in one of the preformed pairs of binary sequences. Coincidence block 2.2.2 consists of Q groups of comparators and Q combining schemes 2.2.2.2Q + 1, 2.2.2.2Q + 2, ..., 2.2.2.3Q. The first group of comparators includes two-digit comparators 2.2.2.1, ..., 2.2.2.2, the second group of comparators includes three-digit comparators 2.2.2.3, ..., 2.2.2.4, etc. In the first group of comparators, the outputs of comparators 2.2.2.1, ..., 2.2.2.2 are connected to the inputs of the combining circuit 2.2.2.2Q + 1, in the second group of comparators the outputs of comparators 2.2.2.3, ..., 2.2.2.4 are connected to the inputs of the combining circuit 2.2.2.2 Q + 2, etc. The first inputs of each category of comparators 2.2.2.1, ..., 2.2.2.2Q are the inputs of the first group of information inputs of the coincidence block 2.2.2. The first inputs of the first category of comparators 2.2.2.1, ..., 2.2.2.2Q are connected to the output of the first category of the shift register 2.2.1, the first inputs of the second category of comparators 2.2.2.1, ..., 2.2.2.2Q are connected to the output of the second category of the shift register 2.2. 1 etc. The second inputs of each category of comparators 2.2.2.1, ..., 2.2.2.2Q are the inputs of the second group of information inputs of the coincidence block 2.2.2. The second inputs of the first category of comparators 2.2.2.1, ..., 2.2.2.2Q are connected to the first category of the Q-bit bus with parallel transfer of the output of the memory block 2.2.3, the second inputs of the second category of comparators 2.2.2.1, ..., 2.2.2.2Q are connected to second category of this tire, etc. The control inputs of the comparators 2.2.2.1, ..., 2.2.2.2Q are the control input of the block 2.2.2 matches.

The outputs of the combining circuits 2.2.2.2Q + 1, 2.2.2.2Q + 2, ..., 2.2.2.3Q are the output of the matching block 2.2.2, implemented as a Q-bit bus with parallel transmission. The output of the first combining circuit 2.2.2.2Q + 1 is connected to the control input of the first counter 2.2.5.1 of the reading control unit 2.2.5, the output of the second combining circuit 2.2.2.2Q + 2 is connected to the control input of the second counter 2.2.5.2 of this block, etc. d.

The scheme of comparators 2.2.2.1, ..., 2.2.2.2Q is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 108, Fig. 5.6. They can be implemented, for example, on the K564IP2 chip (see A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 109). The union scheme 2.2.2.2Q + 1, 2.2.2.2Q + 2, ..., 2.2.2.3Q is known as the logical element “OR” and is given, for example, in the book: G.I. Pukhalsky, T.Ya. Novoseltsev , Design of discrete devices on integrated circuits. - M.: Radio and Communications, 1990, pp. 33-36, Fig. 2.1. It can be implemented, for example, on the 155LE7 chip (see G.I. Pukhalsky, T.Ya. Novoseltsev, Designing discrete devices on integrated circuits. - M.: Radio and Communications, 1990, p. 39, Fig. 2.3) .

The memory block 2.2.3 is designed to store and read binary sequences that are part of one of the preformed pairs of binary sequences. The memory block 2.2.3 consists of Q memory elements (ES) 2.2.3.1, 2.2.3.2, ..., 2.2.3.Q, in each of which the corresponding binary sequence is included in one of the previously generated pairs of binary sequences. The same category of outputs of the outputs 2.2.3.1, 2.2.3.2, ..., 2.2.3.Q are combined and are the output of the 2.2.3 memory block, implemented as a Q-bit bus with parallel transmission. The control inputs of the EC 2.2.3.1, 2.2.3.2, ..., 2.2.3.Q are a group of control inputs of the 2.2.3 memory block. The control signal, which transfers the corresponding ES to the read state at the output of the recorded binary sequence, is supplied alternately to the control input of one of the described ES. The electronic circuit 2.2.3.1, 2.2.3.2, ..., 2.2.3.Q is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 138, Fig. 5.28. ЭП 2.2.3.1, 2.2.3.2, ..., 2.2.3.Q can be implemented, for example, on the KM1608RT1 ROM chip (see Digital and analog integrated circuits: reference book / S.V. Yakubovsky, L.I. Nisselson, V I.I. Kuleshov et al. Edited by S.V. Yakubovsky. - M.: Radio and Communications, 1989, p. 317).

The pulse generator 2.2.4 is designed to generate a sequence of clock pulses counted by the reading control unit 2.2.5. The formation of a sequence of clock pulses begins when a control signal is received at the control input of the pulse generator 2.2.4. The pulse generator circuit 2.2.4 is similar, for example, to the pulse generator circuit 1.10.10 described earlier.

The reading control unit 2.2.5 is designed to control the reading of the output of the shift register 2.2.1 of the selected binary sequences of the Huffman code of the received block of the electronic image. The reading control unit 2.2.5 consists of Q counters (CT) 2.2.5.1, 2.2.5.2, ..., 2.2.5.Q and a combining scheme 2.2.5.Q + 1. The information inputs of the counters 2.2.5.1, 2.2.5.2, ..., 2.2.5.Q are combined and are the information input of the reading control unit 2.2.5. The output of the combining circuit 2.2.5.Q + 1 is the output of the reading control unit 2.2.5. The outputs of the counters 2.2.5.1, 2.2.5.2, ..., 2.2.5.Q are connected to the corresponding inputs of the combining circuit 2.2.5.Q + 1. In each of the counters, the corresponding counting coefficient is pre-recorded: in the first counter 2.2.5.1 - the value of the counting coefficient 2, in the second counter 2.2.5.2 - the value of the counting coefficient 3, etc. The control inputs of the counters are a group of control inputs of the reading control unit 2.2.5. When a control signal is received at the control input of the selected counter through the combining circuit 2.2.5.Q + 1, a read signal is received at the read control input, which determines the number of bits read to the output of the shift register 2.2.1 that make up the selected binary sequence of the Huffman code of the received block of the electronic image .

The circuit of the counters 2.2.5.1, 2.2.5.2, ..., 2.2.5.Q is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 128, Fig. 5.19. Counters 2.2.5.1, 2.2.5.2, ..., 2.2.5.Q can be implemented, for example, on the K561IE11 microcircuit (see V.M.Shilo, Popular digital microcircuits: Reference book. - M.: Radio and communications, 1987, p. 244, fig. 2.44).

The integration scheme 2.2.5.Q + 1 is known as the “OR” logical element and is given, for example, in the book: G.I. Pukhalsky, T.Ya. Novoseltsev, Design of discrete devices on integrated circuits. - M.: Radio and Communications, 1990, pp. 33-36, Fig. 2.1. It can be implemented, for example, on the 155LE7 chip (see G.I. Pukhalsky, T.Ya. Novoseltsev, Designing discrete devices on integrated circuits. - M.: Radio and Communications, 1990, p. 39, Fig. 2.3) .

Counter 2.2.6 is intended for counting clock pulses arriving at its information input. The information input of the counter 2.2.6 is the control input of the reading of VPHPB 2.2. The output of the counter 2.2.6, implemented as an L-bit bus with parallel transmission, is connected to the input of the decoder 2.2.7. The control input of the counter 2.2.6 is the control input of the VPHPB 2.2 record. The counter scheme 2.2.6 is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 127, Fig. 5.18. The counter 2.2.6 can be implemented, for example, on the K561IE2 chip (see V.M.Shilo, Popular digital microcircuits: Reference book. - M.: Radio and communication, 1987, p. 236, Fig. 2.36a).

The decoder 2.2.7 is designed to control the sequential reading of binary sequences from the outputs of the ES 2.2.3.1, 2.2.3.2, ..., 2.2.3.Q included in the memory block 2.2.3. The output of the decoder 2.2.7, implemented in the form of a Q-bit bus with parallel transmission, is connected to the group of control inputs of the memory block 2.2.3. In accordance with the clock pulses counted by counter 2.2.6, the signal from the output of the decoder 2.2.7 is fed to the control input of one of the ES 2.2.3.1, 2.2.3.2, ..., 2.2.3.Q, from the output of which the corresponding binary sequence is read.

The Huffman decoder 2.3 is intended for decoding binary sequences of the Huffman code of a received block of an electronic image by replacing them with preset values of the quantized Fourier coefficients of the block of the electronic image. The Huffman decoder 2.3 is physically a memory module that converts the parallel-readable Q-bit binary sequences of the Huffman code of the received block of the electronic image into the corresponding G-bit values of the quantized Fourier coefficients of this block. In N × N cells of the memory module, G-bit values of the quantized Fourier coefficients of the electronic image block are pre-recorded. The addresses of the cells of the memory module are the binary sequences of the Huffman code of the received block of the electronic image corresponding to the values of the quantized Fourier coefficients of the received block of the electronic image pre-recorded in it. From the output of the memory module, the values of the quantized Fourier coefficients of the received block of the electronic image are read, the moment of reading is determined by the control signal of reading, received at its control input of reading. The Huffman decoder 2.3 scheme is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 138, Fig. 5.28. The Huffman decoder 2.3 can be implemented, for example, on the KM1608RT1 ROM chip (see Digital and analog integrated circuits: a reference book / S.V. Yakubovsky, L.I. Nisselson, V.I. Kuleshova, etc. Edited by S.V. Yakubovsky. - M.: Radio and Communications, 1989, p. 317).

The dequantizer 2.4 shown in FIG. 14 is intended for dequantizing the values of the quantized Fourier coefficients of the received block of the electronic image. In the dequantizer 2.4, N × N values of the quantization coefficients of the Fourier coefficients of the electronic image block are pre-recorded. To dequantize the quantized Fourier coefficients of the received block of the electronic image, their values are multiplied by the value of the corresponding quantization coefficient.

Dequantifier 2.4 consists of a memory block 2.4.1, a multiplier (MPL) 2.4.2, a counter 2.4.3, and a switch (MX) 2.4.4. The G-bit information input of the dequantizer 2.4 is the G-bit information input of the “quantized Fourier coefficients” (X ₁ ) of the multiplier 2.4.2. The group of N × N outputs of the memory block 2.4.1 implemented in the form of G-bit buses with parallel transmission is connected to the group of N × N information inputs (X ₁ , X ₂ , ..., X _{N × N} ) of the switch 2.4.4 . The output (Y) of the switch 2.4.4, implemented in the form of a G-bit bus with parallel transmission, is connected to the information input of the “value of the quantization coefficients” (X ₂ ) of the multiplier 2.4.2. The output of the counter 2.4.3, implemented as a K-bit bus with parallel transmission, is connected to the control input (Address) of the switch 2.4.4. The control inputs of the reading of the memory block 2.4.1 and the multiplier 2.4.2, as well as the input of the counter 2.4.3 are combined and are the control input of the reading of the dequantizer 2.4. The output of the multiplier 2.4.2, implemented in the form of an M-bit bus with parallel transmission, where G≤M, is the M-bit output of the dequantizer 2.4.

The memory block 2.4.1 is designed to store N × N values of the quantization coefficients of the Fourier coefficients of the received block of the electronic image. The circuit of the memory block 2.4.1 is similar, for example, to the circuit of the memory block 1.3.1 described earlier.

The multiplier 2.4.2 is designed to multiply the values of the quantization coefficients of the Fourier coefficients of the received block of the electronic image by the corresponding values of the quantization coefficients. The multiplier scheme 2.4.2 is similar, for example, to the multiplier scheme 1.3.2 described earlier.

The counter 2.4.3 is intended for generating control signals connecting through the switch 2.4.4 the output of the memory element selected from the transmitter 2.4.1.1, 2.4.1.2, ..., 2.4.1.N × N to the information input “quantization coefficient values” of the multiplier 2.4. 2. The counter layout 2.4.3 is similar, for example, to the counter layout 1.3.3 described earlier.

The switch 2.4.4 is designed to connect, in accordance with the control signals generated by the counter 2.4.3, the output signals of the memory element selected from the transmitter 2.4.1.1, 2.4.1.2, ..., 2.4.1.N × N to the information input "quantization coefficient values" of the multiplier 2.4 .2. The switch 2.4.4 is similar, for example, to the switch 1.3.4 described earlier.

The inverse Fourier transform block 2.5 is designed to perform the inverse Fourier transform of the received block of the electronic image. Over the N × N values of the Fourier coefficients of the received block of the electronic image in the inverse Fourier transform block 2.5, the inverse Fourier transform is performed, as a result of which N × N brightness values of the pixels of this block are formed. The block diagram of the inverse Fourier transform 2.5 is known and is given, for example, in RF patent 2125290, Arithmetic device for performing fast Hartley-Fourier transform. It can be implemented, for example, on the Xilinx XCV100-4 programmable logic circuits of the Virtex series (see Xilinx Electronic Product Catalog, 2003, pp. 129-133).

The third quantizer 2.6 is designed to quantize the brightness values of the pixels of the received block of the electronic image. In the third quantizer 2.6, N × N values of the quantization coefficients of brightness of pixels of the received block of the electronic image are pre-recorded. These values are equal to the corresponding values of the quantization coefficients of brightness of the pixels of the electronic image block, previously recorded in the second quantizer 1.8. The third quantizer 2.6 is similar, for example, to the second quantizer 1.8. The procedure for establishing the values of the quantization coefficients of brightness of pixels of a received block of an electronic image is described, for example, in the book A. Dilgin, P. Sementilli, M. Marcellin, Progressive image coding using trellis coded quantization / IEEE Trans. on Image Processing. No. 11, 1997, p.1240-1253.

The received block sequence generator (FPPB) 2.7 is intended for generating a binary sequence of a received block of an electronic image by concatenating the quantized pixel brightness values of this block. In FPPB 2.7, binary sequences of quantized pixel brightness values of a received block of an electronic image are sequentially recorded from the first to the (N × N) th so that the beginning of the next binary sequence is written close to the end of the previous binary sequence. The sequential recording of binary sequences of quantized pixel brightness values of the received block of the electronic image is controlled by recording control signals received at the recording control input of the sequence former of the received block 2.7. The sequential reading of the binary sequence of the received electronic image block is controlled by the read control signals received at the read control input of the sequence former of the received block 2.7. The sequence shaper circuit of the received block 2.7 is similar, for example, to the sequence shaper circuit of block 1.9 described previously.

The received unit authenticator shaper (FAPB) 2.8 is intended for generating the authenticator of the received electronic image block. The FAPB 2.8 scheme is similar, for example, to the circuit of the authenticator block 1.10 described earlier.

The second block of memory of the authentication key 2.9 is designed to store the value of the secret authentication key. The scheme of the second memory block of the authentication key 2.9 is similar, for example, to the scheme of the first memory block of the authentication key 1.11 described earlier.

The second memory block pairs of sequences 2.10 is designed to store binary sequences of pre-formed pairs. The scheme of the second memory block of pairs of sequences 2.10 is similar, for example, to the scheme of the first memory block of pairs of sequences 1.6 described earlier.

The second matching sequence extractor (HSPF) 2.11 shown in FIG. 15 is designed to identify matching sequences from binary sequences of the Huffman code of the received block of the electronic image, read from the output of the Huffman sequence extractor of the received block 2.2, and binary sequences included in one of the preformed pairs binary sequences recorded in the second block of memory pairs of sequences 2.10.

VVSP 2.11 consists of S Q-bit comparators 2.11.1, 2.11.2, ..., 2.11.S, three combining units 2.11.S + 1, 2.11.S + 2, 2.11.S + 3 and two electronic keys (EC) 2.11.S + 4, 2.11.S + 5. The number S is equal to twice the number of preformed pairs of binary sequences recorded in the second memory block of pairs of sequences 2.10. The first inputs of the Q bits of the comparators 2.11.1, 2.11.2, ..., 2.11.S are implemented as a Q-bit bus with parallel transmission. The first inputs of the same name Q bits of the comparators 2.11.1, 2.11.2, ..., 2.11.S are combined and are the Q-bit information input of the Huffman sequence of the VVSP 2.11. The second inputs of the Q bits of the comparator 2.11.1 are the first Q-bit information input of the “sequence of pairs” of the VVSP 2.11, the second inputs of the Q bits of the comparator 2.11.2 are the second Q-bit information input of the “sequence of pairs” of the VVSP 2.11, etc. The outputs of the comparators 2.11.1, 2.11.2, ..., 2.11.S are also connected to the inputs of the unit of the same name 2.11.S + 1, the output of which is the “presence of coincidence” VVSP 2.11 output.

The outputs of the comparators with odd numbers 2.11.1, ..., 2.11.S-1 are connected to the corresponding inputs of the combining unit 2.11.S + 2, and the outputs of the comparators with even numbers 2.11.2, ..., 2.11.S are connected to the corresponding inputs of the combining unit 2.11 .S + 3. The output of the combining unit 2.11.S + 2 is connected to the control input of the electronic key 2.11.S + 4, and the output of the combining unit 2.11.S + 3 is connected to the control input of the electronic key 2.11.S + 5. The information inputs of electronic keys 2.11.S + 4 and 2.11.S + 5 are connected respectively to signal sources with zero and single values, and their outputs are combined and are the “identification” output of VVSP 2.11. The control inputs for reading comparators 2.11.1, 2.11.2, ..., 2.11.S are combined and are the control input for reading the VVSP 2.11.

The same comparators 2.11.1, 2.11.2, ..., 2.11.S are intended to identify matching sequences of the Huffman code of the received block of the electronic image and binary sequences of length Q bits included in one of the preformed pairs of binary sequences. When such a match is detected, the output of the corresponding comparator at a time determined by the control signal at its control input, a single binary signal appears. The scheme of comparators 2.11.1, 2.11.2, ..., 2.11.S is similar, for example, to the scheme of comparators 1.5.1, 1.5.2, ..., 1.5.S described earlier.

The combining circuit 2.11.S + 1 is designed to combine the signals from the outputs of the comparators 2.11.1, 2.11.2, ..., 2.11.S. When any of the comparators is activated, a single binary signal appears at the output of the combining circuit 2.11.S + 1. The union scheme 2.11.S + 1 is similar, for example, to the union scheme 1.5.S + 1 described earlier.

Combining schemes 2.11.S + 2 and 2.11.S + 3 are intended for combining signals from the outputs of comparators with odd numbers 2.11.1, ..., 2.11.S-1 and, accordingly, signals from the outputs of comparators with even numbers 2.11.2, ..., 2.11 .S. The appearance of the output signal of the unit level of the combining scheme 2.11.S + 2 means that the sequence of the Huffman code of the received block of the electronic image is detected, which coincides with the first binary sequence included in one of the preformed pairs of binary sequences. Accordingly, the appearance of the output signal of the unit level of the combining scheme 2.11.S + 3 means that the sequence of the Huffman code of the received block of the electronic image is detected, which coincides with the second binary sequence included in one of the preformed pairs of binary sequences. The union schemes 2.11.S + 2 and 2.11.S + 3 are similar, for example, to the union scheme 1.5.S + 1 described earlier.

Electronic keys 2.11.S + 4 and 2.11.S + 5 are intended for switching signals with zero and single values, respectively, to the output "identification" of the second selector of matching sequences 2.11. Switching of the required signals is performed when the corresponding electronic key 2.11.S + 4 or 2.11.S + 5 is received at the control input of a single level control signal. The electronic key schemes 2.11.S + 4 and 2.11.S + 5 are similar, for example, to the electronic key scheme 1.12.2 described earlier.

The second matching sequence counter (VSSP) 2.12 is designed to count the number N ₂ matching sequences from binary sequences of the Huffman code of the received block of electronic images and binary sequences included in one of the pre-generated pairs of binary sequences. The scheme of VSSP 2.12 is similar, for example, to the scheme of the first counter of matching sequences 1.7 described earlier.

The adder 2.13 is designed to sum modulo 2 the sequence of the secret embed key, which is input to the “embed key”, with a binary signal, which is input to the “identification” input. The adder circuit 2.13 is similar, for example, to the adder circuit 1.10.3 described previously.

The digital watermark extraction unit (BICWZ) 2.14, shown in FIG. 16, is designed to extract the digital watermark of the received electronic image block from the output signal of the adder 2.13. BICVZ 2.14 consists of three electronic keys (EC) 2.14.1, 2.14.2, 2.14.5, an inverter 2.14.3 and a counter (ST) 2.14.4. The information inputs of electronic keys 2.14.1 and 2.14.5, the input of the inverter 2.14.3 and the control input of the electronic key 2.14.1 are combined and are the information input “summed signal” of BICVZ 2.14. The S-bit informational input “number of matches” of BICCW 2.14 is the information input of “setting the account coefficient” (Set) of the counter 2.14.4, the recording control input of which (Rec.) Is the control input of the BICCW 2.14 record. The output of the electronic key 2.14.5 is the output of BICVZ 2.14. The output of the inverter 2.14.3 is connected to the information and control inputs of the electronic key 2.14.2, the output of which, connected to the output of the electronic key 2.14.1, is connected to the information input “subtraction” (-1) of the counter 2.14.4, the output of which is connected to the control the input of the electronic key 2.14.5.

The electronic key 2.14.1 is intended for switching signals with a single value to the information input “subtraction” (-1) of the counter 2.14.4. Inverter 2.14.3 is intended for converting signals with a zero value arriving at its input into signals with a single value. The electronic switch 2.14.2 is intended for switching signals with a single value from the output of the inverter 2.14.3 to the information input “subtraction” (-1) of the counter 2.14.4. Thus, the combination of electronic keys 2.14.1, 2.14.2 and inverter 2.14.3 provides the input to the information input "subtraction" (-1) of the counter 2.14.4 signals with a single value upon receipt of the information input “summed signal” BICVZ 2.14 signals with a single or zero value. The electronic key scheme 2.14.1 and 2.14.2 is similar, for example, to the electronic key scheme 1.12.2 described earlier. The circuit of the inverter 2.14.3 is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 106, Fig. 5.4. Inverter 2.14.3 can be implemented, for example, on the K155LE1 microcircuit (see V.M.Shilo, Popular digital microcircuits: Handbook. - M.: Radio and communications, 1987, p. 46, Fig. 1.27).

The counter 2.14.4 is designed to control the extraction from the output of the adder 2.13 of a digital watermark of the received electronic image block. To do this, through the information input “setting the counting coefficient” (Set) of counter 2.14.4, it records the number N _{2 of} matching sequences from binary sequences of the Huffman code of the received block of the electronic image and binary sequences included in one of the preformed pairs of binary sequences. The moment of recording is determined by the receipt of a recording control signal (Rec.) On its control input. Each signal with a unit value, arriving at the information input “subtraction” (-1) of the counter 2.14.4, reduces the number written to it by a unit value. When the counter 2.14.4 reaches zero, its output signal supplied to the control input of the electronic key 2.14.5 changes from allowing switching signals through this electronic key to a prohibiting signal. The counter scheme 2.14.4 is similar, for example, to the counter scheme 1.12.3 described earlier.

The electronic key 2.14.5 is designed to read from the output signal of the adder 2.13 the binary sequence of the digital watermark of the received block of the electronic image. To do this, through the electronic key 2.14.5 read the first N ₂ bit signals from the output of the adder 2.13 upon receipt of the electronic key enabling the signal switching to the control input of the electronic key. The electronic key diagram 2.14.5 is similar, for example, to the electronic key diagram 1.12.2 described earlier.

The second embedding key memory block 2.15 is designed to store and read the value of the embedding secret key in the form of a binary sequence. The scheme of the second memory block of the embed key 2.15 is similar, for example, to the scheme of the first memory block of the embed key 1.14 described earlier.

Comparison unit 2.16 is designed to identify the coincidence of the digital watermark of the received block of the electronic image with the authenticator of the same block. When this coincidence is detected, the comparison block 2.16 at the time determined by the arrival of the read control signal to its read control input generates a unit level output signal, otherwise it generates a zero level output signal. Physically, the comparison block 2.16 is an N _2- bit comparator. The circuit of the comparison block 2.16 is known and is given, for example, in the book by A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and Communications, 1983, p. 108, Fig. 5.6. It can be implemented, for example, on the K564IP2 microcircuit (see A.A.Sikarev, O.N. Lebedev, Microelectronic devices for generating and processing complex signals. - M.: Radio and communications, 1983, p. 109).

The decision generating block 2.17 is intended to form one of two solutions: the received electronic image block is genuine or the received electronic image block is not authentic. Physically, the decision-making unit 2.17 is a memory module, in the memory cell of which with a single address the information message “genuine EI” is preliminarily written, and in the memory cell with a zero address - information message “non-genuine EI”. The reading of the output signal is carried out at a time determined by the control signal read to the control input of the reading block forming the solution 2.17. The circuit of the block forming the solution 2.17 is similar, for example, to the circuit of the memory elements 2.2.3.1, 2.2.3.2, ..., 2.2.3.Q, described earlier.

The claimed device for the formation and verification of a digital watermarked electronic image works as follows.

On the transmitting and receiving sides of the device, an authentication key memory block 1.11 and a second authentication key memory block 2.9, a first embedding key memory block 1.14 and a second embedding key memory block 2.15, respectively, an authentication secret key and an embedding secret key are also recorded in a Huffman encoder 1.4 and Huffman decoder 2.3, respectively, binary sequences of the Huffman code, and in the first memory block of pairs of sequences 1.6 and the second memory block of pairs of sequences 2.10, respectively - binary different sequences of preformed pairs. Also written in the first quantizer 1.3 N × N values inverse to the corresponding values of the quantization coefficients of the Fourier coefficients of the electronic image block, in the second quantizer 1.8 and the third quantizer 2.6 - N × N values of the quantization coefficients of brightness of the pixels of the electronic image block and N × N values of the quantization of brightness pixels of the received block of the electronic image, respectively, in the dequantizer 2.4 - N × N values of the quantization coefficients of the Fourier coefficients of the block of the electronic image.

On the transmitting side of the device, the electronic image separation unit 1.1 receives an electronic image and is recorded in this unit as a matrix of pixels upon receipt of a recording control signal for recording, shown in Figure 17 (a), at its control input. Upon receipt of the read control signal shown in Figure 17 (b), the verified electronic image is divided into disjoint blocks each of N × N pixels in size and read from its M-bit output to the control input of this block. Then, in the Fourier transform block 1.2, the Fourier transform is performed on the N × N pixel brightness values of the first block of the electronic image, and the Fourier coefficients of the electronic image block generated as a result of N × N are fed to the M-bit information input “Fourier coefficients” (input X ₁ ) multiplier 1.3.2 of the first quantizer 1.3. Upon receipt of the read control signal, shown in figure 17 (c), the counter 1.3.3 generates control signals to the input of the counter, which alternately connect through the switch 1.3.4 the output of the selected memory element 1.3.1.1, 1.3.1.2, ..., 1.3.1 .N × N of the memory block 1.3.1 of the memory element to the M-bit information input “inverse values of the quantization coefficients” of the multiplier 1.3.2. In the multiplier 1.3.2, the Fourier coefficients of the electronic image block are multiplied by the corresponding values that are inverse to the value of the quantization coefficients of the Fourier coefficients of the electronic image block, and the values of the quantized Fourier coefficients of the electronic image block thus generated are read out alternately to the G-bit output of the first quantizer 1.3. They are then encoded in the Huffman 1.4 encoder by replacing the predefined binary sequences of the Huffman code with N × N. Upon receipt of the control read signal, shown in figure 17 (d), to the control input of the read matrix of the memory 1.4.1 of the Huffman encoder 1.4 in accordance with the next value of the quantized Fourier coefficients of the electronic image block received on the information input (Address) of the matrix 1.4.1 the corresponding binary sequence of the Huffman code to the Q-bit output of the Huffman encoder 1.4 is read from the selected cell of the memory matrix.

Then, in the first matching sequences extractor 1.5, matching sequences are extracted from binary sequences of the Huffman code of the electronic image block read from the output of the Huffman encoder 1.4 and binary sequences included in one of the preformed pairs of binary sequences read from the output of the first memory block of pairs of sequences 1.6 . To the first inputs of Q-bit comparators 1.5.1, 1.5.2, ..., 1.5.S, in turn, from the first to the (N × N) th, binary sequences of the Huffman code of the electronic image block are received, to the second inputs of the bits of the same comparators S various binary sequences included in one of the preformed pairs of binary sequences. The reading of binary sequences included in one of the preformed pairs of binary sequences is performed from the first memory block of pairs of sequences 1.6 upon receipt of a read control signal shown in FIG. 17 (e) at its control input.

Upon receipt of the read control signal shown in FIG. 17 (e), to the read control inputs of the described comparators, when one of the binary sequences being compared coincides, one of the comparators is triggered, and its output signal of a single level is transmitted to the S-bit output “matching number ”PVSP 1.5. If there are mismatched sequences from binary sequences of the Huffman code of the electronic image block and binary sequences included in one of the preformed pairs of binary sequences, none of these comparators fails. At the same time, the output signal of the triggered comparator is fed to the input of the combining unit 1.5.S + 1, at the output of which the output signal “presence of coincidence” of PVSP 1.5 is generated. The number N _{1 of} matching sequences from binary sequences of the Huffman code of the electronic image block and binary sequences included in one of the preformed pairs of binary sequences is calculated by the first counter of matching sequences 1.7.

From the M-bit output of the electronic image separation unit 1.1, the pixel brightness values of the next electronic image block are also sent to the M-bit information input of the “pixel brightness value” (input X ₁ ) of the multiplier 1.8.2 of the second quantizer 1.8. Upon receipt of the read control signal, shown in figure 17 (g), to the read control input of the second quantizer 1.8, the counter 1.8.3 generates control signals that alternately connect through the switch 1.8.4 the output of the selected memory elements 1.8.1.1, 1.8.1.2, ... , 1.8.1.N × N of the memory block 1.8.1 of the memory element to the information input of the “quantization coefficient value” of the multiplier 1.8.2. In the multiplier 1.8.2, the brightness values of the pixels of the electronic image block are multiplied by the corresponding values of the quantization coefficients of the brightness of the pixels of the electronic image block, and the N × N quantized values of the brightness of pixels of the electronic image block are successively read to the G-bit output of the second quantizer 1.8.

The quantized brightness values of the pixels of the electronic image block in the form of binary sequences are read into the G-bit information input FPB 1.9. Upon receipt of the write control signal shown in FIG. 17 (h), the binary sequence of the quantized pixel brightness values of the electronic image block is sequentially written from the first to the (N × N) th block control input to the write control input of the sequence 1.9 unit, so that the beginning of the next binary sequence is written close to the end of the previous binary sequence. Upon completion of the recording, upon receipt of the read control signal shown in FIG. 17 (s) to the read control input of the sequence generator of block 1.9, the binary sequence of the electronic image block is sequentially read out from its output to the information input “block sequence” of FAB 1.10. The authentication key FAB 1.10 reads the authentication secret key from the output of the first memory block of the authentication key 1.11. Upon receipt of the control signal read the unit level shown in figure 17 (k), the control input of the FAB 1.10 through the switch 1.10.1 in the register 1.10.2 is written to the binary sequence of the block of the electronic image, and through the switch 1.10.4 in the register 1.10.5 is written binary sequence of the secret authentication key. The same control signal is sent to the standby multivibrator 1.10.9, forming a trigger signal, which starts the pulse generator 1.10.10. From the output of the latter to the control inputs “clock pulses” of registers 1.10.2 and 1.10.5, a sequence of clock pulses is received, which advances the binary sequences recorded in the registers to the output. After writing binary sequences into registers 1.10.2 and 1.10.5, the unit level of the control signal shown in figure 17 (s) changes to zero and the switches 1.10.1 and 1.10.4 are connected to the information inputs of registers 1.10.2 and 1.10. 5 outputs of adders 1.10.3, 1.10.6, respectively. The binary sequences from the outputs “recurrence sequence” and “shifted sequence” of registers 1.10.2 and 1.10.5 are summed modulo 2 in adders 1.10.3, 1.10.6, respectively, and the summed sequences through the switches 1.10.1 and 1.10.4 are written to information inputs of the respective registers. The outputs of the “recurrence sequence” of the registers 1.10.2 and 1.10.5 are summed modulo 2 in the adder 1.10.7, the output signal of which as the authenticator of the electronic image block is read through the public electronic key 1.10.8 from the output of the FAB 1.10 to the information input “block authenticator” shaper digital watermark block 1.12 and sequentially recorded in the shift register 1.12.1.

Through the R-bit informational input “number of matches” of the FCVSB 1.12, the number _{1 of} clock pulses to be counted is recorded in counter 1.12.6. Upon receipt of the write control signal in the form of a sequence of clock pulses shown in Figure 17 (l), the counter 1.12.3 during the counting of N × N pulses gives an enable signal for their passage through the electronic key 1.12.2 to the control input of the shift register 1.12. one. At the end of counting N × N pulses, the output signal of the counter 1.12.3 starts the pulse generator 1.12.4, and it generates a sequence of pulses that are counted by the counter 1.12.6 and simultaneously arrive at the information input of the electronic key 1.12.5. During the counting of N ₁ pulses from the output of the counter 1.12.6, an enable signal is received to the control input of the electronic key 1.12.5, N ₁ pulses are received to the control input of reading the shift register 1.12.1, and from this register the corresponding number is read out sequentially to the output of FCVZB 1.12 binary pulses of a digital watermark electronic image block.

In adder 1.13, a modulo 2 summation of the embedding secret key sequence from the first memory block of embedding key 1.14 is input to the “embed key” input and the digital watermark sequence of the electronic image block coming from FCVZB 1.12 to the “TsVZ block” input is the formation of the output of the adder 1.13 summed digital watermark block.

In BVCVZ 1.15, the summed digital watermark of a block is embedded in the same block of an electronic image. To do this, the next binary sequence of the Huffman code of the electronic image block is received at the input of the shift register 1.15.1, which is written into the shift register by the write control signal shown in figure 17 (m). The S-bit information input of the block of registers 1.15.2 of the BVCVZ 1.15 is simultaneously fed and, according to the recording control signal shown in Figure 17 (m), binary sequences are written that indicate the numbers of matches of the binary sequences of the Huffman code of the electronic image block and binary sequences included in one from preformed pairs of binary sequences. Corresponding binary sequences of pairs arrive at S Q-bit information inputs of the selection block 1.15.7 BVCVZ 1.15. The information input of the shift register 1.15.3 BVVSVZ 1.15 is received and by the control signal of the recording shown in figure 17 (m), the binary sequence “presence of coincidence” is recorded.

Upon receipt of the control read signal, shown in figure 17 (n), to the control input of the reading of the register block 1.15.2 from its output to the control input "select the upper bits of the address" of the multiplexer 1.15.4 receives signals of the highest bits of the address. Signals of the least significant bit of the address go to the control input “selection of the least significant bit of the address” of the same multiplexer through the information input “summed TsVZ” BVTSVZ 1.15. At the same time, the signals of the S-bit output of the block of registers 1.15.2 are fed to the corresponding S-bit control inputs of the block of selection 1.15.7, providing the connection through the corresponding modules of choice 1.15.7.1, ..., 1-15.7.S of the signals of the selected Q-bit information input of the block selection 1.15.7 on the Q-bit information input of the multiplexer 1.15.4. The multiplexer 1.15.4 in accordance with these control signals outputs to the second information input of the switching unit 1.15.5 the selected binary sequence of the pair. Upon receipt of the control signal read, shown in figure 17 (n), to the control input of the read register 1.15.3 from its output is read another binary signal to the control input of the switching unit 1.15.5. If the next binary signal has a zero value, then the next binary sequence of the Huffman code of the electronic image block is read from the output of the switching block 1.15.5, that is, there is no embedding, otherwise the selected binary sequence of the pair is replaced, that is, the next bit of the summed digital watermark of the block is embedded electronic image. Sequentially in parallel / serial register 1.15.6, the next binary sequence is written from the output of the switching block 1.15.5, which is the next binary sequence of the Huffman code verified by the digital watermark of the electronic image block, and upon receipt of the read control signal shown in figure 17 (n) , to the control input of reading in parallel / serial register 1.15.6 it is sequentially read to the output of the BVCVZ 1.15 and through the transmission unit 1.16 certified by a digital leading th sign of the first block of the electronic image is transmitted on a transmit channel. The second block of the electronic image, etc., is also certified with a digital watermark.

The receiving unit 2.1 receives from the transmission channel an electronic image. Binary sequences of the Huffman code of the received electronic image are extracted from the received electronic image in the HSPF 2.2. The received electronic image in the form of a binary sequence upon receipt of the write control signal shown in FIG. 17 (o) is written to it at the control input of the shift register record 2.2.1. The specified control signal also starts the pulse generator 2.2.4, and the signals from its output are counted by the counters 2.2.5.1, 2.2.5.2, ..., 2.2.5.Q of the reading control unit 2.2.5. Upon receipt of the control signal read, shown in figure 17 (p), to the information input of the counter 2.2.6 they are counted and control the decoder 2.2.7. At the outputs of the decoder 2.2.7, read control signals are sequentially generated that arrive at the corresponding read control input from the output of the selected memory element 2.2.3.1, 2.2.3.2, ..., 2.2.3.Q of the 2.2.3 memory block of the corresponding binary sequence. If the first bits of the binary sequence at the output of the shift register 2.2.1 coincide with the bits read from the output of the selected memory element 2.2.3.1, 2.2.3.2, ..., 2.2.3.Q of the corresponding binary sequence, then the block of matches 2.2.2 from its corresponding output gives a control signal to the control input of one of the Q counters 2.2.5.1, 2.2.5.2, ..., 2.2.5.Q of the reading control unit 2.2.5. The selected counter controls the receipt of the required number of read signals at the shift control input 2.2.1 of the shift register, and the selected binary Huffman code sequence of the received electronic image is read from the shift register 2.2.1 output. Then they are decoded in the Huffman decoder 2.3 by replacing the received block of the electronic image with the preset values of the quantized Fourier coefficients. Upon receipt of the read control signal shown in FIG. 17 (p) to the read control input of the Huffman decoder 2.3, in accordance with the next binary value of the Huffman code received in the decoder information input of the received electronic image, the corresponding value of the quantized Fourier coefficient is read from the decoder the received block of the electronic image.

In dequantizer 2.4, the values of the quantized Fourier coefficients of the received block of the electronic image are dequantized. Upon receipt of the read control signal shown in FIG. 17 (c) at the input of the counter 2.4.3, its output signal controls the connection to the information input of the “quantization coefficient value” (X ₂ ) of the multiplier 2.4.2 through the output signal switch 2.4.4 of the corresponding element memory block memory 2.4.1. In the multiplier 2.4.2, the values of the quantization coefficients of the Fourier coefficients of the received block of the electronic image are multiplied by the corresponding values of the quantization coefficients, as a result, the M-bit values of the dequantized Fourier coefficients of the received block of the electronic image are read into the inverse Fourier transform block 2.5, in which N × N values are generated pixel brightness of this block.

Next, in the third quantizer 2.6, the pixel luminance values of the received block of the electronic image are quantized upon receipt of the read control signal shown in FIG. 17 (t). The actions performed in the third quantizer 2.6 are similar, for example, to the actions in the second quantizer 1.8 described previously.

The quantized pixel luminance values of the received block of the electronic image in the form of binary sequences are read to the G-bit information input FPPB 2.7. Upon receipt of the recording control signal shown in FIG. 17 (y), the FPPB 2.7 recording control input sequentially writes, from the first to the (N × N) th, binary sequences of quantized pixel brightness values of the received electronic image block so that the beginning of the next binary sequence was written close to the end of the previous binary sequence. At the end of the recording, upon receipt of the read control signal shown in FIG. 17 (f), the binary sequence of the received block of the electronic image is sequentially read from the output to the control input of the read FPPB 2.7 to the information input “sequence of the received block” of FAPB 2.8. To the control input of the reading FAPB 2.8 receives the control signal read, shown in figure 17 (x). The actions performed in FAPB 2.8 are similar, for example, to the actions in the authenticator block 1.10 described earlier.

Then, in VVSP 2.11, matching sequences are detected from binary sequences of the Huffman code of the received block of the electronic image, read from the output of the Huffman sequence extractor of the received block 2.2, and binary sequences included in one of the preformed pairs of binary sequences recorded in the second memory block of the pairs of sequences 2.10 . The first inputs of the Q-bit comparators 2.11.1, 2.11.2, ..., 2.11.S alternately, from the first to the (N × N) th, receive binary sequences of the Huffman code of the received block of the electronic image, and the second inputs of the bits of the same comparators S different binary sequences are included in one of the preformed pairs of binary sequences. The reading of binary sequences included in one of the preformed pairs of binary sequences is performed from the second memory block of pairs of sequences 2.10 upon receipt of a read control signal shown in FIG. 17 (c) at its control input.

Upon receipt of the read control signal shown in FIG. 17 (h) to the read control inputs of the described comparators, when one matches the binary sequences being compared, one of the comparators is triggered, and its output signal of a single level is transmitted to the “presence of coincidence” output of VVSP 2.11. At the same time, the output signal of the tripped comparator with an even or odd number goes to the inputs of the combining units 2.11.S + 2 or 2.11.S + 3. The triggered combining unit generates a signal of zero or unit level at the output “identification” of VVSP 2.11.

In VSSP 2.12, the number N ₂ matching sequences from binary sequences of the Huffman code of the received block of the electronic image and binary sequences included in one of the preformed pairs of binary sequences is calculated. In adder 2.13, the modulo 2 summation of the sequence of the secret embed key, which is input to the “embed key", is performed with the binary signal that goes to the "identification" input.

In BICVZ 2.14, the digital watermark of the received block of the electronic image is extracted from the output signal of the adder 2.13. Upon receipt of the write control signal, shown in figure 17 (w), the number N _{2 of} matching sequences is written to the write control input of the counter 2.14.4. Zero or single value of the signal supplied to the information input “summed signal” BICVZ 2.14, causes a decrease by a single value of the state of the counter 2.14.4. When calculating the binary signals arriving at the information input “summed signal” of BICVZ 2.14, the counter 2.14.4 allows reading of the first N ₂ binary signals from them to the output of BICVZ 2.14.

In comparison block 2.16, the digital watermark of the received electronic image block is compared with the authenticator of the same block. When this coincidence is detected, the comparison block 2.16 at the time determined by the arrival of the read control signal to its read control input, shown in figure 17 (n), generates a unit level output signal, otherwise it forms a zero level output signal. In the decision generation block 2.17, one of two solutions is formed: the received electronic image block is genuine or the received electronic image block is not authentic. The reading of the output signal is carried out at a time determined by the control signal read to the control input of the reading of the block forming decision 2.17, shown in figure 17 (e).

To confirm the possibility of achieving the formulated technical result, a computer simulation of the inventive device for the formation and verification of an electronic image certified by a digital watermark was carried out. Immunity authenticated digital watermark from the electronic image intruder deliberate action to change its content was estimated from the value of the probability P _nepod decision block true false electronic image formed infringer. In the information and telecommunication systems transmit electronic images should be performed P _nepod ≤R _{dop, dop} where P - the allowable probability of acceptance by the recipient as a genuine false electronic image. Typically, the value of P _{add is} set equal to 10 ^-9 , which is recommended, for example, in state standard 28147-89. Information processing systems. Cryptographic protection. Cryptographic conversion algorithm. - M.: Gosstandart of the USSR. 1989. The simulation result revealed that with increasing magnitude of the value of P N _{1 nepod} rapidly decreases and at the value N ₁ ≥32 provided _nepod ≤R P _ext = 10 ^-9.

The figure 18 shows the dependence of P _nep on the values of N ₁ . Inequality N ₁ ≥32, as a rule, holds for blocks of electronic images of size 8 × 8 pixels or more, as described, for example, in the book by D.Vatolin, A. Ratushnyak, M. Smirnov, V. Yukin, Data compression methods. The device archivers, image and video compression. - M.: DIALOGUE-MEPhI, 2002, p. 309.

Also, as a result of computer modeling, it was revealed that the complexity of the intruder calculating a digital watermark for embedding in a false electronic image, which will be recognized by the recipient as authentic, is estimated at least 10 ²⁰ ... 10 ³⁰ computational operations. Calculations of such complexity are practically impossible for the intruder at the current level of development of computer technology.

The studies confirm that when using the proposed device for the formation and verification of an electronic image certified by a digital watermark, the security of the electronic image, verified by the sender's digital watermark, from the deliberate actions of the violator to change the content of the electronic image is increased.

Claims (1)

A device for generating and checking an electronic image certified by a digital watermark (CEH), comprising, on the transmitting side, a Fourier transform unit, the M-bit input of which is connected to the M-bit output of the electronic image separation unit, where M≥2, the information input of which is the information input of the device , shaper of the authenticator of the block, the information input "authentication key" and the output of which are connected, respectively, to the output of the first memory block of the authentication key and to the information the input of the “block authenticator” of the digital watermark generator of the block, the output of which is connected to the input of the digital watermark of the adder, the output of which is connected to the information input of the digital watermark of the digital watermark embedding unit, the output of which is connected to the input of the transmission block, the output of which is the output of the transmitting side of the device, and the electronic image separation unit, the unit authenticator, and the digital watermark embedding unit are provided with reading control inputs, The digital watermark of the unit is equipped with a recording control input, and the electronic image separation unit and the digital watermark embedding unit are also equipped with recording control inputs, to which the corresponding control signals are received, on the receiving side of the device, a receiving unit, the input of which is connected to the output of the transmitting channel the device side, the authenticator of the received block, the information input of the authentication key of which is connected to the output of the second memory block of the key ay identification, a digital watermark extraction unit and a decision generating unit, the outputs of which are “genuine electronic image” and “non-genuine electronic image” are the corresponding outputs of the device, the received unit authenticator driver and the decision generating unit are provided with read control inputs, and the digital watermark extraction unit equipped with a control input of the record, which receives the corresponding control signals, characterized in that on the transmitting side of the devices additionally introduced the first quantizer, Huffman encoder, the first matching sequence extractor, the first sequence pair memory block, the first matching sequence counter, the second quantizer, the block sequence generator and the first embedder key memory block, the output of which is connected to the adder embed key input, M- the bit output of the electronic image separation unit is connected to the M-bit information input of the second quantizer, the G-bit output of which is connected to G- a single information input of the block sequence generator, where 2≤G≤M, the output of which is connected to the information input "block sequence" of the block authenticator generator, the M-bit output of the Fourier transform block is connected to the M-bit information input of the first quantizer, whose G-bit output connected to the G-bit information input of the Huffman encoder, the Q-bit output of which is connected to the Q-bit information input of the "Huffman sequence" of the first matching sequences and to the same information input of the digital watermark embedding unit, where Q≥2, S-bit output "match number" of the first matching sequences extractor is connected to the same S-bit information input of the digital watermark embedding unit, where S≥2, output " the presence of coincidence "of the first selector of matching sequences is connected to the same information input of the digital watermark embedding unit and to the input of the first counter of matching sequences the one whose R-bit output is connected to the R-bit information input "number of matches" of the digital watermark generator of the block, where R≥log ₂ (N × N), from the first to the S-th Q-bit outputs of the first block memory of pairs of sequences connected to the corresponding Q-bit information inputs of the “sequence of pairs” of the first matcher of matching sequences and the digital watermark embedding unit, the first quantizer, Huffman encoder, the first matcher of matching sequences, the first memory block pa p sequences, the second quantizer and the block sequence generator are equipped with read control inputs, and the block sequence generator is additionally equipped with a write control input to which the corresponding control signals are received, and on the receiving side, a Huffman sequence extractor of the received block, a Huffman decoder, a dequantizer, a reverse block are additionally introduced Fourier transform, third quantizer, shaper of the received block sequence, second memory block there are two pairs of sequences, a second selector of matching sequences, a second counter of matching sequences, an adder, a second embedding key memory block and a comparison block, the information inputs of which are “received block authenticator” and “removed CEH” of which are connected to the outputs of, respectively, the authenticator of the received block and block digital watermark extraction, R-bit information input "number of matches" of the digital watermark extraction unit is connected to the R-bit output of the second a coincident sequence meter, the input of which is connected to the “presence of coincidence” output of the second highlighter of coincident sequences, the Q-bit information input “Huffman sequence”, and the first through Sth Q-bit information inputs of “sequence of pairs” of which are connected, respectively, to Q -digit output of the Huffman sequence extractor of the received block and to the corresponding Q-bit outputs of the second memory block of the pairs of sequences, the output of the "identification" of the second allocator is the same x sequences connected to the input of the adder of the same name, the “embed key” input of which is connected to the output of the second embedding key memory block, the output of the reception block is connected to the information input of the Huffman sequence extractor of the received block, whose Q-bit output is connected to the Q-bit information input of the Huffman decoder The G-bit output of which is connected to the G-bit information input of the dequantizer, the M-bit output of which is connected to the M-bit input of the inverse transform unit urye, the M-bit output of which is connected to the M-bit information input of the third quantizer, the G-bit output of which is connected to the G-bit information input of the received block sequence generator, the output of which is connected to the information input "received block sequence" of the received block authenticator, the output of the adder is connected to the information input "summed signal" of the digital watermark extraction unit, the output of the comparison unit is connected to the information input of the solution is formed, moreover, the Huffman sequence extractor of the received block, the Huffman decoder, the dequantizer, the third quantizer, the received block sequence generator, the second sequence pair memory block, the second matching sequence allocator and the comparison unit are equipped with read control inputs, and the Huffman sequence extractor of the received block and generator the sequence of the received block is additionally equipped with control inputs of the record, which come from appropriate control signals.

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