RU2475812C1 - Apparatus for multiplying numbers in "1 out of 4" code - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: apparatus has a tetrad shift register, a second multiplier register, a partial product unit, a product carry unit, a first carry adder unit, an adder unit, a sum carry flip flop unit, a second carry adder unit, a result register in "1 out of 4" code, a result carry unit, a control unit, n-bit quaternary inputs in "1 out of 4" code of the first and second multipliers, where n is the number of quaternary bits of multipliers, a shift input and error feature outputs.

EFFECT: faster operation of the device.

7 dwg, 3 tbl

Description

The invention relates to computer technology, in particular to data processing devices, and can be used to build computer systems with increased reliability of obtaining the result and with high speed.

A device for multiplying numbers (RU No. 2021633 C1, IPC G06F 7/52, claimed 10.07.1991, publ. 10/15/1994), containing n single-digit multiplication nodes (n - multiplicity of multiplicable), two groups of n buffer registers, n combination adders of the first group and (n + 1) combinational adders of the second group, (n + 1) registers of the intermediate result, n transfer triggers, (n-1) switches and a correction generation unit with corresponding connections.

The disadvantage of this device is that in the operating mode does not check the correctness of the issued data, which, in turn, does not make it possible to increase the reliability of the issued results.

The reasons that impede the achievement of the required technical result are the lack of tools that provide the ability to verify the correctness of the issued data code.

Known accelerated multiplier on neurons (RU No. 2323288 C2, IPC G06F 7/52, announced April 3, 2006, publ. 10/20/2007, BI No. 11), containing a data input unit, a register register multiplier, a register register multiplier, a summation block, a block a decoder, a result storage unit, a control unit. In the multiplier, binary numbers are multiplied. The product of the numbers is obtained as the sum of the partial products, by analyzing the least significant bits of the factor, a shift of two bits of the factor to the right, and a shift of the multiplier to the left.

The disadvantage of this device is that in the operating mode does not check the correctness of the issued data, which, in turn, does not make it possible to increase the reliability of the issued results.

The reasons that impede the achievement of the required technical result are the lack of tools that provide the ability to verify the correctness of the issued data code.

A device for multiplying numbers modulo is known (RF patent No. 2143723 C1, IPC G06F 7/52, G06F 7/72, claimed July 29, 1998, publ. 12/27/99), containing the first and second binary code converters for the first internal module, the first and the second binary code converters for the second internal module, the first to sixth blocks of AND elements, a table computer, unitary code converters for the first and second modules, and an adder modulo. The device provides multiplication of numbers in the system of residual classes for two modules.

The disadvantage of this device is that it does not check the correctness of the issued data, which, in turn, does not make it possible to increase the reliability of the issued results.

The reasons that impede the achievement of the required technical result are the lack of tools that provide the ability to verify the correctness of the issued data code.

The closest device of the same purpose to the claimed invention in terms of features is the prototype device for multiplying numbers in the code "1 of 4" (RU No. 2251144 C1, IPC G06F 7/52, claimed October 28, 2003, published on April 27, 2005, BI No. 12), which contains a notebook shift register, a partial product block, an adder block, a result register in the “1 of 4” code, a control block, quadruple inputs in the “1 of 4” code of the first and second device factors, a device recording input, device clock input, constant 0 input in the code "1 of 4" and outputs a sign of error, while the tetrad shift register contains n tetrads, where n is the number of quadruple bits of the factors, and the inputs of the quadruple bits in the code “1 of 4” of the first factor of the device are connected to the information inputs of the corresponding tetrads of the tetrad shift register, the information inputs of the quadruple bits shift to in the code “1 of 4” from the first to the (n-1) th tetrad are connected, respectively, with the outputs of the four-digit bits in the code “1 of 4” from the second to the n-th tetrad of the tetrad shift register, the information inputs of the quadruple shift are the rows of the nth notebook are connected to the input of the constant 0 in the code “1 of 4”, the block of partial products contains n nodes of partial works in the code “1 of 4”, the inputs of the first group of notebooks of the block of partial works connected to the outputs of the lower first notebook of the notebook register shift, and the adder block contains (n-1) the adder in the code "1 of 4", and the result register in the code "1 of 4" contains 2n tetrads of four-digit bits, and the information inputs are from the first to the nth tetrads of four-digit bits of the result register in the code "1 of 4" are connected to the outputs of a hundred group of quaternary digits, respectively, with the second in the (n + 1) th tetrad of quaternary digits of the result register in the code "1 of 4", the outputs of the quaternary digits with the (n + 2) th in the 2nth tetrad of the result register in the code "1 of 4 "are connected respectively to the inputs of the four-digit bits of the second term from the first to (n-1) -th adders in the code" 1 of 4 ", while the control unit contains 2n nodes of the code" 1 of 4 ", the outputs of which are connected to the outputs a sign of a device error, inputs from the first to (n + 1) -th nodes of the code control block "1 of 4" are connected to the outputs of the quad digits, respectively, from the first to (n + 1) th tetrad of four-digit digits of the result register in the code "1 of 4", the input of the recording device is connected to the input of the register of the result in the code "1 of 4" and the input of the register of the notebook shift register, the clock input the device is connected to the sync inputs of the result register in the code "1 of 4" and the notebook shift register.

The disadvantage of this device is that at each step of the calculation, the values of the current accumulated sum of partial products are set on the result register after a time equal to the sum of the time for calculating the bitwise products, plus the time for the bitwise summation and plus the time for sequential correction of n bitwise transfers.

The reasons that impede the achievement of the required technical result are that the device lacks the means to store bitwise transfers and communications for transferring them to the next step.

The technical result of the invention is to increase the speed of the device.

The proposed device is distinguished by the regularity of the connections of nodes and links, as well as providing increased reliability of the output, due to bitwise control of the operation of multiplication of numbers, and uniform distribution of energy over the discharges during operation, which is especially important when implementing device equipment in the form of VLSI.

The specified technical result in the implementation of the invention is achieved by the fact that in the device for multiplying numbers in the code "1 of 4", containing a notebook shift register, a block of partial products, a block of adders, a register of results in the code "1 of 4", a control unit, quadruple inputs digits in the code “1 of 4” of the first and second device factors, the input of the device recording, the input of the device clock, the input of the constant 0 in the code “1 of 4” and the outputs of the error indicator, while the notebook shift register contains n tetrads, where n is the number of quaternary p rows of factors, and the inputs of the four-digit bits in the code "1 of 4" of the first factor of the device are connected to the information inputs of the corresponding notebooks of the tetrad shift register, the information inputs of the shift of the four-digit bits in the code "1 of 4" from the first to (n-1) -th notebook connected respectively to the outputs of the four-digit bits in the code “1 of 4” from the second to the nth tetrads of the notebook shift register, the information inputs of the four-digit bits of the nth notebook are connected to the input of the constant 0 in the code “1 of 4”, the block of partial works contains n y of partial works in the code "1 of 4", and the inputs of the first group of tetrads of the block of partial works are connected to the outputs of the lower first tetrad of the notebook shift register, and the adder block contains (n-1) the adder in the code "1 of 4", and the result register in the code “1 of 4” contains 2n tetrads of quadruple digits, and the information inputs from the first to the fifth tetrades of quadruple digits of the result register in the code “1 of 4” are connected to the outputs of the oldest group of quadruple digits, respectively, from the second to (n + 1) 4th tetrad tetrad register and the result in the code “1 of 4”, the outputs of the four-digit bits from the (n + 2) -th through the 2nth notebook of the result register in the code “1 of 4” are connected respectively to the inputs of the four-digit bits of the second term from the first to (n-1 ) of the adders in the code "1 of 4", while the control unit contains 2n nodes of the code "1 of 4", the outputs of which are connected to the outputs of the device error indicator, inputs from the first to (n + 1) -th nodes of the control unit the codes “1 of 4” are connected to the outputs of the four-digit bits, respectively, from the first to (n + 1) -th tetrads of the four-digit bits of the result register in the code “1 of 4 ", the input of the recording device is connected to the input of the register of the result register in the code" 1 of 4 "and the input of the write register of the notebook shift, the input of the clock pulses of the device is connected to the clock inputs of the register of the result in the code" 1 of 4 "and the register of the notebook shift, the register of the second factor is additionally entered , a hyphenation block of a product, a first block of hyphenation adders, a block of summation transfer triggers, a second block of hyphenation adders, a hyphenation block of a result, and a shift input, and the register of the second factor contains n notebooks, the inputs being the digits in the code "1 of 4" of the second factor of the device are connected to the information inputs of the corresponding tetrads of the register of the second factor, and the outputs of the register are connected to the inputs of the second group of the corresponding tetrads of the block of partial products, while the transfer unit of the product and the first block of transfer adders contain n nodes moreover, the outputs of the tetrads of the block of partial works in the code "1 of 4" are connected to the inputs of the first group of the corresponding nodes of the first block of carry adders, the inputs of the second group of which are dined with outputs in the code “1 of 3” of the corresponding units of the unit of transfers of work, the output of the transfer of nodes of the first block of adders of transfers is connected to the first input of one transfer of the corresponding nodes of the unit of transfers of work, the second input of one transfer and the input of two transfers of nodes of the block of transfers of the product are connected to the same the outputs of the corresponding nodes of the notebooks of the block of partial works in the code "1 of 4", the outputs in the code "1 of 4" from the first to the (n-1) th nodes of the first block of carry-over adders are connected to the corresponding inputs four-digit bits in the code “1 of 4” of the first term, respectively, from the first to the (n-1) th adders of the adder block, the outputs in the code “1 of 4” of the nth node of the first block of adder transfers are connected to the information inputs of the 2nth tetrads of quaternary digits of the result register in the code "1 of 4", while the block of transfer triggers of the sum and the second block of carry adders contain (n-1) nodes, and the inputs of the first group in the code "1 of 4" from the first to (n- 1) of the nodes of the second block of adders carry connected to the information outputs, respectively, with the first o by the (n-1) th adders in the code “1 of 4” of the adder block, the inputs of the second group in the code “1 of 2” from the first to the (n-1) th nodes of the second block of adders of transfers are connected to the corresponding outputs, respectively from the first to (n-1) -th nodes of the sum transfer trigger block, the transfer output from the first to (n-1) -th nodes of the second transfer adder block is connected to the first transfer input of the corresponding nodes of the sum transfer trigger block, the second transfer input of which is connected with carry outputs from the first to the (n-1) -th adders in the code "1 of 4" of the sum block mators, the result transfer block contains (n-1) nodes, the information inputs of the first group in the code "1 of 4" from the first to (n-1) -th nodes of which are connected to the information outputs of the quadruple digits with (n + 2) - 1st through 2nth notebook of the result register in the code "1 of 4", the first inputs of transfers from the first to (n-1) -th nodes of the block of transfers of results are connected to the direct output of the unit in the code "1 of 2", respectively, from the first to ( n-1) -th nodes of the sum transfer trigger block, second transfer inputs from the second to (n-1) -th nodes of the result transfer block are connected to the output and transfers from the first to the (n-2) th nodes of the transfer block of the result, the second input of the transfers of the first node of the transfer block is connected to a zero constant, the inputs from the (n + 2) th to 2 n-th nodes of the code control block "1 of 4 "are connected to the outputs of the four-digit bits, respectively, from the first to the (n-1) th nodes of the result transfer block in the code" 1 of 4 ", the input of the device clock pulses is also connected to the clock inputs of the nodes of the product transfer block and the sum transfer trigger block, the recording input of the device also connected to the input of the register entry of the second som ozhitelya with inputs setting unit transfers work units and block transfer amount triggers shift input device connected to the input offset of the first to (n-1) -th transfer unit assemblies result.

Figure 1 presents the functional diagram of the proposed device for multiplying numbers in the code "1 of 4"; figure 2 presents an embodiment of a node 3 _i block partial works; figure 3 presents an embodiment of a node 6 _i of the adder block in the code "1 of 4"; figure 4 presents an embodiment of a node 10 _i block transfer result; figure 5 presents an embodiment of a node 4 _i block transfers of the product; 6 shows an embodiment of a node 7 _{i of a} block of triggers for transferring a sum; 7 shows timing diagrams of control signals.

A device for multiplying numbers in the code "1 of 4" (Fig. 1) contains a notebook shift register 1, a second factor register 2, a partial product block 3, a product carry unit 4, a first carry adder unit 5, an adder unit 6, a transfer trigger unit sums 7, the second block of carry-over adders 8, the result register in the code “1 of 4” 9, the carry-over block of the result 10, the control unit 11, the inputs of the four-digit bits in the code “1 of 4” of the first B and second A factors of the device, the input of the device record 12, the clock input of the device 13, the input of the constant 0 to the code “1 of 4” 14, the input of the shift 15 and the outputs of the sign of error 16. In this case, the register of the tetrad shift 1 contains n tetrads of four-digit bits in the code “1 of 4” 1 ₁ ... 1 _n , where n is the number of four-digit bits of the factors, and it is intended for the first factor, carries out a shift towards the lower digits one notebook at a time and by entering the constant 0 in the code "1 of 4" from the input 14 to the upper digits, the register of the second factor 2 contains n tetrads of four-digit digits in the code "1 of 4" 2 ₁ ... 2 _n , block of partial products 3 contains n nodes of partial products 3 ₁ ... 3 _n , hyphenation of product 4 contains n hyphenation storage nodes in the code “1 of 3” 4 ₁ ... 4 _n , the first block of hyphenation adders 5 contains n nodes in the code “1 of 4” 5 ₁ ... 5 _n , the adder block 6 contains (n- 1) the adder in the code "1 of 4" 6 ₁ ... 6 _n-1 , the block of transfer triggers of the sum 7 contains (n-1) nodes of the storage of transfers 7 ₁ ... 7 _n-1 , the second block of the adders of transfers 8 contains (n-1 ) nodes in the code "1 of 4" 8 ₁ ... 8 _n-1 , the result register in the code "1 of 4" 9 contains 2n tetrads of quadruple digits 9 ₁ ... 9 _2n , the transfer block of the result 10 contains (n-1) nodes in code "1 of 4" 10 ₁ ... 10 _n-1 , control unit 11 contains 2n nodes ov control in the code "1 of 4" 11 ₁ ... 11 _2n .

The inputs of the four-digit bits in the code “1 of 4” of the first factor B of the device are connected to the information inputs of the corresponding tetrads 1 _{i of the} register 1 of the tetrad shift, the information inputs of the four-digit bits in the code “1 of 4” from the first to the (n-1) th notebook 1 ₁ -1 _{(n-1) are} connected respectively to the outputs of the quaternary digits in the code "1 of 4" from the second to the nth tetrads 1 ₂ -1n of the register 1 of the tetrad shift, the information inputs of the quadruple digits shift of the nth tetrad 1 _{n are} connected with input 14 constants 0 in the code "1 of 4".

The inputs of the four-digit bits in the code "1 of 4" of the second factor A of the device are connected to the information inputs of the corresponding tetrads 2 _{i of} register 2 of the second factor.

The inputs of the first group of nodes 3 _i tetrads of the block of partial products 3 are connected to the outputs of the youngest first notebook 1 _i of the notebook shift register 1, the inputs of the second group of nodes 3 _{i of the} tetrads of the block of partial products 3 are connected to the outputs of the corresponding nodes 2 _{i of the} books of the register 2 of the second factor.

The outputs of nodes 3 _i tetrads of the block of partial works 3 in the code "1 of 4" are connected to the inputs of the first group of the corresponding nodes 5 _{i of the} first block 5 of adders, the inputs of the second group of which are connected to the outputs in the code "1 of 3" of the corresponding nodes 4 _{i of the} block transfers of product 4, transfer output PM1 of nodes 5 _{i of the} first block of transfer adders 5 is connected to the first input of one transfer PM1 of the corresponding nodes 4 _i of the transfer of product of 4, the second input of one transfer P1 and the input of two transfers P2 of which are connected to the outputs of the same name corresponding nodes 3 _i tetrads of the block of partial works 3 in the code "1 of 4".

The outputs in the code “1 of 4” from the first through the (n-1) th nodes 5 ₁ -5 _{(n-1) of the} first block of carry-over adders 5 are connected to the corresponding inputs of the four-digit bits of the first term, respectively, from the first to (n-1) of the nodes 6 ₁ -6 _(n-1) of the adder block 6 in the code "1 of 4", the outputs in the code "1 of 4" of the n-th node 5 _{n of the} first block of carry-over adders 5 are connected to the information inputs of the 2nth notebook 9 _2n quaternary digits of result register 9 in code "1 of 4".

The inputs of the first group in the code "1 of 4" from the first through the (n-1) -th nodes 8 ₁ -8 _{(n-1) of the} second block of carry-over adders 8 are connected to the information outputs, respectively, from the first to (n-1) -th nodes 6 ₁ -6 _(n-1) of the adder block 6 in the code "1 of 4", the inputs of the second group in the code "1 of 2" from the first to (n-1) -th nodes 8 ₁ -8 _{(n-1 ) of the} second block of transfer adders 8 are connected to the corresponding outputs, respectively, from the first through the (n-1) th nodes 7 ₁ -7 _(n-1) of the transfer trigger block of the sum 7, the transfer output of the PS from the first to (n-1) th node 8 ₁ -8 _(n-1) of the second unit carries adders 8 is connected to a first input transferring the respective nodes SS 7 ₁ -7 _(n-1) triggers the transfer unit 7, the sum, the second input transfer ns which is connected to the outputs of shifts ns respectively to the first to (n-1) th adders June ₁ -6 _(n-1) in the code "1 of 4".

Information inputs from the first to the nth tetrads 9 ₁ -9 _{n of the} four-digit bits of the register of the result 9 in the code "1 of 4" are connected to the outputs of the senior group of the four-digit bits, respectively, from the second to the (n + 1) -th notebook 9 ₂ -9 _{( n + 1)} four-digit bits of the register of result 9 in the code "1 of 4", outputs of the four-digit bits from the (n + 2) -th through the 2nth tetrads 9 _{(n + 2)} -9 _{2n of the} register of the result of 9 in the code "1 of 4 4 "are connected respectively to the inputs of the four-digit bits of the second term from the first to the (n-1) th nodes 6 ₁ -6 _(n-1) of the adder block 6 in the code" 1 of 4 "and the information inputs of the first group in the code" 1 from 4 "from the first to the (n-1) th nodes 10 ₁ -10 _(n-1) of the hyphenation block of the result 10, the first inputs of the transfers of the TP from the first to (n-1) -th nodes 10 ₁ -10 _{(n- 1)} the transfer unit of result 10 is connected to the direct output of the unit unit in the code "1 of 2", respectively, from the first to (n-1) -th nodes 7 ₁ -7 _(n-1) of the transfer trigger block of the sum 7, the second transfer inputs are П from the second by (n-1) th nodes 10 ₂ -10 _(n-1) of the result transfer block are connected to the outputs of transfers P, respectively, from the first by (n-2) -th nodes of 10 ₁ -10 (n-2) block 10 transfers the result, the second input of the first node transfers P transfer unit 10 ₁ is connected constant zero.

The inputs from the first through the (n + 1) th nodes 11 ₁ -11 _{(n + 1)} of the control unit 11 of the code "1 out of 4" are connected to the outputs of the four-digit bits, respectively, from the first to the (n + 1) th notebook 9 ₂ - 9 _{(n + 1)} quaternary digits of result register 9 in the code "1 of 4", inputs from the (n + 2) -th through 2n-th nodes 11 _{(n + 2)} -11 _{n of the} block 11 control code "1 of 4 "are connected to the outputs of the quaternary digits, respectively, from the first through the (n-1) th nodes 10 ₁ -10 _(n-1) of the carry block of the result 10 in the code" 1 of 4 ".

The outputs of 2n nodes 11 ₁ -11 _2n of the control unit 11 of the code "1 of 4" are connected to the outputs 16 of the error sign of the device.

The input 12 of the recording device is connected to the input of the register setting of the result 9 in the code "1 of 4", the input of the register of the notebook shift 1, the input of the register of the second factor 2, with the installation inputs of the nodes of the transfer unit of product 4 and the block of transfer triggers of the sum 7.

The input 13 of the device’s clock pulses is connected to the clock inputs of the result register 9 nodes in the code “1 of 4”, the notebook shift register 1, the product transfer unit 4, and the total transfer trigger unit 7.

The shift input 15 of the device is connected to the shift input from the first through the (n-1) -th nodes 10 ₁ -10 _(n-1) of the transfer block of the result 10.

A possible variant of the partial works node in the code “1 of 4” 3 _i (FIG. 2) contains the first to fourth groups of elements AND 17-20, the group of elements OR 21 and the element OR 22. The group of elements OR 21 contains 4 elements OR, each the group of elements And 17-20 contains 4 elements And, forming a 4 × 4 matrix. The first inputs of the same elements And from the first to the fourth of each group are interconnected and connected to the corresponding binary components of the four-digit discharge of the factor a _3i a _2i a _1i a _0i , which are the second group of inputs of the node 3 _i , the second inputs of the elements And of each group from the first to the fourth interconnected and connected to the corresponding binary components of the four-digit discharge of the factor b _0i b _1i b _2i b _3i , which are the first group of inputs of node 3 _i . The outputs of the matrix of 4x4 AND elements are connected to the inputs of the group of elements OR 21 and the element OR 22 in accordance with the conversion of the input values of the factors into partial products and transfers, shown in table 1, and the outputs of the group of elements OR 21 are the group of outputs of the node 3 _{i of} binary components of the quadruple discharge works with _3i with _2i with _1i with _0i , the output p1 _i of the OR element 22 is the output of one transfer of the node 3 _i , the output p2 _{i of the} first element of the fourth group of elements And 20 is the output of two transfers of the node 3 _i .

A possible variant of the adder node in the code "1 of 4" 6 _i (Fig. 3) contains from the first to the fourth group of elements AND 23-26, a group of elements OR 27 and an element OR 28. The group of elements OR 27 contains 4 elements OR, each group And the elements 23-26 contains 4 elements I. The groups of elements 23-26, similarly to the partial product node 3 _i , form a 4 × 4 matrix, but the matrix outputs are connected to the inputs of the group of OR elements 27 and the OR element 28 in accordance with the conversion of input values in terms of amount and wrapping table 2. Groups and inputs and _{3i 1i} and _2i and _{3i 0i} and b b b _{2i 1i} b _0i is tsya groups of first and second terms node 6 _i adders 6 unit, and outputs element group OR 27 are a group node 6 _i binary components yields quaternary discharge amount s _3i s _2i s _1i s _0i output ns _i OR gate 28 is the output node migration 6 _i .

A possible variant of node 5 _{i of the} first block of adders 5 can be implemented similarly to node 6 _{i of the} block of adders 6, and the second group of inputs includes only three binary components b _2i b _1i b _0i in the code “1 of 3”, and a 4 × matrix is formed 3 and the 4th group of elements And 26 and the corresponding relationships are excluded.

A possible variant of node 8 _{i of the} second block of adders 8 can be implemented similarly to node 6 _{i of the} block of adders 6, and the second group of inputs includes only two binary components b _1i b _0i in the code “1 of 2”, and a 4 × 2 matrix is formed and the 4th and 3rd groups of elements And 26-25 and the corresponding relationships are excluded.

A possible variant of the node 10 _i of the transfer block of the result 10 (Fig. 4) contains the first second group of elements AND 29-30, the group of elements OR 31, element OR 32, element OR NOT 33 and element AND 34. Each group of elements And 29-30 contains 4 AND elements, forming a 4 × 2 matrix, the outputs of which are connected to the inputs of the group of elements OR 31, similarly to the nodes of the adder block 6 in accordance with table 2 with two binary components b _1i b _0i in the code "1 of 2", the outputs of the group of elements OR 31 are the group of outputs of the node 10 _{i of} binary components of the quadruple discharge of the product z _3i z _2i z _1i z _{0i, the} output P _i is the transfer output of the node 10 _i . The first inputs of the OR 32 and OR 33 elements are interconnected and are the external second transfer input P _i-1 from the junior node 10 _i-1 of the transfer block 10, the second inputs of the OR 32 and OR NOT 33 elements are interconnected and connected to the output of the AND 34 element, the inputs of which are the external first transfer transfer TP _i-1 from the junior node 7 _i of the transfer trigger block 7 and the shift input 15. The outputs of the OR 32 and OR 33 elements are binary components of the second term b _1i b _0i for matrix of 4x2 elements.

A possible variant of node 4 _i of the carry unit of product 4 (Fig. 5) contains a synchronous D-flip-flop 35 with an installation input of one, two synchronous D-flip-flops 36-37 with an installation input of zero, an OR-NOT 38 element, an EXCLUSIVE-OR element 39, AND element 40 and OR element 41. Synchronization inputs of triggers 35-37 are interconnected and connected to the external input of SI synchronization 13, the inputs of the initial installation of triggers 35-37 are interconnected and connected to the external input 12 of the initial recording. Logic elements 38-41 convert the inputs of two transfers P2 _i and one transfer P1 _i , from the node 3 _{i of} partial products, and the input of one transfer PM1 _i , from node 5 _{i of the} first block of adders of transfers 5, into the code "1 of 3" in accordance with table 3. The first inputs of the OR-NOT 38, EXCLUSIVE-OR 39 and И 40 elements are interconnected and connected to the external input of one transfer PM1 _i , from node 5 _i , and their second inputs are interconnected and they are connected to the external input one transfer P1 _i , from node 3 _i , the third input of the OR-NOT 38 element is connected to the second input of the IL element And 41 and are connected to the external input of the two transfers P2 _i , from the node 3 _i , the first input of the OR element 41 is connected to the output of the AND 40 element. The output of the OR-NOT 38 element is the lowest first bit b _{0i of the} components in the code “1 of 3” and connected to the information input D of the trigger 35, the output of the EXCLUSIVE-OR element 39 is the second bit b _1i and connected to the information input D of the trigger 36, the output of the element OR 41 is the senior third bit b _2i and connected to the information input D of the trigger 37. Outputs of the triggers 37 -35 are outputs TP1 TP2 _{i i i} TP0 assembly 4 _i per unit 4 noses product code "1 in 3".

A possible version of the node 7 _i block transfer triggers sum 7 (Fig.6) contains a synchronous D-flip-flop 42 with the installation input to zero and having direct and inverse outputs, and an OR element 43. The trigger synchronization input 42 is connected to the external input 13 synchronization SI, the input of the initial installation of the triggers 42 is connected to the external input 12 of the initial recording RECORD. The outputs of the trigger 42 are the outputs b _1i and b _{0i of the} components in the code "1 of 2" and are the outputs of the node 7 _i . The information input D of the trigger 42 is connected to the output of the OR element 43, the first input of which is connected to the external input of one transfer of PS _i from node 8 _i , and the second input is connected to the external input of one transfer of PS _i from node 6 _i , which are also external the inputs of node 7 _i .

A device for multiplying numbers in the code "1 of 4" works as follows.

The numbers of factors B and A are presented in the quaternary system

B = b _n × 4 ^n-1 + ... + b ₂ × 4 ¹ + b ₁ × 4 °,

A = a _n × 4 ^n-1 + ... + a ₂ × 4 ¹ + a ₁ × 4 °,

where n is the number of quaternary digits, a ₁ and b ₁ are the least significant bits, a _n and b _n are the highest bits.

The device works according to the algorithm of multiplication from the least significant bits of the factor and the shift of the accumulated sum of partial products to the right towards the lower bits

Z = B × A = (((b ₁ × (a _n × 4 ^n-1 + ... + a ₂ × 4 ¹ + a ₁ × 4 °) × 4 ^-1 +

+ b ₂ × 4 ¹ × (a _n × 4 ^n-1 + ... + a ₂ × 4 ¹ + a ₁ × 4 °)) × 4 ^-1

+ ... +

+ b _n-1 × (a _n × 4 ^n-1 + ... + a ₂ × 4 ¹ + a ₁ × 4 °)) × 4 ^-1 +

+ b _n × (a _n × 4 ^n-1 + ... + a ₂ × 4 ¹ + a ₁ × 4 °)) × 4 ^-1 ,

where a _i and b _{i are} represented in the code "1 of 4".

Multiplication and summation are carried out according to the corresponding weights of the four-digit digits in the code "1 of 4".

Table 1 shows the codes for converting the input values of the factors into the weekend in the nodes of partial products 3 _i when multiplying the quadruple digits in the code "1 of 4" and the conditions for the formation of one transfer P1 and two transfers P2 to the next four-digit discharge.

Obviously, the occurrence of one P1 _i-1 or two P2 _i-1 transfers from the previous (i-1) -th quadruple discharge does not necessitate the formation of an additional signal of the third transfer, since the maximum value of the partial product code with the active signal of even two transfers P2 _i from the current discharge is 0010 and, therefore, even two transfers P2 _i-1 from the previous discharge will give a result code 1000 without the need for generating an additional transfer signal.

Table 2 shows the codes for converting the input values of the terms into the weekend in adders 6 _i when summing the quadruple digits in the code "1 of 4" and the conditions for the formation of transfer P1.

Obviously, the occurrence of the transfer of P1 _i-1 from the previous (i-1) -th quadruple discharge does not necessitate the formation of an additional transfer signal, since the maximum value of the sum code with the active transfer signal P1 _i from the current discharge is 0100 and, therefore, transferring P1 _i-1 from the previous bit will give a result code of 1000 without the need for generating an additional transfer signal.

The implementation of the multiplication algorithm is based on the hyphenation conservation method. When implementing the multiplication algorithm, transfers of partial products P2 _i , P1 _i and transfers of the sum of partial products P1 that occur at each step of the calculations are not transferred to the corresponding higher digits of the product and the amount, but are stored in the storage blocks of the transfers of the product 4 _i and the transfer of the sum 7 _{i of the} current i-th quadruple discharge. At the next step, the current sum of partial products is shifted towards the lower digits, which is performed when the sum values are transferred from the (i + 1) th node of the result register 9 to the i-th node of the adder 6, and in each i-th bit the summation is shifted the current amount of partial products and the next value of the partial product from node 3 _i and the corresponding stored transfers of the product from node 4 _i and transfers of the sum from nodes 7 _i .

After completing n steps of the algorithm at the next (n + 1) th step, the partial product will be equal to zero, since at each step, when shifting to the notebook shift register 1, the constant 0 in the code "1 of 4" from input 14 is sequentially entered. Therefore, on The (n + 1) -th step is the summation of the current value of the sum of partial works only with saved transfers of works and saved transfers of the amount. Next, the operation of the transfer unit of result 10 is allowed, in which the result is corrected for the values of the stored transfers in nodes 7 ₁ ... 7 _ni . In this case, a sequential interdischarge transfer to the higher bits is performed. At each step of the calculations, the result is monitored in nodes 11 ₁ ... 11 _2n control units 11.

At the beginning of the operation, multiplying the input 12 of the device, the Write signal is sent (Fig. 7), by which the operands of the factor B are recorded in the notebook shift register 1 and the factor A in the register of the second factor 2 and the nodes are set to zero in the code “1 of 4” result register 9, to zero in the code "1 of 3" nodes of the transfer unit of product 4 and to zero in the code "1 of 2" nodes of the block of transfer triggers of the sum 7.

Each of the quaternary digits a _{i of the} factor A is represented by the code "1 of 4" a _3i a _2i a _1i a _0i and is entered in the i-th notebook of register 2, and each of the quadruple digits b _{i of the} factor B is represented by the code "1 of 4" b _3i b _2i b _2i b _0i and is entered in the i-th notebook of the notebook shift register 1. The output of the lower notebook of register 1 is connected to the first group of inputs of all nodes 3 _{i of the} partial products in the code “1 of 4” of the block of partial products 3, into the second groups the inputs of which are supplied with the corresponding quaternary digits in the code "1 of 4" from the register of the second factor 2. Since the node partial products 3 _i unit 3 combination, then a transient time within each node unit 3, the output partial products nodes 3 _i in accordance with the multiplication algorithm set values bitwise multiplication of b × a _n, b ₁ × a _n-1, ... b ₁ × a ₂ , b ₁ × a ₁ and the values of the formed one transfer P1 or two transfers P2 to the next four-digit discharge.

The values of bitwise multiplication from nodes 3 _i are supplied to the groups of second inputs of the corresponding nodes 5 _{i of the} first block of carry adders 5, which are also combinational, and the values of zeros in the code “1 of 3” from nodes 4 _{i of the} zero block of transfers set to zero are fed to the first groups of inputs 4. at work output nodes 5 _i, through the transient within each node unit 5 will be installed bitwise multiplication values, which are applied to respective input group of second nodes 6 _i adders unit 6, and a group of first Rin rows of zeros in the code value "1 of 4" with the following older nodes _{i + 1} 9 9 result register. At the outputs of nodes 6 _i of the adder block 6, which is also combinational, after the transition process only inside each node 6 _i of the adder block 6, bitwise multiplication values will be set that go to the groups of second inputs of nodes 8 _{i of the} second block of adders 8, and to groups of first inputs whose values are zeros in the code "1 of 2" from the set of transfer trigger triggers to zero 7. As a result, at the outputs of the quadruple bits 8 _{i of the} second block of carry adders 8, which is also combinational, after the transition time of the process only inside each node 8 _{i of the} second block of carry-over adders 8, bitwise multiplication values b ₁ × a _n , b ₁ × a _n-1 , ... b ₁ × a ₂ , b ₁ × a ₁ , and also at the inputs the carry-over unit of product 4 and the transfer-trigger block of the sum 7 will set the values of one or two transfers, respectively. The signals in nodes 4 _i of the hyphenation block of product 4 are formed in accordance with table 3 in the code “1 of 3”. From table 3 it follows that for any input values of the factors and the occurrence of two transfers, an additional third transfer to the next category cannot occur. The signals in nodes 7 _i of the carry unit of the sum 7 realize the logical function OR from transfers - PS∨PS and the value is generated in the code “1 of 2”.

On the leading edge of the first SI clock pulse (Fig. 7), the calculated values will be entered in the corresponding bits of the register of result 9, the carry unit of the product 4, and the block of trigger for the transfer of the sum 7. Thus, the values of bitwise multiplication and the values of the product and total transfers in the next bits will be fixed . In addition, on the same front of the SI signal, the factor B is shifted by one quadruple digit in the tetrad shift register 1 and the constant 0 in the code "1 of 4" is entered in the highest bit of register 1.

After that, the inputs of the first group of block 3 of partial products receive the value of the next four-digit discharge b _{2 of} factor B, the outputs of block 3 produce the value of bitwise multiplication b ₂ × a _n , b ₂ × a _n-1 , ... b ₂ × a ₂ , b ₂ × a ₁ and the values of the formed one transfer P1 or two transfers P2 to the next four-digit discharge. At the outputs of nodes 5 _{i of the} first block of carry-over adders 5, the sums of partial products of the i-th quadruple discharge in the code “1 of 4” and transfers in the code “1 of 3” of the i-th category coming from nodes 4 _i of the carry-over blocks of product 4 will be generated saved in the previous step. Then this sum is added to adders 6 _{i of the} first adder block 6 with the accumulated partial sum from register 9 shifted by one quadruple digit towards the lower digits. Then this sum is bitwise added to the 8 _i bits of the second block of carry-over adders 8 with the stored carry sum i-th bit in the previous step of the nodes _i 7 triggers transfer unit amounts 7. Thus, the next partial sum output of the adder unit 8 transfers codes formed with the translations of the previous step that go to the inputs of the nodes of the register 9 of the result, and also transfers are formed to the next bits at the inputs of the transfer unit of product 4 and the block of transfer triggers of the sum 7, which are entered in the register 9 of the result and the transfer units of the product 4 and transfers of the amount 7 along the leading edge of the second clock SI At the same time, the least significant bit of the partial sum of the previous calculation step is shifted by one four-digit bit in the result register 9 in the direction of the least significant bits from the output of the (n + 1) th digit to the n-th digit.

In the future, the calculation process is cyclically repeated.

After applying the n-th SI pulse in the result register 4, a bitwise sum of partial products and bitwise fixation of product transfers in block 4 and sum transfers in block 7 are formed. Next, their bitwise summation is performed in the nodes of the first block of carry totalizers 5, block of adders 6 and second block adders 8, while the first group of inputs of block 3 of partial works from the register 1 notebook receives constant 0 in the code "1 of 4". When the (n + 1) th SI pulse is applied, the summation result is entered into the result register 9 and the transfer unit of the sum 7, and the constant 0 in the code “1 of 4” is entered into the transfer unit of the product 4, since there will be no transfers from the block 3 of products and block 5 adders carry.

At the same time (Fig. 7), the input SHIFT is applied to input 15 and the transfers are carried out with the inter-bit transfer to the higher bits, which is performed at nodes 10 ₁ ... 10 _n-1 , transfer block of result 10 in the code "1 of 4". Since the nodes 10 _i of the transfer blocks are combinational, then after the transition process the senior bits z _2n ... z _{n + 2 the} sums of the partial products will be formed at the outputs of the nodes 10 _n-1 ... 10 ₁ of the transfer block of the result 10. The duration of the SHIFT signal should be longer transient in block 10 and the retention time of the result of the work on the outputs of the device. The least significant bits z _{n + 1} ... z _{1 of the} total sum of partial products Z = A × B are removed from the outputs and nodes 9 _{n + 1} ... 9 ₁ tetrads of four-digit bits of the register of result 9 in the code "1 out of 4".

At each step of the calculations, the outputs of all 2n digits of the quadruple current sums of partial products go to the inputs of the corresponding control nodes of the code "1 of 4" 11 ₁ ... 11 _2n of the control unit 11, since in the absence of a shift signal the nodes 10 ₁ ... 10 _n-1 are transmitted to output of the value of the tetrads of the register of result 9 in the code "1 of 4". In the event of a mismatch of the code in at least one bit z _{i, the} code “1 of 4” at the outputs 16 _{i of the} device will signal Osh.

Combination nodes 3 _i partial works in the code "1 of 4" (Fig.2) block partial works work as follows. Each group of elements And 17-20 contains 4 elements And, forming a 4 × 4 matrix. The binary inputs of the elements And from the first to the fourth groups give the binary components of the quadruple discharge of the factor b _3i b _2i b _1i b _0i to the second inputs of the elements And from the first to the fourth of each group the binary components of the quadruple discharge of the factor a _3i a _2i a _1i a _0i are fed. At sixteen outputs of the matrix of elements And, obviously, only one “1” can appear, the remaining zeros (any other combination, passing through the logical elements of the combination nodes of the block of partial products 3, the first block of adders 5, the block adders 6, the second block adders 8 and writing to the result register 9 in the code “1 of 4” will lead to the occurrence of an error sign signal at one of the outputs of the control unit 11). The outputs of the elements AND groups 17-20 are connected to the inputs of the four groups of elements OR 21 in such a way that at their outputs the necessary result of the partial product is realized in accordance with Table 2. At the same time, at the output of the OR element 22, a signal of the sign of one transfer P1 _{i is formed} and from the output of the first element And the fourth group of elements And 20, the signal of the sign of the second transfer P2 _i to the next four-digit discharge is taken.

The combination nodes 5 _{i of the} first block of carry-over adders 5 summarize a partial product of the current i-th quadruple discharge and the signals of two P2 and one P1 transfers from the previous (i-1) -th bit of partial transfers, stored in nodes 4 _i of the transfer block of product 4. In this case, an active signal can be generated at the transfer outputs PM1 _{i of} nodes 5 _i . The signals of two transfers P2 _i and one transfer P1 _i from the node 3 _{i of} partial works in the code "1 of 4" and one transfer from node 5 _{i of the} first block of adders of transfers of the current i-th category are fed to the inputs of node 4 _i of the transfers of product 4. In accordance with table 3, nodes 4 _i form the transfer value in the code “1 of 3” to the next bit, which is recorded in triggers 35-37. Table 3 indicates that for any input values of the factors and the occurrence of two transfers, an additional third transfer to the next category cannot occur.

The combiners in the code "1 of 4" 6 _i block adders 6 (figure 3) implement the conversion according to table 2. Each group of elements And 23-26 contains 4 elements And, forming a 4 × 4 matrix. The binary inputs of the quadruple category of the term a _0i , _1i , and _2i , and _3i are fed to the first inputs of the elements And from the first to the fourth groups of And 23-26, the binary inputs are fed to the second inputs of the elements And from the first to the fourth of each group And 23-26 the quadruple discharge of the second term b _0i , b _1i , b _2i , b _3i . At sixteen outputs of the matrix of elements And, obviously, only one "1" can appear, the remaining zeros (any other combination, going through the logical elements of the adder 6 _i , the second block of carry-over adders 8 and writing to the result register 9 in the code "1 of 4" will lead to the occurrence of an error sign signal at one of the outputs of the control unit). In the first groups of inputs of adders 6 _i in the code "1 of 4" binary components of the quadruple discharge of the i-th partial product block from nodes 5 _i are fed, and the second groups of inputs are supplied with binary components of the four-digit discharge of the highest (i + 1) th tetrad of the sum from register 9 result. The outputs of the elements AND groups 23-26 are connected to the inputs of the four elements OR of group 27 in such a way that the required bit-wise result of the sum of the partial product is realized at their outputs in accordance with table 2. At the same time, the signal of the transfer sign PS _i to the next is generated at the output of the element OR 28 quadruple discharge.

The combination nodes 8 _{i of the} second block of transfer adders 8 summarize the current sum of the partial product of the i-th quadruple discharge and the transfer signal TP from the previous (i-1) -th discharge stored in nodes 7 _i of the transfer block of amount 7. Moreover, at the transfer outputs PS _i nodes 8 _i can be formed an active signal. The signal of transfer of PS _i from node 8 _i and transfer of PS _i from node 6 _i of the adder block of the current i-th category is fed to the inputs of node 7 _i of the transfer block of sum 7. In nodes 7 _i , the transfer value is generated in the code "1 of 2", as logical sum PS _i ∨PS _i, the next discharge, which is written in the flip-flops 42 _i. Moreover, for any input values of the terms and the formation of transfers, two additional transfers to the next category cannot occur.

As a result of the operation of the device, a 2n-bit multiplication result Z = A × B is generated at the outputs of nodes 10 ₁ ... 10 _n-1 of the carry block of result 10 and nodes 9 ₁ ... 9 _{n + 1} tetrads of four-digit bits of register 9 of the result in the code "1 of 4 "after the (n + 1) -th step of the SI signals and in the presence of a shift signal at the input 15. At each step of the calculations, bitwise control of the operation is carried out and in case of a code mismatch in at least one bit z _{i to the} code" 1 of 4 "on the outputs 16 _{i of the} device will be issued a signal of a sign of error Osh.

Rate the performance of the proposed device.

In the proposed device, the clock cycle of the SI is determined only by the sum of the delays in the passage of signals from four consecutive blocks 3 _i , 5 _i , 6 _i , 8 _i and the transfer formation time in block 7, and does not depend on the bit depth of n factors. Bit depth n defines the number of calculation steps, and is also taken into account only at the (n + 1) -th step in the correction of transfers in the nodes of block 10.

In the prototype, at each step of the calculations, a sequential inter-bit transfer is performed through the (n-1) node in the block of partial works or in the block of adders. Therefore, the period of SI clock pulses in the prototype at each step is directly proportional to the number of bits n and will be approximately equal to the total execution time of the multiplication operation for the proposed device.

Thus, the proposed device has a higher speed, in comparison with the prototype.

The above information allows us to conclude that the proposed device for multiplying numbers in the code "1 of 4" has a regularity of nodes and connections, provides increased reliability of the multiplication result due to bitwise control of the operation, uniform distribution of energy over the discharges during operation and corresponds to the claimed technical result - increase the speed of the device.

Table 1 Quaternary code 0 one 2 3 Multipliers "1 of 4" 0001 0010 0100 1000 0 0001 = 0001 = 0001 = 0001 = 0001 one 0010 = 0001 = 0010 = 0100 = 1000 2 0100 = 0001 = 0100 = 0001 + P1 = 0100 + P1 3 1000 = 0001 = 1000 = 0100 + P1 = 0010 + P2

table 2 Quaternary code 0 one 2 3 The terms "1 of 4" 0001 0010 0100 1000 0 0001 = 0001 = 0010 = 0100 = 1000 one 0010 = 0010 = 0100 = 1000 = 0001 + P1 2 0100 = 0100 = 1000 = 0001 + P1 = 0010 + P1 3 1000 = 1000 = 0001 + P1 = 0010 + P1 = 0100 + P1

Table 3 Inputs Outputs P2 P1 PM1 TP2 TP1 TP0 0 0 0 0 0 one 0 0 one 0 one 0 0 one 0 0 one 0 0 one one one 0 0 one 0 0 one 0 0 one 0 one X X X one one 0 X X X one one one X X X

Claims (1)

A device for multiplying numbers in the "1 of 4" code, containing a tetrad shift register, a partial product block, an adder block, a result register in the "1 of 4" code, a control unit, quadruple inputs in the "1 of 4" code of the first and second device factors, device recording input, device clock input, constant 0 input in the “1 of 4” code and error indicator outputs, while the tetrad shift register contains n tetrads, where n is the number of quadruple bits of the factors, and the inputs of quadruple bits in the code 1 in 4 "of the first multiplies If devices are connected to the information inputs of the corresponding notebooks of the tetrad shift register, the information inputs of the four-digit shift in the code “1 of 4” from the first to the (n-1) -th tetrads are connected respectively to the outputs of the quadruple bits in the code “1 of 4” from the second according to the nth tetrad of the tetrad shift register, the information inputs of the quaternary digit shift of the nth tetrad are connected to the input of the constant 0 in the code “1 of 4”, the block of partial works contains n nodes of partial works in the code “1 of 4”, and the inputs of the first groups of notebooks block hour of different products are connected to the outputs of the lowest first tetrad of the tetrad shift register, and the adder block contains (n-1) the adder in the code “1 of 4”, and the result register in the code “1 of 4” contains 2n tetrads of four-digit digits, and the information inputs with the first by the nth tetrad of tetrads of the result register in the code "1 of 4" are connected to the outputs of the highest group of quaternary digits, respectively, with the second by the (n + 1) of the tetrads of quaternary bits of the register of the result in the code "1 of 4", the outputs of the quaternary bits from the (n + 2) -th through the 2n-th tetrad the result in the code “1 of 4” are connected respectively to the inputs of the four-digit bits of the second term from the first to (n-1) -th adders in the code “1 of 4”, while the control unit contains 2n nodes of the control code “1 of 4”, the outputs of which are connected to the outputs of the device error indicator, the inputs from the first to (n + 1) -th nodes of the code control block "1 of 4" are connected to the outputs of the four-digit bits, respectively, from the first to (n + 1) -th tetrads of the four-digit bits of the result register in the code "1 of 4", the input of the recording device is connected to the input of the installation of the result register in the code "1 of 4" and a notebook shift register entry, the device clock input is connected to the sync inputs of the result register in the code “1 of 4” and the notebook shift register, characterized in that the register of the second factor, the product transfer unit, the first transfer adder block, the sum transfer trigger block, the second block of adders of transfers, the block of transfers of the result and the shift input, and the register of the second factor contains n tetrads, and the inputs of the four-digit bits in the code "1 of 4" of the second factor of the device are connected to inf by the input inputs of the corresponding register notebooks of the second factor, and the register outputs are connected to the inputs of the second group of the corresponding notebooks of the partial product block, while the product carry unit and the first transfer adder unit contain n nodes each, and the outputs of the partial product block notebooks in the code “1 of 4” connected to the inputs of the first group of the corresponding nodes of the first block of carry adders, the inputs of the second group of which are connected to the outputs in the code "1 of 3" of the corresponding nodes of the block of transfers The output of the transfer of nodes of the first block of adders of transfers is connected to the first input of one transfer of the corresponding nodes of the block of transfers of work, the second input of one transfer and the input of two transfers of nodes of the block of transfers of work are connected with the same outputs of the corresponding nodes of the notebooks of the block of partial works in the code "1 of 4" , the outputs in the code “1 of 4” from the first to the (n-1) th nodes of the first block of carry-over adders are connected to the corresponding inputs of the four-digit bits in the code “1 of 4” of the first term, respectively, with the first o by the (n-1) th adders of the adder block, the outputs in the code “1 of 4” of the nth node of the first block of carry-over adders are connected to the information inputs of the 2nth tetrad of four-digit bits of the result register in the code “1 of 4”, when In this case, the sum transfer trigger block and the second carry adder block each contain (n-1) nodes, the inputs of the first group in the code “1 of 4” from the first to (n-1) th nodes of the second carry adder block being connected to the information outputs, respectively from the first to (n-1) -th adders in the code "1 of 4" block adders, the inputs of the second group in the code "1 from 2 "from the first to the (n-1) th nodes of the second block of carry-over adders are connected to the corresponding outputs, respectively, from the first to (n-1) -th nodes of the block of carry-over triggers of the sum, the transfer output from the first to (n-1) is nth nodes of the second block of transfer adders is connected to the first transfer input of the corresponding nodes of the block of transfer triggers, the second transfer input of which is connected to the outputs of transfers from the first to (n-1) -th adders in the code "1 of 4" of the adder block, transfer block The result contains (n-1) nodes, with informational inputs of the first group in the code "1 of 4" from the first through (n-1) -th nodes of which are connected to the information outputs of the quadruple digits from the (n + 2) -th through the 2n-th notebooks of the result register in the code "1 of 4" , the first transfers inputs from the first to the (n-1) -th nodes of the result transfer block are connected to the direct output of a unit in the code "1 of 2", respectively, from the first to the (n-1) -th nodes of the transfer transfer triggers block, the second transfers inputs from the second to the (n-1) th nodes of the result transfer block are connected to the outputs of the transfers, respectively, from the first to the (n-2) th nodes of the result transfer block, the second shift input of the first node of the transfer block is connected to a zero constant, the inputs from the (n + 2) -th through the 2nth nodes of the code control block "1 of 4" are connected to the outputs of the quadruple bits, respectively, from the first to (n-1) -th nodes of the result transfer block in the code “1 of 4”, the input of the device clock pulses is also connected to the clock inputs of the nodes of the product transfer block and the block of sum transfer triggers, the input of the device record is also connected to the input of the second register register, with the installation inputs of the nodes of the work transfer block and block trigger s transfer amount, a shift device is connected to the input of the input shift from the first to (n-1) -th transfer unit assemblies result.

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