RU2449469C1 - Functionally complete tolerant element - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: functionally complete tolerant element has first, second, third and fourth n-conductivity type transistors, fifth, sixth, seventh and eighth p-conductivity type transistors, a first, a second, a third and a fourth input bus, power bus, neutral bus and output bus.

EFFECT: high reliability of the element in case of failure of external inputs and transistors by maintaining functional completeness of the executed function.

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Description

The invention relates to computer technology and can be used to implement digital circuits having increased reliability requirements, in particular in the aviation and space industries.

A well-known logical element on KMDP transistors containing the first, second and third information transistors of n-type connected in series, fourth, fifth and sixth information transistors of n-type connected in series, four input buses, bus direct and inverse control signal. The first, second and third information transistors are connected between the output and common buses; the fourth, fifth and sixth information transistors are connected between the output and common buses; the first, second and third p-type load transistors are connected in series between the power supply bus and the output bus, fourth, fifth and a sixth p-type load transistor is connected in series between the power supply bus and the output bus, the drain of the first p-type blocking transistor is connected to the power supply bus, and the source is connected to the drain of the third p-type load transistor, the drain of the first p-type switching transistor is connected to the drain of the second p-type load transistor, and the source is connected to the drain of the sixth p-type load transistor, the drain of the second p-type switching transistor is connected to the drain of the fifth load transistor p-type, and the source is connected to the output bus, the drain of the second n-type blocking transistor is connected to the common bus, and the source is connected to the drain of the first n-type information transistor, the drain of the third switching transistor nt pa is connected to the drain of the second n-type information transistor, and the source is connected to the drain of the fourth n-type information transistor, the drain of the fourth n-type switching transistor is connected to the drain of the fifth p-type load transistor, and the source is connected to the output bus, the drain of the second blocking the n-type transistor is connected to a common bus, and the source is connected to the drain of the first n-type information transistor, the drain of the third n-type switching transistor is connected to the drain of the second n-type information transistor, and the source is to the fourth quarter of the n-type information transistor, the drain of the fourth n-type switching transistor is connected to the drain of the fifth n-type information transistor, and the source is connected to the output bus, the gates of the first p-type load transistor and the third n-type information transistor are connected to the first input bus , the gates of the second p-type load transistor and the second n-type information transistor are connected to the second input bus, the gates of the fifth p-type load transistor and the fifth n-type information transistor are connected to the third input bus, the gates of the sixth p-type load transistor and the fourth n-type information transistor are connected to the fourth input bus, the gates of the first and sixth n-type information transistors and the third and fourth p-type load transistors are connected to the direct control bus, the gates switching and blocking transistors are connected to the bus of the inverse control signal (ed. St. USSR No. 1064470, cl. H03K 19/094, publ. 12/30/83).

A disadvantage of the known element is the large number of transistors and, as a result, low structural reliability. In addition, in case of failures, the element does not preserve its functional completeness from the point of view of the Post theorem (see S. Marchenkov, Closed classes of Boolean functions. - M.: Fizmatlit, 2000, p. 18).

(см. Букреев И.Н., Горячев В.И., Мансуров Б.М. Микроэлектронные схемы цифровых устройств. - 4-е изд., перераб. и доп. М.: Техносфера, 2009. - 712 с, ил. 2.25). Данное устройство принято за прототип.The closest device of the same purpose to the claimed invention by the totality of features is a logic element on KMDP transistors containing four transistors with n-type conductivity, four transistors with p-type conductivity, four input buses, one output bus and one power bus and a zero bus, the drain of the first transistor is connected to the first input bus, the second input bus is connected to the gates of the first and second transistors, the drain of the third transistor is connected to the third input bus, to the gates of the third and fourth the fourth input bus is connected, the drain of the fifth transistor is connected to the power bus, the source of the first transistor, the drain of the second transistor and the gates of the sixth and seventh transistors are connected to each other, the sources of the second, seventh, eighth and fourth transistors are connected to the zero bus, the source of the fifth transistor is connected to the drain of the sixth transistor, the source of the third transistor, the drain of the fourth transistor and the gates of the fifth and eighth transistors are interconnected, the source of the sixth transistor is connected to the drains of the seventh eighth transistors and the output bus. This circuit is built on the basis of a two-input element OR-NOT, through the use of additional gate and blocking CMD transistors and implements a logical function

(see Bukreev I.N., Goryachev V.I., Mansurov B.M. Microelectronic circuits of digital devices. - 4th ed., revised and enlarged M .: Tekhnosfera, 2009. - 712 p., ill. 2.25). This device is taken as a prototype.

Signs of the prototype, coinciding with the essential features of the claimed invention - four transistors with n-type conductivity; four transistors with p-type conductivity; four input buses; one output bus; power bus and zero bus.

A disadvantage of the known device adopted for the prototype is the low probability of maintaining the basis in case of transistor failures. This fact creates difficulties when using the element for the implementation of combinational devices in non-repairable equipment.

The objective of the invention is to increase the reliability of the element in case of failures of the external inputs and transistors by maintaining the functional completeness of the implemented function.

The problem was solved due to the fact that in the known device containing the first, second, third, fourth transistors with n-type conductivity, fifth, sixth, seventh, eighth transistors with p-type conductivity, four input buses, one output bus, bus power supply and zero bus, the gates of the first and fifth transistors are connected to the first input bus, the gates of the second and seventh transistors are connected to the third input bus, the gates of the third and sixth transistors are connected to the second input bus, the gates of the fourth and sixth transistor ora are connected to the fourth input bus, the sources of the first and third transistors with n-type conductivity are connected to the power bus, the sources of the sixth and eighth transistors with p-type conductivity are connected to the zero bus, the drain of the first transistor with n-type conductivity is connected to the source of the second transistor , the drain of the third transistor with n-type conductivity is connected to the source of the fourth transistor, while the drains of the first and third transistors with n-type conductivity and the sources of the second and fourth transistors with n-type conductivity are connected between themselves, the drains of the second and fourth transistors with n-type conductivity and the drains of the fifth and seventh transistors are connected to the output bus, the source of the fifth transistor with p-type conductivity is connected to the drain of the sixth transistor with p-type conductivity, the source of the seventh transistor with p-conductivity type connected to the drain of the eighth transistor with p-type conductivity.

Signs of the proposed technical solution, distinctive from the prototype, - the gates of the first and fifth transistors are connected to the first input bus; the gates of the second and seventh transistors are connected to the third input bus; the gates of the third and sixth transistors are connected to the second input bus; the gates of the fourth and sixth transistors are connected to the fourth input bus; the sources of the first and third transistors with n-type conductivity are connected to the power bus; the sources of the sixth and eighth p-type transistors are connected to the zero bus; the drain of the first transistor with n-type conductivity is connected to the source of the second transistor; the drain of the third transistor with n-type conductivity is connected to the source of the fourth transistor; the drains of the first and third transistors with n-type conductivity and the sources of the second and fourth transistors with n-type conductivity are interconnected; the drains of the second and fourth transistors with n-type conductivity and the drains of the fifth and seventh transistors are connected to the output bus; the source of the fifth transistor with p-type conductivity is connected to the drain of the sixth transistor with p-type conductivity; the source of the seventh p-type transistor is connected to the drain of the eighth p-type transistor.

Distinctive features in combination with the known ones allow to increase the reliability of an element in case of failures of external inputs and transistors by maintaining the functional completeness of the function being implemented.

The basic function in accordance with the Post theorem allows one to realize by superposition any function of any number of variables.

With a discrete design, as KMDP transistors with n-type conductivity can be used KP301, IRF7304, and as KMDP transistors with p-type conductivity KP302, IRF7311 or any others.

The element can be implemented in integrated form and used as a universal basis for programmable logic integrated circuits (FPGAs), since existing basic elements with failures in the switching matrix and with transistor failures do not have the ability to maintain the basis.

Figure 1 shows a circuit diagram of the inventive logic element.

Figure 2 shows the timing diagram of the operation of the claimed element.

The device includes four KMDP transistors of the conductivity n-type 1-4 and four KMDP transistors of the conductivity p-type 5-8 (figure 1). The sources of transistors 1, 3 with n-type conductivity are connected to the power bus 9, the sources of transistors 6, 8 with p-type conductivity are connected to zero bus 10. The gates of transistors 1, 5 are connected to the first input bus 11, the gates of transistors 2, 7 are connected to the third input bus 12, the gates of transistors 3, 6 are connected to the second input bus 13, the gates of transistors 4, 8 are connected to the fourth input bus 14. The drain of transistor 1 with n-type conductivity is connected to the source of transistor 2, the drain of transistor 3 with conductivity n -type connected to the source of transistor 4. One hundred and transistors 1, 3 to n-type conductivity connected to the sources of the transistors 2, 4 with the n-conductivity type and are interconnected. The drains of transistors 2, 4 with n-type conductivity and the drains of transistors 5, 7 with p-type conductivity are connected to the output bus 15. The source of transistor 5 with p-type conductivity is connected to the drain of transistor 6 with p-type conductivity, the source of the transistor is 7 s p-type conductivity is connected to the drain of transistor 8 with p-type conductivity.

The device operates as follows.

Подключение источника питания на выход Z происходит при равенстве логической единице выражения

в случае неравенства логической единице этих конъюнкций нижняя последовательно-параллельная цепь транзисторов 5-8 с проводимостью p-типа обеспечивает подключение нулевой шины 10 на выход Z в соответствии с выражением

.Two parallel chains of transistors 1, 3 and 2, 4 with n-type conductivity, connected in series, realize by conjunction of two disjunctions the expression

The power supply is connected to output Z when the logical unit of expression is

in case of inequality of the logical unit of these conjunctions, the lower series-parallel circuit of transistors 5-8 with p-type conductivity provides the connection of the zero bus 10 to the output Z in accordance with the expression

.

In Fig.2, the timing diagram displays the state change of the output bus 15 depending on the state of the input signals 11, 12, 13, 14.

In the time interval from 0 to t _0, all input buses 11, 12, 13, 14 are at a low logic level, this leads to the closure of transistors 5-8 with p-type conductivity and the opening of transistors 1-4 with n-type conductivity. Through two consecutive chains of open transistors, the output bus 15 is connected to the power bus 9, therefore, the output of the element has a high logic level.

In the time interval from t ₀ to t _{1, the} value of the first input bus 11 changes to a high logic level. In this case, transistors 6-8 with p-type conductivity will still be closed, and transistor 5 with p-type conductivity will be open. Also, changing the voltage value on the first input bus 11 will close the transistor 1 with n-type conductivity, while the rest of the transistors with n-type conductivity 2-4 will be in the open state. Through a series of open transistors with n-type conductivity 3, 4, the output bus 15 is connected to the power bus 9. The output is still at a high logic level.

In the time interval from t ₁ to t _{2, the} value of the first input bus 11 is switched to zero, and the second input line 13 is switched to one. In this time interval, transistors 1, 2, 4 with n-type conductivity and transistor 6 with p-type conductivity are open, and transistors 3, 5, 7, 8 are in a closed state. Through a serial chain of open transistors 1, 2, the output bus 15 is connected to the power bus 9. At the output, a high logic level is maintained.

In the time interval from t ₃ to t ₄ on the first and second input lines 11, 13 a high logic level is set, on the other pair of inputs a low level. With this set of input signals, transistors 2, 4 with n-type conductivity and transistors 5, 6 with p-type conductivity are open, and transistors 1, 3, 7, 8 are in the closed state. Through a series of open transistors 5, 6, the output bus 15 is connected to the zero bus 10. The output switches to a low logic level.

In the time interval from t ₃ to t ₄ on the third input bus 12 is a high logic level, and on the other input lines 11, 13, 14 low. In this case, the transistors 1, 3, 4, 5 are in the open state, and the transistors 2, 6-8 are in the closed state. Through a serial chain of open transistors 3, 4, the output bus 15 is connected to the power bus 9. At the output, a high logic level.

In the time interval from t ₄ to t _5, the first 11 and third 12 input buses have a high logic level, and the remaining logic lines 13, 14 have a low logic level. Then the transistors 3, 4, 5, 7 are in the open state, and the transistors 1, 2, 6, 8 are in the closed state. In this case, through the open transistors 3, 4, the output bus 15 is connected to the power bus 9, so the value of the output signal remains at a high logical level.

In the time interval from t ₅ to t ₆ on the second 13 and third 12 input buses, a high logic level, while on the remaining input lines 11, 14 a low logic level. This leads to the opening of transistors 1, 4, 6, 7 and the closing of transistors 2, 3, 5, 8. Through a series of open transistors 1, 4, the output bus 15 is connected to the power bus 9, so the value of the output signal remains equal to unity.

In the time interval from t ₆ to t ₇ on the first three input lines 11, 13, 12 a high logic level is set, and at the input 14 a low logic level. In this case, the transistors 4, 5, 6, 7 are in the open state, and the transistors 1, 2, 3, 8 are closed. Then, through a pair of open transistors 5, 6, the output 15 is connected to the zero bus 10. It follows that the output bus 15 will switch to a low logic level.

In the time interval from t ₇ to t ₈ on the first three input lines 11, 13, 12, a low logic level is set, and at the input 14 a high logic level. In this case, the transistors 1, 2, 3, 8 are in the open state, and the transistors 4, 5, 6, 7 are closed. Therefore, through two pairs of consecutive chains of open transistors 1, 2 and 2, 3, the output 15 is connected to the power bus 9 and the output will establish a high logic level.

In the time interval from t ₈ to t ₉ at the first 11 and fourth 14 input units, and the remaining 12, 13 zeros. Then the transistors 2, 3, 5, 8 are in the open state, and the transistors 1, 4, 6, 7 are closed. Through a serial chain of open transistors 2, 3, the output bus 15 is connected to the power bus 9 and the output will be a high logic level.

In the time interval from t ₉ to t ₁₀ at the second 13 and fourth 14 input units, and on the remaining input lines 11, 12 zeros. Therefore, the transistors 1, 2, 6, 8 are in the open state, and the transistors 3, 4, 5, 7 are closed. Through open transistors 1, 2, the output bus 15 is connected to the power bus 9 and the output remains a high logic level.

In the time interval from t ₁₀ to t ₁₁ on the first 11, second 13 and fourth 14 input buses, a high logic level, and the third input 12 low logic level. Then the transistors 2, 5, 6, 8 are in the open state, and the transistors 1, 3, 4, 7 are closed. Through an open chain of transistors 5, 6, the output bus 15 is connected to the zero bus 10 and the output is set to a low logic level.

In the time interval from t ₁₁ to t ₁₂ on the first pair of input lines 11, 13 is a low logic level, and on the second pair of input lines 12, 14 a high logic level. This set of input signals will lead to the opening of transistors 1, 3, 7, 8 and the closing of transistors 2, 4, 5, 6. Through two open transistors 7, 8, the output bus 15 will be connected to the zero bus 10 and the output will remain low logic level.

In the time interval from t ₁₂ to t ₁₃ at the first 11, third 12 and fourth 14 input lines, a high logic level, and at the second input 13 a low logic level. In this case, the transistors 3, 5, 7, 8 will be open, and the transistors 1, 2, 4, 6 are closed. Through an open chain of transistors 7, 8, the output bus 15 is connected to the zero bus 10 and the output will remain zero.

In the time interval from t ₁₃ to t _14, the first input bus 11 will have a low logic level, and the second 13, third 12 and fourth 14 input buses will have a high logic level. Then transistors 1, 6-8 will be open, and transistors 2-5 will be closed. Through an open chain of transistors 7, 8, the output bus 15 remains connected to the zero bus 10 and the output still has a low logic level.

In the time interval from t ₁₄ to t ₁₅ on all input buses 11, 13, 12, 14 there will be a high logic level. Therefore, transistors 5-8 with p-type conductivity will be open, and transistors 1-4 with n-type conductivity will be closed. Through the open transistors 5, 6 and 7, 8, the output bus 15 is connected to the zero bus 10 and the output low logic level.

We show that the inventive device ensures the preservation of the basis of a single constant failure. For this, we calculate the probability of maintaining the basis of the FPT with a single constant transistor failure. There are two possible cases of constant failure for the MOSFET transistors: a unit constant, which is equivalent to a drain-source breakdown or a constant-on gate, and a zero constant, which is equivalent to a drain-source connection breakdown or a gate break. Thus, 16 cases of failure are possible. The full group of events includes the following implementations:

1. A breakdown of the drain-source circuit (or a constant-on gate) of the first transistor.

2. Open circuit source-source (or open gate) of the first transistor.

3. A breakdown of the drain-source circuit (or the constantly-on gate) of the second transistor.

4. Open circuit source-source (or open gate) of the second transistor.

5. A breakdown of the drain-source circuit (or a constant-on gate) of the third transistor.

6. Open circuit source-source (or open gate) of the third transistor.

7. A breakdown of the drain-source circuit (or the constantly-on gate) of the fourth transistor.

8. Open circuit source-source (or open gate) of the fourth transistor.

9. A breakdown of the drain-source circuit (or a constant-on gate) of the fifth transistor.

10. Open circuit source-source (or open gate) of the fifth transistor.

11. The breakdown of the drain-source circuit (or the constantly-on gate) of the sixth transistor.

12. Open circuit source-source (or open gate) of the sixth transistor.

13. Open circuit source-source (or open gate) of the seventh transistor.

14. A breakdown of the drain-source circuit (or the constant-on gate) of the seventh transistor.

15. Open circuit source-source (or open gate) of the eighth transistor.

16. Breakdown of the drain-source circuit (or the constantly-on gate) of the eighth transistor.

Let us calculate the conservation of the basis for the FPT in figure 1.

, так и функцию подключения к шине ноль вольт

.And in this case it is necessary to consider as a function of connecting to the power bus

, and the function of connecting to the bus zero volts

.

.1. A breakdown of the drain-source circuit (or a constant-on gate) of the first transistor. In this case, the source of the second transistor is connected to the power bus, and the basis will look like

.

не изменяется, для обеспечения ортогональности необходима

. Для этого в подаваемых наборах Х₁=0 и Х₂=0.This is a basic function in the sense of the Post theorem. Thus, since

does not change, to ensure orthogonality is necessary

. For this, in the supplied sets X ₁ = 0 and X ₂ = 0.

2. Open circuit source-source (or open gate) of the first transistor.

. Однако, поскольку

не изменяется, для обеспечения ортогональности (взаимной инверсности) с

, необходима

. Для этого в подаваемых наборах X₁=1.We obtain the basis function from the point of view of the Post theorem

. However, since

does not change, to ensure orthogonality (mutual inversion) with

is necessary

. For this, in the supplied sets X ₁ = 1.

. Тогда

.3. A breakdown of the drain-source circuit (or the constantly-on gate) of the second transistor. Similarly, we obtain the basis function from the point of view of the Post theorem

. Then

.

и

. Это базисная функция в смысле теоремы Поста.4. Open circuit source-source (or open gate) of the second transistor. In this case, we get

and

. This is a basic function in the sense of the Post theorem.

и

. Это базисная функция в смысле теоремы Поста.5. A breakdown of the drain-source circuit (or a constant-on gate) of the third transistor. Similarly, we obtain

and

. This is a basic function in the sense of the Post theorem.

, а

. Это базисная функция в смысле теоремы Поста.6. Open circuit source-source (or open gate) of the third transistor. We get the basic function

, but

. This is a basic function in the sense of the Post theorem.

и

. Это базисная функция в смысле теоремы Поста.7. A breakdown of the drain-source circuit (or the constantly-on gate) of the fourth transistor. Similarly, we obtain

and

. This is a basic function in the sense of the Post theorem.

, в то время как

. Это базисная функция в смысле теоремы Поста.8. Open circuit source-source (or open gate) of the fourth transistor. We get the basic function

, while

. This is a basic function in the sense of the Post theorem.

, значит надо использовать базис

. Это базисная функция в смысле теоремы Поста.9. A breakdown of the drain-source circuit (or a constant-on gate) of the fifth transistor. For the fifth and subsequent transistors, failures will affect the function of connecting to the zero volt bus. Therefore, we obtain

, so you need to use the basis

. This is a basic function in the sense of the Post theorem.

. Значит надо использовать базис

. Это базисная функция в смысле теоремы Поста.10. Open circuit source-source (or open gate) of the fifth transistor. We get

. So you need to use the basis

. This is a basic function in the sense of the Post theorem.

, значит, базис

. Это базисная функция в смысле теоремы Поста.11. The breakdown of the drain-source circuit (or the constantly-on gate) of the sixth transistor. We get

means the basis

. This is a basic function in the sense of the Post theorem.

. Базис

. Это базисная функция в смысле теоремы Поста.12. Open circuit source-source (or open gate) of the sixth transistor. We get

. Basis

. This is a basic function in the sense of the Post theorem.

. Базис

. Это базисная функция в смысле теоремы Поста.13. Open circuit source-source (or open gate) of the seventh transistor. We get

. Basis

. This is a basic function in the sense of the Post theorem.

, значит, базис

. Это базисная функция в смысле теоремы Поста.14. A breakdown of the drain-source circuit (or the constant-on gate) of the seventh transistor. We get

means the basis

. This is a basic function in the sense of the Post theorem.

. Базис

. Это базисная функция в смысле теоремы Поста.15. Open circuit source-source (or open gate) of the eighth transistor. We get

. Basis

. This is a basic function in the sense of the Post theorem.

, значит, базис

.16. Breakdown of the drain-source circuit (or the constantly-on gate) of the eighth transistor. We get

means the basis

.

This is a basic function in the sense of the Post theorem.

We get that out of sixteen cases of single constant failures in transistors, the basis has never been lost, so the probability of maintaining the basis is equal to

Now we will calculate the probability of maintaining the basis for a functionally complete tolerant element in the case of external single-time constant input and output failures. For each input bus 11, 13, 12, 14 and for the output bus 15, there may be cases of short circuit to the power bus 9 and to the zero volt bus 10. Thus, a total of 10 cases of failures are possible. The full group of events includes the following implementations:

1. The closure of the first input 11 to the bus zero volt 10.

2. The closure of the first input 11 to the power bus 9.

3. The closure of the second input 13 to the bus zero volt 10.

4. The closure of the second input 13 to the power bus 9.

5. The closure of the third input 12 to the bus zero volt 10.

6. The closure of the third input 12 to the power bus 9.

7. The closure of the fourth input 14 to the bus zero volt 10.

8. The closure of the fourth input 14 to the power bus 9.

9. The closure of the output bus 15 to the bus zero volt 10.

10. The closure of the output bus 15 to the power bus 9.

. Рассмотрим подробней каждую реализацию:As you know, FPT implements a logical function

. Let's consider in more detail each implementation:

.1. The closure of the first input 11 on the bus zero volts 10. In this case, you need to put zero in the expression for the logical function, then the expression will be the basis

.

.2. The closure of the first input 11 on the power bus 9. In this case, you need to put one in the expression for the logical function, then the expression will be the basis

.

.3. The closure of the second input 13 to the bus zero volts 10. Basis

.

.4. The closure of the second input 13 to the power bus 9. Basis

.

.5. The closure of the third input 12 to the bus zero volts 10. Basis

.

.6. The closure of the third input 12 to the power bus 9. Basis

.

.7. The closure of the fourth input 14 to the bus zero volts 10. Basis

.

.8. The closure of the fourth input 14 to the power bus 9. Basis

.

.9. The output 15 is shorted to a zero volt bus 10. In this case, the output will always have a low logic level. An element cannot implement any basis. The basis is lost

.

.10. The closure of output 15 on the power bus 9. In this case, the output will always have a high logic level. The basis is lost

.

Thus, out of ten cases of external one-time constant failures, the basis was lost in two of them; therefore, the probability of maintaining the basis is equal to

In the case of external one-time constant output failures, the basis is lost, but in the case of one-time constant input failures, the basis is preserved.

. Это базисная функция при X₄=0, X₂=0 - НЕ-ИЛИ:

.Now we will consider the functioning of the prototype in the case of external one-time constant failures of inputs and outputs. Ten failures are also possible for him. The prototype implements a logical function

. This is the basis function for X ₄ = 0, X ₂ = 0 - NON-OR:

.

Let us consider in more detail each implementation in case of failure:

. Это не базисная функция.1. Shorting the first input to the bus zero volts. In this case, you need to put zero in the expression for the logical function, then

. This is not a basic function.

. Это не базисная функция.2. Shorting the first input to the power bus. In this case, you need to put one in the expression for the logical function, then the prototype will implement the function

. This is not a basic function.

Это базисная функция при Х₄=0.3. Shorting the second input to the bus zero volts. Function

This is the basis function for X ₄ = 0.

Это не базисная функция.4. Shorting the second input to the power bus. Function

This is not a basic function.

. Это не базисная функция.5. Shorting the third input to the bus zero volts. Function

. This is not a basic function.

. Это не базисная функция.6. Shorting the third input to the power bus. Function

. This is not a basic function.

Это базисная функция при Х₂=0.7. Shorting the fourth input to the bus zero volts. Function

This is the basis function for X ₂ = 0.

. Это не базисная функция.8. Shorting the fourth input to the power bus. Function

. This is not a basic function.

.9. Short circuit output to the bus zero volts. In this case, the output will always be a low logic level. The prototype will not be able to implement any logical function.

.

.10. Short circuit of the output to the power bus. In this case, the output will always be a high logic level. The output will be

.

Thus, the prototype retains the basis only in the case of external one-time constant input failures. Out of ten cases of external one-time constant failures, the prototype realized a function, basic from the point of view of the Post theorem, in two cases. Therefore, the probability of preserving the basis is

In the case of single constant failures in transistors, the probability of maintaining the basis of the prototype is zero.

Thus, the claimed element maintains a basis in the sense of the Post theorem for external single-time constant input and output failures with a probability of 80% and with a probability of 100% for internal single-time constant transistor failures. While the prototype basis is preserved with external single-time constant failures of 20%, with transistor failures it is not preserved in any case.

In addition, the FPT element is resistant to bridging faults. As you know, this type of failure is represented by three failure models: a wired AND / OR type faults model (Wired - AND / OR), a Dominant fault model, a dominant AND / OR type fault circuit model (Dominant - AND / OR).

вариантов. Каждый такой вариант характеризуется «превалированием» одной из двух переменных. Тогда полная группа событий включает 12 реализаций:Consider the dominant model with the closures of two inputs. In this case we get

options. Each such option is characterized by the "prevalence" of one of two variables. Then the full group of events includes 12 implementations:

и

первый вариант - превалирует

;1. Closure

and

first option prevails

;

и

второй вариант - превалирует

;2. Closure

and

the second option prevails

;

и

первый вариант - превалирует

;3. Closure

and

first option prevails

;

и

второй вариант - превалирует

;4. Short circuit

and

the second option prevails

;

и

первый вариант - превалирует

;5. Closure

and

first option prevails

;

и

первый вариант - превалирует

;6. Closure

and

first option prevails

;

и

второй вариант - превалирует

;7. Closure

and

the second option prevails

;

и

второй вариант - превалирует

;8. Closure

and

the second option prevails

;

и

второй вариант - превалирует

;9. Closure

and

the second option prevails

;

и

первый вариант - превалирует

;10. Closure

and

first option prevails

;

и

второй вариант - превалирует

;11. Closure

and

the second option prevails

;

и

первый вариант - превалирует

.12. Closure

and

first option prevails

.

:Let us consider in more detail each implementation in case of failures in the function

:

и

первый вариант - превалирует

. Базис

;1. Closure

and

first option prevails

. Basis

;

и

второй вариант - превалирует

. Базис

;1. Closure

and

the second option prevails

. Basis

;

и

первый вариант - превалирует

. Базис

;3. Closure

and

first option prevails

. Basis

;

и

второй вариант - превалирует

. Базис

;4. Short circuit

and

the second option prevails

. Basis

;

и

первый вариант - превалирует

. Базис

5. Closure

and

first option prevails

. Basis

и

первый вариант - превалирует

. Базис

;6. Closure

and

first option prevails

. Basis

;

и

второй вариант - превалирует

. Базис

;7. Closure

and

the second option prevails

. Basis

;

и

второй вариант - превалирует

. Базис

;8. Closure

and

the second option prevails

. Basis

;

и

второй вариант - превалирует

. Базис

;9. Closure

and

the second option prevails

. Basis

;

и

первый вариант - превалирует

. Базис

;10. Closure

and

first option prevails

. Basis

;

и

второй вариант - превалирует

. Базис

;11. Closure

and

the second option prevails

. Basis

;

и

первый вариант - превалирует

. Базис

.12. Closure

and

first option prevails

. Basis

.

вариантов. Каждый вариант характеризуется «превалированием» одной из трех переменных. Тогда полная группа событий включает 12 реализаций:Consider the dominant failure model when three inputs are closed. In this case we get

options. Each option is characterized by the "prevalence" of one of three variables. Then the full group of events includes 12 implementations:

,

,

первый вариант - превалирует

;1. Closure

,

,

first option prevails

;

,

,

первый вариант - превалирует

;2. Closure

,

,

first option prevails

;

,

,

первый вариант - превалирует

;3. Closure

,

,

first option prevails

;

,

,

первый вариант - превалирует

;4. Short circuit

,

,

first option prevails

;

,

,

первый вариант - превалирует

;5. Closure

,

,

first option prevails

;

,

,

первый вариант - превалирует

;6. Closure

,

,

first option prevails

;

,

,

первый вариант - превалирует

;7. Closure

,

,

first option prevails

;

,

,

первый вариант - превалирует

;8. Closure

,

,

first option prevails

;

,

,

первый вариант - превалирует

;9. Closure

,

,

first option prevails

;

,

,

первый вариант - превалирует

;10. Closure

,

,

first option prevails

;

,

,

первый вариант - превалирует

;11. Closure

,

,

first option prevails

;

,

,

первый вариант - превалирует

.12. Closure

,

,

first option prevails

.

:Let us consider in more detail each implementation in case of failures in the function

:

,

,

первый вариант - превалирует

. Базис

;1. Closure

,

,

first option prevails

. Basis

;

,

,

второй вариант - превалирует

. Базис

;2. Closure

,

,

second option - prevails

. Basis

;

,

,

третья вариант - превалирует

. Базис

;3. Closure

,

,

third option - prevails

. Basis

;

,

,

первый вариант - превалирует

. Базис

;4. Short circuit

,

,

first option prevails

. Basis

;

,

,

второй вариант - превалирует

. Базис

;5. Closure

,

,

second option - prevails

. Basis

;

,

,

третий вариант - превалирует

. Базис

;6. Closure

,

,

third option - prevails

. Basis

;

,

,

первый вариант - превалирует

. Базис

;7. Closure

,

,

first option prevails

. Basis

;

,

,

второй вариант - превалирует

. Базис

;8. Closure

,

,

the second option prevails

. Basis

;

,

,

третий вариант - превалирует

. Базис

;9. Closure

,

,

third option - prevails

. Basis

;

,

,

первый вариант - превалирует

. Базис ;10. Closure

,

,

first option prevails

. Basis ;

,

,

второй вариант - превалирует

. Базис

;11. Closure

,

,

the second option prevails

. Basis

;

,

,

третий вариант - превалирует

. Базис

.12. Closure

,

,

third option prevails

. Basis

.

вариантов. Для каждого варианта возможны отказы типа И и ИЛИ. Тогда полная группа событий включает 12 реализаций:Consider a wired AND / OR type failure model when two inputs are shorted. In this case we get

options. For each option, failures of the type AND and OR are possible. Then the full group of events includes 12 implementations:

и

проводное И;1. Closure

and

wired AND;

и

проводное И;2. Closure

and

wired AND;

и

проводное И;3. Closure

and

wired AND;

и

проводное И;4. Short circuit

and

wired AND;

и

проводное И;5. Closure

and

wired AND;

и

проводное И;6. Closure

and

wired AND;

и

проводное ИЛИ;7. Closure

and

wired OR;

и

проводное ИЛИ;8. Closure

and

wired OR;

и

проводное ИЛИ;9. Closure

and

wired OR;

и

проводное ИЛИ;10. Closure

and

wired OR;

и

проводное ИЛИ;11. Closure

and

wired OR;

и

проводное ИЛИ.12. Closure

and

wired OR.

:Let us consider in more detail each implementation in case of failures in the function

:

и

проводное И. Базис

;1. Closure

and

wired I. Bazis

;

и

проводное И. Базис

;2. Closure

and

wired I. Bazis

;

и

проводное И. Базис

;3. Closure

and

wired I. Bazis

;

и

проводное И. Базис

;4. Short circuit

and

wired I. Bazis

;

и

проводное И. Базис

;5. Closure

and

wired I. Bazis

;

и

проводное И. Базис

;6. Closure

and

wired I. Bazis

;

и

проводное ИЛИ. Базис

;7. Closure

and

wired OR. Basis

;

и

проводное ИЛИ. Базис

;8. Closure

and

wired OR. Basis

;

и

проводное ИЛИ. Базис

;9. Closure

and

wired OR. Basis

;

и

проводное ИЛИ. Базис

;10. Closure

and

wired OR. Basis

;

и

проводное ИЛИ. Базис

;11. Closure

and

wired OR. Basis

;

и

проводное ИЛИ. Базис

.12. Closure

and

wired OR. Basis

.

вариантов. Для каждого варианта возможны отказы типа И и ИЛИ. Тогда полная группа событий включает 8 реализаций:Consider a failure model such as a wired AND / OR when three inputs are shorted. In this case we get

options. For each option, failures of the type AND and OR are possible. Then the full group of events includes 8 implementations:

,

,

проводное И;1. Closure

,

,

wired AND;

,

,

проводное И;2. Closure

,

,

wired AND;

,

,

проводное И;3. Closure

,

,

wired AND;

,

,

проводное И;4. Short circuit

,

,

wired AND;

,

,

проводное ИЛИ;5. Closure

,

,

wired OR;

,

,

проводное ИЛИ;6. Closure

,

,

wired OR;

,

,

проводное ИЛИ;7. Closure

,

,

wired OR;

,

,

проводное ИЛИ.8. Closure

,

,

wired OR.

:Let us consider in more detail each implementation in case of failures in the function

:

,

,

проводное И. Базис

;1. Closure

,

,

wired I. Bazis

;

,

,

проводное И. Базис

;2. Closure

,

,

wired I. Bazis

;

,

,

проводное И. Базис

;3. Closure

,

,

wired I. Bazis

;

,

,

проводное И. Базис

;4. Short circuit

,

,

wired I. Bazis

;

,

,

проводное ИЛИ. Базис

;5. Closure

,

,

wired OR. Basis

;

,

,

проводное ИЛИ. Базис

;6. Closure

,

,

wired OR. Basis

;

,

,

проводное ИЛИ. Базис

;7. Closure

,

,

wired OR. Basis

;

,

,

проводное ИЛИ. Базис

.8. Closure

,

,

wired OR. Basis

.

вариантов. Для каждого варианта возможны отказы типа И и ИЛИ и превалирование одного из двух входов. Тогда полная группа событий включает 24 реализации:Consider a dominant AND / OR failure model with two inputs shorted. In this case we get

options. For each option, failures of the type AND and OR are possible and the prevalence of one of the two inputs. Then the full group of events includes 24 implementations:

и

доминантное И - превалирует

;1. Closure

and

dominant AND - prevails

;

и

доминантное И - превалирует

;2. Closure

and

dominant AND - prevails

;

и

доминантное И - превалирует

;3. Closure

and

dominant AND - prevails

;

и

доминантное И - превалирует

;4. Short circuit

and

dominant AND - prevails

;

и

доминантное И - превалирует

;5. Closure

and

dominant AND - prevails

;

и

доминантное И - превалирует

;6. Closure

and

dominant AND - prevails

;

и

доминантное И - превалирует

;7. Closure

and

dominant AND - prevails

;

и

доминантное И - превалирует

;8. Closure

and

dominant AND - prevails

;

и

доминантное И - превалирует

;9. Closure

and

dominant AND - prevails

;

и

доминантное И - превалирует

;10. Closure

and

dominant AND - prevails

;

и

доминантное И - превалирует

;11. Closure

and

dominant AND - prevails

;

и

доминантное И - превалирует

;12. Closure

and

dominant AND - prevails

;

и

доминантное ИЛИ - превалирует

;13. Closure

and

dominant OR - prevails

;

и

доминантное ИЛИ - превалирует

;14. Closure

and

dominant OR - prevails

;

и

доминантное ИЛИ - превалирует

;15. Closure

and

dominant OR - prevails

;

и

доминантное ИЛИ - превалирует

;16. The closure

and

dominant OR - prevails

;

и

доминантное ИЛИ - превалирует

;17. Closure

and

dominant OR - prevails

;

и

доминантное ИЛИ - превалирует

;18. Closure

and

dominant OR - prevails

;

и

доминантное ИЛИ - превалирует

;19. Closure

and

dominant OR - prevails

;

и

доминантное ИЛИ - превалирует

;20. Closing

and

dominant OR - prevails

;

и

доминантное ИЛИ - превалирует

;21. The closure

and

dominant OR - prevails

;

и

доминантное ИЛИ - превалирует

;22. Closure

and

dominant OR - prevails

;

и

доминантное ИЛИ - превалирует

;23. Closure

and

dominant OR - prevails

;

и

доминантное ИЛИ - превалирует

.24. Closure

and

dominant OR - prevails

.

.Let us consider in more detail each implementation in case of failures in the function

.

и

доминантное И - превалирует

. Базис

;1. Closure

and

dominant AND - prevails

. Basis

;

и

доминантное И - превалирует

. Базис

;2. Closure

and

dominant AND - prevails

. Basis

;

и

доминантное И - превалирует

. Базис

;3. Closure

and

dominant AND - prevails

. Basis

;

и

доминантное И - превалирует

. Базис

;4. Short circuit

and

dominant AND - prevails

. Basis

;

и

доминантное И - превалирует

. Базис

;5. Closure

and

dominant AND - prevails

. Basis

;

и

доминантное И - превалирует

. Базис

;6. Closure

and

dominant AND - prevails

. Basis

;

и

доминантное И - превалирует

. Базис

;7. Closure

and

dominant AND - prevails

. Basis

;

и

доминантное И - превалирует

. Базис

;8. Closure

and

dominant AND - prevails

. Basis

;

и

доминантное И - превалирует

. Базис

;9. Closure

and

dominant AND - prevails

. Basis

;

и

доминантное И - превалирует

. Базис

;10. Closure

and

dominant AND - prevails

. Basis

;

и

доминантное И - превалирует

. Базис

;11. Closure

and

dominant AND - prevails

. Basis

;

и

доминантное И - превалирует

. Базис

;12. Closure

and

dominant AND - prevails

. Basis

;

и

доминантное ИЛИ - превалирует

. Базис

;13. Closure

and

dominant OR - prevails

. Basis

;

и

доминантное ИЛИ - превалирует

. Базис

14. Closure

and

dominant OR - prevails

. Basis

и

доминантное ИЛИ - превалирует

. Базис

;15. Closure

and

dominant OR - prevails

. Basis

;

и

доминантное ИЛИ - превалирует

. Базис

;16. The closure

and

dominant OR - prevails

. Basis

;

и

доминантное ИЛИ - превалирует

. Базис

;17. Closure

and

dominant OR - prevails

. Basis

;

и

доминантное ИЛИ - превалирует

. Базис

;18. Closure

and

dominant OR - prevails

. Basis

;

и

доминантное ИЛИ - превалирует

. Базис

;19. Closure

and

dominant OR - prevails

. Basis

;

и

доминантное ИЛИ - превалирует

. Базис

;20. Closing

and

dominant OR - prevails

. Basis

;

и

доминантное ИЛИ - превалирует

. Базис

;21. The closure

and

dominant OR - prevails

. Basis

;

и

доминантное ИЛИ - превалирует

. Базис

;22. Closure

and

dominant OR - prevails

. Basis

;

и

доминантное ИЛИ - превалирует

. Базис

;23. Closure

and

dominant OR - prevails

. Basis

;

и

доминантное ИЛИ - превалирует

. Базис

.24. Closure

and

dominant OR - prevails

. Basis

.

вариантов. Для каждого варианта возможны отказы типа И и ИЛИ и превалирование одного из трех входов. Тогда полная группа событий включает 24 реализации:Consider a dominant AND / OR failure model when three inputs are shorted. In this case we get

options. For each option, failures of the type AND and OR are possible and the prevalence of one of the three inputs. Then the full group of events includes 24 implementations:

,

,

доминантное И - превалирует

;1. Closure

,

,

dominant AND - prevails

;

,

,

доминантное И - превалирует

;2. Closure

,

,

dominant AND - prevails

;

,

,

доминантное И - превалирует

;3. Closure

,

,

dominant AND - prevails

;

,

,

доминантное И - превалирует

;4. Short circuit

,

,

dominant AND - prevails

;

,

,

доминантное И - превалирует

;5. Closure

,

,

dominant AND - prevails

;

,

,

доминантное И - превалирует

;6. Closure

,

,

dominant AND - prevails

;

,

,

доминантное И - превалирует

;7. Closure

,

,

dominant AND - prevails

;

,

,

доминантное И - превалирует

;8. Closure

,

,

dominant AND - prevails

;

,

,

доминантное И - превалирует

;9. Closure

,

,

dominant AND - prevails

;

,

,

доминантное И - превалирует

;10. Closure

,

,

dominant AND - prevails

;

,

,

доминантное И - превалирует

;11. Closure

,

,

dominant AND - prevails

;

,

,

доминантное И - превалирует

;12. Closure

,

,

dominant AND - prevails

;

,

,

доминантное ИЛИ - превалирует

;13. Closure

,

,

dominant OR - prevails

;

,

,

доминантное ИЛИ - превалирует

;14. Closure

,

,

dominant OR - prevails

;

,

,

доминантное ИЛИ - превалирует

;15. Closure

,

,

dominant OR - prevails

;

,

,

доминантное ИЛИ - превалирует

;16. Closure

,

,

dominant OR - prevails

;

,

,

доминантное ИЛИ - превалирует

;17. Closure

,

,

dominant OR - prevails

;

,

,

доминантное ИЛИ - превалирует

;18. Closure

,

,

dominant OR - prevails

;

,

,

доминантное ИЛИ - превалирует

;19. Closure

,

,

dominant OR - prevails

;

,

,

доминантное ИЛИ - превалирует

;20. Closing

,

,

dominant OR - prevails

;

,

,

доминантное ИЛИ - превалирует

;21. The closure

,

,

dominant OR - prevails

;

,

,

доминантное ИЛИ - превалирует

;22. Closure

,

,

dominant OR - prevails

;

,

,

доминантное ИЛИ - превалирует

;23. Closure

,

,

dominant OR - prevails

;

,

,

доминантное ИЛИ - превалирует

.24. Closure

,

,

dominant OR - prevails

.

:Let us consider in more detail each implementation in case of failures in the function

:

,

,

доминантное И - превалирует

. Базис

;1. Closure

,

,

dominant AND - prevails

. Basis

;

,

,

доминантное И - превалирует

. Базис

;2. Closure

,

,

dominant AND - prevails

. Basis

;

,

,

доминантное И - превалирует

. Базис

;3. Closure

,

,

dominant AND - prevails

. Basis

;

,

,

доминантное И - превалирует

. Базис

;4. Short circuit

,

,

dominant AND - prevails

. Basis

;

,

,

доминантное И - превалирует

. Базис

;5. Closure

,

,

dominant AND - prevails

. Basis

;

,

,

доминантное И - превалирует

. Базис

;6. Closure

,

,

dominant AND - prevails

. Basis

;

,

,

доминантное И - превалирует

. Базис

;7. Closure

,

,

dominant AND - prevails

. Basis

;

,

,

доминантное И - превалирует

. Базис

;8. Closure

,

,

dominant AND - prevails

. Basis

;

,

,

доминантное И - превалирует

. Базис

;9. Closure

,

,

dominant AND - prevails

. Basis

;

,

,

доминантное И - превалирует

. Базис

;10. Closure

,

,

dominant AND - prevails

. Basis

;

,

,

доминантное И - превалирует

. Базис

;11. Closure

,

,

dominant AND - prevails

. Basis

;

,

,

доминантное И - превалирует

. Базис12. Closure

,

,

dominant AND - prevails

. Basis

;

;

,

,

доминантное ИЛИ - превалирует

. Базис

;13. Closure

,

,

dominant OR - prevails

. Basis

;

,

,

доминантное ИЛИ - превалирует

. Базис

;14. Closure

,

,

dominant OR - prevails

. Basis

;

,

,

доминантное ИЛИ - превалирует

. Базис

;15. Closure

,

,

dominant OR - prevails

. Basis

;

,

,

доминантное ИЛИ - превалирует

. Базис

;16. The closure

,

,

dominant OR - prevails

. Basis

;

,

,

доминантное ИЛИ - превалирует

. Базис

;17. Closure

,

,

dominant OR - prevails

. Basis

;

,

,

доминантное ИЛИ - превалирует

. Базис

;18. Closure

,

,

dominant OR - prevails

. Basis

;

,

,

доминантное ИЛИ - превалирует

. Базис

;19. Closure

,

,

dominant OR - prevails

. Basis

;

,

,

доминантное ИЛИ - превалирует

. Базис

;20. Closing

,

,

dominant OR - prevails

. Basis

;

,

,

доминантное ИЛИ - превалирует

. Базис

;21. The closure

,

,

dominant OR - prevails

. Basis

;

,

,

доминантное ИЛИ - превалирует

. Базис

;22. Closure

,

,

dominant OR - prevails

. Basis

;

,

,

доминантное ИЛИ - превалирует

. Базис

;23. Closure

,

,

dominant OR - prevails

. Basis

;

,

,

доминантное ИЛИ - превалирует

. Базис

.24. Closure

,

,

dominant OR - prevails

. Basis

.

Thus, the calculation shows that the functionally complete tolerant element maintains functional completeness not only for constant single failures, but also for failures such as closures, which describe a large number of failures observed in the FPGA. In turn, the prototype does not possess such properties. Therefore, the claimed element has a higher reliability.

Claims (1)

Functionally complete tolerant element containing the first, second, third, fourth transistors with n-type conductivity, fifth, sixth, seventh, eighth transistors with p-type conductivity, four input buses, one output power bus and a zero bus, characterized in that the gates of the first and fifth transistors are connected to the first input bus, the gates of the second and seventh transistors are connected to the third input bus, the gates of the third and sixth transistors are connected to the second input bus, the gates of the fourth and sixth transistors are connected are connected to the fourth input bus, the sources of the first and third transistors with n-type conductivity are connected to the power bus, the sources of the sixth and eighth transistors with p-type conductivity are connected to the zero bus, the drain of the first transistor with n-type conductivity is connected to the source of the second transistor, the drain of the third transistor with n-type conductivity is connected to the source of the fourth transistor, while the drains of the first and third transistors with n-type conductivity and the sources of the second and fourth transistors with n-type conductivity are connected between oh, the drains of the second and fourth transistors with n-type conductivity and the drains of the fifth and seventh transistors are connected to the output bus, the source of the fifth transistor with p-type conductivity is connected to the drain of the sixth transistor with p-type conductivity, the source of the seventh transistor with p-type conductivity connected to the drain of the eighth p-type transistor.

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