RU2331923C2 - Information processing device - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: this device contains the block for data input, data output block, ring bus, local pools of command packages each one consisting of command memory block, block of functional parameters memory, memory block of data readiness, memory block of readiness control, readiness scheme, decipher, block of accumulator memory, multiplier, summer, block of activation function and data package registry, blocks of stack data memory, priority chains, compare circuits, input clamping circuits, each of them is created by the address registers according the number of jack fields of data package and data registry.

EFFECT: increase of device efficiency due to implementation of data processing according to its place of storage in the multifunctional pools' memory of the command packages and time adjustment of the data input and converting processes.

2 cl, 2 dwg

Description

The invention relates to computer technology and can be used to build information processing systems in a neural network basis.

A device for processing information based on the regular structure of RAM, oriented to parallel computing and containing interconnected via a switch operating units, memory units, and data input / output blocks [Patterson D., Anderson T., Cadvel N., Fromm R., Keaton K., Kozyarakis K., Thomas R, Elik K. Arguments in favor of IRAM. - Computerra, No. 15, 1998, Appendix C.3-14].

Due to the limited number of processor units, this device does not allow to efficiently solve the tasks of a neural network basis with a high degree of parallelization of the computing process.

A device for processing information is known that contains command pools formed by blocks of command memory, data memory and a stack of data memory, operational blocks interconnected with command pools, as well as data input and output blocks connected to a parallel bus [VLSI Computers: 2- x kn. Prince 1: Trans. with japan. / Motooka T., Tomita S. et al. - M.: Mir, 1988, pp. 102-107].

The disadvantage of this device is software parallelization of calculations: with the help of the compiler, the ability to simultaneously execute a number of program fragments is determined and assigned to specific operating units. This approach does not allow to realize the potential for parallelizing the computing process.

The closest technical solution to the present invention, chosen by the authors for the prototype, is an information processing device containing pools of command packets, each of which is composed of blocks of local command memory, local memory of functional parameters, local data availability memory and is interconnected with the same block of stack memory the results and the ring bus to which the data input units, data output units are connected [Patent 2179739 RF, IPC G06F 15/00. Device for processing information. / G.F. Nesteruk, F.G. Nesteruk. - No.2000108883 / 09; claimed 10.04.2000; publ. 02/20/2002. Bull. No. 5. Priority from 10.04.2000].

The disadvantage of the prototype is the diversity of the processing and storage of information in time and in the structure of the device, which reduces the overall performance of the calculations due to the intensive exchange of data between memory and operating units.

The objective of the present invention is to increase the productivity of calculations by organizing the processing of information at the place of its storage in the pools of the command packages and combining in time the processes of recording and data conversion.

The task is achieved by the fact that in each of the pools of command packets of the device for processing information, a readiness control memory block, a readiness circuit, a decoder, a battery memory, a multiplier, an adder, an activation function block and a data packet register are introduced, and each of the data stack memory blocks interconnected with a priority circuit, comparison circuits, and an input latch formed by address registers by the number of communication fields of the data packet and the data register, and the input latch interconnections They are connected with the ring bus and the input bus of the corresponding data stack memory block, and the address registers are with the inputs of the corresponding comparison circuits and the first outputs of the priority circuit, the first inputs of each of which are connected to the outputs of the comparison circuits, and the second input and second output are connected to the output and the input of the same block of the stack data memory, the output bus address of each of the blocks of the stack data memory is interconnected with the address buses of the command memory blocks, battery memory, data ready memory, readiness control memory by the address register of the functional parameter memory block and the decoder, and the output bus of each of the blocks of the stacked data memory with data buses of the command memory blocks, functional parameter memory and the input bus of the multiplier, the second input and output buses of which are connected respectively to the output bus of the functional memory block parameters and the input bus adder, the second input bus of which is connected to the output bus of the battery unit, and the output bus to the input register of the battery unit and in one bus of the activation function block, the output buses of the activation function block and the command memory block are interconnected with the input bus of the data packet register, the output bus of which is connected to the ring bus, the output buses of the data readiness memory blocks, the availability control memory and the decoder are bitwise combined and interconnected with the input the register of the data readiness memory block and with the input bus of the corresponding readiness circuit, the output of each of which is connected to the first control input of the corresponding input istra block of memory data is ready, the input register of the storage memory unit, the memory unit address register and functional parameters register data packets and the second outputs of all the priority circuits are combined by the OR gate, interconnected with the second control inputs of all data packets registers.

In addition, in the inventive device for processing information, the priority circuit contains two-input logic elements NAND and sequentially connected two-input logic elements AND, the first inputs of two-input logic elements AND are connected to the corresponding first inputs of the priority circuit, the outputs of two-input logic elements AND with the corresponding first outputs of the priority circuit, inputs of the multi-input logic element AND and the first inputs of the same two-input logic elements AND, the second input take priority circuit coupled to the second input of the first two-input AND gate and a second NOR input of the first two-input AND gate, and the second inputs of the remaining two-input AND gates and two-input NOR gates and - to the outputs of the previous two-input AND gates I.

When implementing devices for processing information in accordance with the claimed invention, a technical result arises - an increase in the efficiency of calculations due to a decrease in the time of emulation of a computing process performed by a neural network. An additional important technical result is to increase the data security in the device for processing information due to the fact that:

- the data recording operation is performed not at the specific address of the memory blocks, but according to the content of the data packet fields;

- there is no operation of reading data from memory and, therefore, direct access to stored information;

- data ready for processing, presented in the form of data packets, is automatically extracted from the memory - without external control.

Figure 1 presents the structural diagram of the proposed device for processing information, and figure 2 is one of the possible options for building a priority chain.

The information processing device contains pools of command packets 1, each of which is composed of memory blocks of teams 2, memory of functional parameters 3, memory of data readiness 4 and is interconnected with the same block of stack data memory 5 and a ring bus 6 to which data input blocks 7 are connected , data output blocks 8. A readiness control memory 9, a readiness circuit 10 and a decoder 11, a battery 12, a multiplier 13, an adder 14, an activation function block 15 and a packet register are entered into each of the command packet pools data 16, and each of the blocks of the stack data memory 5 is associated with a priority circuit 17, which is connected to the comparison circuits 18 and the input latch 19 formed by address registers 20 by the number of communication fields of the data packet and data register 21, and the input latches 19 are interconnected with a ring bus 6 and the input bus corresponding from the blocks of the stack data memory 5, and the address registers 20 with the inputs of the respective comparison circuits 18 and the first outputs 22 of the priority circuit 17, the first inputs 23 of each of which are connected to odes of comparison circuits 18, and the second input 24 and second output 25 with the output and input of the same name block of the stack data memory 5, the output bus address 26 of each of the blocks of the stack data memory 5 is interconnected with the address buses of the memory blocks of the teams 2, battery 12, memory data readiness 4, readiness control memory 9, address register 27 of the functional parameter 3 memory block and decoder 11, and the output bus 28 of each of the data stack 5 memory blocks with data buses of command memory blocks 2, functional parameter memory 3 and a running bus of the multiplier 13, the second input and output buses of which are connected respectively to the output bus of the memory block of the functional parameters 3 and the input bus adder 14, the second input bus of which is connected to the output bus of the battery 12 and the output bus to the input register 29 of the battery memory 12 and the input bus of the activation function block 15, the output buses of the activation function block 15 and the command memory block 2 are interconnected with the input bus of the data packet register 16, the output bus of which is connected to the ring 6th bus, output buses of the same blocks of readiness data memory 4, readiness control memory 9 and decoder 11 are bitwise interconnected and interconnected with the input register 30 of the data readiness memory block 4 and with the input bus of the corresponding readiness circuit 10, the output of each of which is connected to the control input corresponding to the input register 30 of the data readiness memory 4, the input register 29 of the battery 12, the address register 27 of the functional parameter memory 3 and the first control input 31 of the register register data networks 16, and the second outputs 25 of all priority circuits 17 are combined by an OR 32 logic element, interconnected with the second control inputs 33 of all data packet registers 16.

The priority circuit 17 may contain two-input logic gates AND AND NOT and sequentially connected two-input logic gates AND, the first inputs 34 of the logic gates AND are NOT connected to the corresponding first inputs 23 of the priority circuit 17, the outputs of the logic gates AND are NOT connected to the corresponding first outputs 22 of the priority circuit 17, the inputs of the multi-input logic element AND and the first inputs 35 of the same logical elements AND, the second input 24 of the priority circuit is connected to the second input 36 of the first logical element AND NOT torym input 37 of the first AND gate, and the second inputs of the remaining AND gates and NOR gates and - to the outputs of the preceding gates I.

Consider the operation of the device for processing the information depicted in figure 1, which uses the priority circuit, made in accordance with figure 2.

In accordance with the values of the signals from the outputs of matching circuits 18 supplied to the first inputs 23 of the priority circuit 17, the first outputs 22 of the priority circuit 17 provide the choice of one of the address registers 20 of the input latch 19 and the prohibition of selecting the remaining registers 20. In the case of a full block of the stack memory 5, the logic zero level at the second input 24 of the priority circuit 17 blocks the transmission of the address field from register 20 and the data value from register 21 of the input latch 19. If, however, the If there is one level, then the logical unit level appears on the second input 24 of the priority circuit 17, which allows the unitary code to be sent to the first outputs 22 of the priority circuit 17. If none of the comparison circuits 18 generated a match signal on the first inputs 23 of the priority circuit 17 or the second input 24 of the priority circuit 17 received a logic zero level (in the case of a full block of the stack of data memory 5), then the second output 25 of the priority circuit 17 generates a signal to prohibit loading of the stack of the data memory 5.

When entering the source data in the input blocks 7 are presented in the form of data packets in the format:

Team Pool Number Command Cell Address Cell address Value

The input data packets from the ring bus 6 go to the input latches 19, and the "Value" field is entered into register 21, and the communication fields consisting of "Command pool number", "Command cell address", "Address in the cell" are sent to the corresponding address registers 20. Comparison schemes 18 compare the address AB _i (1≤I≤r), r is the number of instruction packet pools in the device, the ith block of the data stack 5, with the "Command pool number" fields of all address registers 20. Coincidence though at least one comparison circuit 18 addresses the AV contents from the register _i 20 sets the level of the logical unit at the corresponding first input 23 of the priority circuit 17, which leads to the formation on the corresponding second output 22 of the priority circuit 17 of the logic zero level of the sample signal of the address register 20 and at the second output 25 of the priority circuit 17 of the load enable signal of the stack data storage unit 5. The communication field from the selected address register 20 and the data value from the data register 21, the codes of which then appear, respectively, on the output bus, are loaded into the stacked data memory block 5 no address 26 and output data bus 28. The field "Value" x _i on the data bus 28 enters the pool of command packets 1. Moreover, in the command pool 1 is fixed not entered on the bus 28 value code x _i , but the selected one (in accordance with the address information on the bus 26) from the functional parameter memory 3, the weight coefficient w _i , which, when transmitted through the multiplier 13, is converted to the product value x _i w _i , and is added to the adder 14 with the previously accumulated value selected from the same address section of the battery 12. On in During adder new value is formed, which via an input register 29 is fixed at the same address in the storage memory unit 12. In other words, the value x _i is stored in one cell command pool, and the accumulation of products produced w _i x _i, all associated with a Received present input values x _i . At the same time, in the same address section of the data readiness memory block 4, the corresponding readiness bit is set to zero by performing the bitwise OR operation between the current readiness word value selected from memory 4, read out from the readiness control memory block by 9 words and the unitary code generated by the decoder 11 in accordance with the code from the "Address in cell" field of the data packet. The result of the bitwise operation through the input register 30 is fixed in the same address section of the data ready memory 4 as the current data ready word. The zeroing of all the readiness bits in a certain address section of the data readiness memory block 4 is monitored by the readiness circuit 10, which initiates the delivery of data packets 16 to the register and then on the ring bus 6 data packets, in the communication fields of which the address information about the command cells - result receivers is entered (the fields "Command pool number", "Command cell address", "Address in the cell") from the command memory block 2, and in the "Value" field - a digital code from the output of the activation function block 15, which compares the accumulated in the accumulator memory block 12, the sum of all the works x _i w _i received at this time with the threshold of operation of the formal neuron w ₀ selected from the memory of functional parameters 3, and the automatic scaling of the result. The issuance of w _{0 is} ensured by zeroing the address register 27, through which the field "Address in the cell" of the data packet arrives at the address bus of the memory block of the functional parameters 3. After fixing the data packet in the register 16, the command cell is initialized by resetting the input register 29 and the corresponding address section of the battery memory 12 and writing a word from all units through the input register 30 into the same address section of the data readiness memory 4 of the inventive device for processing information.

The processing process, as follows from the above, in the device for processing information is carried out directly in the pools of the command packets 1 and is combined in time with the fixation of newly arriving data packets in the block of the stack data memory 5. Moreover, the processing process consists in the cyclic execution of read, modify and recording the contents of the data readiness memory 4, the battery 12 and the functional memory 3, the completion of which is controlled by the readiness 10, translating active command cell to its initial state and allow the formation of data packets in data packets 16. Formed received in ring bus 6 and entered via the input latches 19 into corresponding fields of "pool number command" data block of stack memory 5. Next - similar to the process data input.

When outputting the results of the calculations in the form of data packets, the communication fields of each of which corresponds to one of the addresses of the data output blocks 8, enter the ring bus 6 and are entered into the input latches of the data output blocks 8.

The programming mode of the device for processing information is necessary to set the topology of the implemented neural network. When programming, it is necessary for each command package in the corresponding address section of the memory block 2 to enter the address codes of the command packages - the result receivers. In this case, the value of the address of the command packet - the receiver of the result (field "Value") of the data packet generated in the input unit 7, through the ring bus 6, the input latch 19 is entered in the block of the stack data memory 5 (field "number of the command pool"), and then, via bus 28, to the address section (the "Command cell address" field and the "Address in the cell" field) of command memory block 2.

The setting mode of the functional parameters of the device for processing information is necessary to set weight coefficients and thresholds for the operation of formal network neurons. Setting functional parameters is usually done after programming the inventive device. The process of entering the values of functional parameters is similar to the above programming sequence with the only difference being that the “Value” field of the data packet is placed in the address section of the corresponding memory block of functional parameters 3. Performing the setup procedure after programming the device is essential when solving problems in a neural network basis, because the programming process sets the connections between the elements of the neural network, and the functional parameters are selected in the learning process of the already formed network and stored in the memory blocks of the functional parameters 3. If the neural network is trained and the values of the functional parameters are known in advance, then the programming procedure and settings of the protected device for processing information may be arbitrary.

The feasibility of the device for information processing is due to the use of generally accepted technical solutions of blocks, nodes and elements as part of the claimed device (see, for example, Kagan BM Electronic computers and systems. - M .: Energoatomizdat, 1991), and also follows from the above descriptions of the operation of the device for processing information in various modes of its operation.

Based on the foregoing, the claimed combination of components of an information processing device allows us to solve the problem of increasing the productivity of a protected device for processing information by combining in time the process of loading the values of the operands and the data conversion process, as well as organizing the processing of information at its storage location in local pools of command packages which indicates the achievement of the goal.

The information protection effect in the claimed device is due to the interconnection of its components described in the present invention, which ensures, firstly, the addressless entry of data packets into specialized memory blocks of command packet pools, which complicates unauthorized modification of data, and secondly, the selection of data packets from command pools packets are automatically generated as the result is formed and is not associated with the initiation of the procedure for reading information at a given address from the outside, which eliminates unsan Access to stored data.

Claims (2)

1. An information processing device comprising command pack pools, each of which consists of a command memory block, a functional parameter memory block and a data ready memory block, stacked data memory blocks, a ring bus to which data input units and data output units are connected, characterized in that input latches are introduced into the device, each of which consists of address registers by the number of communication fields of the data packet and data register, a comparison circuit and a priority circuit, and in each of the instruction pools of the received packets, the readiness control memory block, the readiness circuit performing the logical OR operation, the decoder, the accumulator memory block, the multiplier, the adder, the activation function block and the data packet register, the control output of the stack data memory block are connected to the second priority circuit input, the first the inputs of which are connected to the outputs of the comparison circuits, and the first outputs are connected to the inputs of the address register selection, the inputs of the address registers and the data register are connected to the ring bus, the outputs of the address registers, on The communication field “command pool number” is connected to the first inputs of the comparison circuits, the second inputs of which receive the address of the ith block of the data stack memory (i = l, r), where r is the number of pools of command packets in the device, the outputs of the address registers and the data register are connected to the input bus of the stacked data memory block, the control input of which is connected to the second output of the priority circuit, the output bus of the address of the stacked data memory block is connected to the address buses of the instruction memory block, the accumulator memory block data readiness memory, readiness control memory, decoder, address register of the memory block of functional parameters, the output data bus of the stack data memory block - with data buses of the command memory block, functional parameter memory block, the input bus of the multiplier, the second input and output buses of which are connected with the output bus of the functional parameter memory unit and the first input adder bus, respectively, the second input bus of which is connected to the output bus of the battery memory, and the output one bus - with the input register of the battery pack and the first input bus of the activation function block, the second input bus of which is connected to the output of the functional parameter memory block, and the output bus, on which a digital code is generated representing the “value” field in the communication field of the data packets, and the output bus of the instruction memory block is connected to the input bus of the data packet register, the output bus of which is connected to the ring bus, the output buses of the data readiness memory blocks, the readiness control memory and the decoders are bitwise integrated and connected to the input register of the data readiness memory block and to the input bus of the readiness circuit, the output of which is connected to the control inputs of the input register of the data readiness memory block, the input register of the battery storage unit, the address register of the functional parameters memory block and the data packet register the outputs of all priority circuits are combined by an OR gate, the output of which is connected to the second control inputs of all the data packet registers. 2. The device for processing information according to claim 1, characterized in that the priority circuit contains two-input logic elements AND and NOT connected in series two-input logic elements AND, the first inputs of two-input logic elements AND are NOT connected to the corresponding first inputs of the priority circuit, the outputs are two-input logical gates AND NOT - with the corresponding first outputs of the priority circuit, the first inputs of the same two-input logic elements AND and the inputs of the multi-input logic element AND, the output to which is the second output of the priority circuit, the second input of the priority circuit is connected to the second input of the first two-input logic element AND AND the second input of the first two-input logic element AND, and the second inputs of the remaining two-input logic elements AND and the two-input logic elements AND - with the outputs of the previous ones two-input logic elements I.

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