RU2326485C1 - Method of current regulation at output of bridge transistor inverter - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: invention is related to electric equipment, in particular to relay systems of automatic current regulation, and may be used in power transducers of direct and alternating current with circuit of negative feedback by current of inverter load. Method of current regulation at the output of bridge transistor inverter, which is made from parallel connected to source two-switch modules with logical devices, which provide for open condition of top or bottom transistors of two-switch modules, at which the instant value is measured and current mark at the outlet of inverter, the measured value is compared with the setting signal of current, the mark is identified and the value of their difference (error signal), after the error signal achieves the threshold value, the transistors are switched only in one of two switch modules, and with open only top or only bottom transistors of modules the time τ delay starts, and with unchanging mark of error signal, transistors of two-switch module are switched, and in case of error signal mark change and reaching threshold value, transistors of first module are switched until time τ delay elapses.

EFFECT: increases efficiency factor and precision of inverter regulation.

3 cl, 2 dwg

Description

The invention relates to electrical engineering, in particular to relay systems for automatic current control, and can be used in power converters of direct and alternating current with a negative feedback circuit for the load current of the inverter.

A known method of regulating the current at the output of a bridge inverter [1], in which measure the value and sign of the current at its output, compare it with a given current value, determine the magnitude and sign of their difference (regulation error). Then, the measured error is compared with two threshold values ΔI and ΔI '', of which ΔI> ΔI ''. As a result of comparisons according to a special program, a sequence of switching on and off the power transistors of the bridge is formed. The shape of the output current of the inverter with this method of regulation is obtained two-stage and always with a maximum amplitude of deviation ΔI in both directions from the set value I _ass .

A smoother current curve with a single-stage ripple is provided by the control method proposed in [2]. With this method, the magnitude and sign of the current control error, as well as the sign of the current, are also determined and, with a positive sign of the difference (error), the command is turned on to turn on one of the transistors of the negative current direction and at the same time turn on the time delay count. After exposure, the command to turn off the transistor is removed. With a negative sign of the difference, similar operations are performed with a transistor of a positive current direction, taking into account the corresponding time delay. The time delay in the function of the error signal is adjusted after it is rectified, i.e. modulo this signal.

The disadvantage of this method of current regulation is the mismatch of the average current value with its task. When a sinusoidal current is formed, this method leads to a phase lag of the main harmonic of the current from its reference signal, i.e. to inaccuracy of regulation.

Proposed in the present invention, the method of regulating current does not have a noted drawback. The average current value always coincides with its task. With the same permissible level of high-frequency ripples of the load current (high-frequency deviations from the reference signal), this allows a lower frequency of switching on and off of the power bridge transistors, i.e. to have less than the prototype switching losses of power transistors and, therefore, to have a higher inverter efficiency (COP).

The technical result is an increase in efficiency and accuracy of regulation of the inverter current.

The technical result is achieved in that the switching of the two-key inverter modules is carried out according to the current control error signal and after it reaches the threshold value, only one of the modules is switched, then their state is compared and, if it turns out to be the same, the time delay countdown τ begins. If during the time τ the error signal does not change sign, then the transistors of the second two-key module are switched, if before the end of exposure τ the error signal changes sign and reaches a threshold value of a different sign, then the transistors of the first module are switched without waiting for the end of exposure τ.

The proposed method of regulating the current can be implemented, for example, using a device whose functional diagram is shown in figure 2, and figure 1 shows a diagram of the change in the output current of the inverter.

A device for implementing the method comprises a current controller 1, an adder 2, a delay element 3, a signal switch 4, relay elements 5 and 6, a counting trigger 7, an exclusive or 8 logic element, a signal inverter 9, logic devices 10 and 11, two-key transistor modules 12 and 13, load 14 and current sensor 15.

The current collector 1 is an adjustable voltage source, such as a potentiometer, and the functions of the summing device 2 are usually implemented using an operational amplifier

The delay element 3 is a device with two inputs, of which the first signal, and the second logical. If a logic zero is present at its second input, then a signal is generated at the output of the delay element as an integral function of the signal at the first input. If at the second input of the element there is a logical unit, then at its output a zero signal is set regardless of the level and sign of the signal at its first input.

The signal switch 4 consists of four semiconductor switches, the control inputs of which are combined in pairs, as shown in figure 2, and using the logic signals at these inputs, they either connect their first input to the first output, and the second input to the second output, if the signal combination on the control inputs of switch 01 and, accordingly, the first input to the second output, and the second input to the first output, if the combination of signals at its control inputs is 10.

The outputs of the signal switch 4 are connected to the inputs of the relay elements 5 and 6 with the same symmetrical hysteresis characteristics for both. The first output is to the input of the relay element 5, and the second is to the input of the relay element 6.

The output of the relay element 5 is connected to the input of the logic device 10 that controls the two-key module 12, and to the first input of the logic element 8, and the output of the relay element 6 to the second input of the logic element 8 and through the inverting element 9 to the input of the logic device 11 that controls the two-key module 13 .

Logic element 8 provides a logical unit at its output if the signals at its inputs have the same sign (both plus or both minus) and provide a logic zero if signals with different signs appear at its inputs.

Logic devices 10 and 11 provide the open state of the “upper” transistor of the two-key module if the signal at the input of the device is positive, and the open state of the lower transistor of the same module if the signal at its input is negative. When changing the sign of the signal, the logic device provides a standard delay for unlocking the transistor switch, eliminating the "through" current in the transistor module.

The output of logic element 8 (the standard logic element is “exclusive or”) is connected to the counting input of trigger 7 and to the second logical input of delay element 3. Counting trigger 7 is switched by the leading edge of the output signal of logic element 8. The outputs of trigger 7 are connected to the control inputs of the keys of the signal switch 4, forming a logical code of either 01 or 10.

The sign and steepness of the increase in the output signal of the delay element 3 at each occurrence of a logical zero at its second input depends on the sign and magnitude of the signal at its first input, i.e. from the magnitude of the current error, which is generated in the form of a signal proportional to it at the output of the summing device 2. The time during which the output signal of the delay element reaches the threshold of one of the relay elements 5 or 6 is the holding time τ.

Connected in parallel to the source U _{n, the} two-key modules 12 and 13 form a bridge, in the diagonal of which the load 14 and the current sensor 15 are connected in series. The output of the current sensor 15 is connected to the second input of the summing device 2.

The load is an electric circuit of series-connected active resistance R _n , inductance L _n and counter EMF E _n . We assume that the condition U _n > E _{n is} always satisfied.

It is more convenient to consider the operation of the device at first without taking into account the operation of the signal switch 4, assuming that the counting input of the trigger 7 is disconnected from the output of the logic element 8, while the output of the trigger 7 is in state 01. This means the state of the switch keys in which the output of the summing device 2 is constantly connected to the input of the relay element 5 and, through the delay element 3, to the input of the relay element 6.

Suppose that under the influence of an error signal, relay elements 5 and 6 have the same sign of the output signal, for example, “plus”. This means that the upper transistor of the two-key module 12 and the lower module 13 are open, while at the output of the logic element 8 there is a signal in the form of a logical unit that resets the output of the delay element 3. Under the action of the source voltage plus U _n and counter-EMF current in the load circuit increases in the positive direction (time interval t ₁ -t ₂ ). In this interval, we assume that the opposite EMF is directed counter to the positive current.

After the load current rises to a value greater than the specified value by Δ (moment t ₂ ), the control error, changing its sign, reaches the threshold of the relay element 5. At its output, a negative signal appears, blocking the upper and unlocking lower transistors of the two-key module 12. At the same time, a logic zero appears at the output of logic element 8 and the time delay τ begins. The combination of signals established in this interval keeps the lower transistors of the two-key modules 12 and 13 closed. The load circuit is shorted and the current drops under the action of the counter-EMF (interval t ₂ -t ₃ ).

If the load current has time to decrease to the value of I _ass. -Δ for a time less than the shutter speed τ, then the relay element 5 is switched back (moment t ₃ ) with the appearance of a positive sign at its output and a logical unit at the output of element 8. The output of delay element 3 is reset again, and under the action of voltage U _n -E _n the load current rises again to the value of I _ass. + Δ (interval t ₃ -t ₄ ).

At time t ₄ , the control error, changing its sign, again reaches the threshold of the relay element 5, a negative signal appears again at its output, a short-circuited circuit is formed from the lower transistors of modules 12 and 13, and again the current drops under the action of the counter-EMF (interval t ₄ -t ₅ ). Further, the process can be repeated in the sequence already described.

Now let the opposite EMF be directed in accordance with the current and the initial conditions correspond to the moment t ₅ . The current in the load circuit shorted by the lower transistors of modules 12 and 13, from the moment t ₅ will already increase under the action of the changed sign opposite the EMF, increasing the control error and simultaneously reducing the time τ.

At the time t _{6 the} end of the exposure τ with a negative signal from the output of the delay element 3, the relay element 6 is switched with the appearance of a negative sign at its output. In this state of the circuit, the outputs of the relay elements 5 and 6 will both be negative. This means that the lower transistor of module 12 and the upper one of module 13 are open. The load current decreases under the influence of the voltage difference minus U _n and counter EMF, which coincides in voltage with the load current (interval t ₆ -t ₇ ).

After the load current decreases to the value of I _ass. -Δ (moment t ₇ ), the control error, changing its sign, reaches the threshold of the relay element 5, the output of which appears a positive signal. Now, the upper transistors of the two-key modules 12 and 13 hold the load circuit in a shorted state and the current increases again under the action against the EMF (interval t ₇ -t ₈ ). At time t ₈ it reaches the value of I _ass. + Δ and, therefore, the threshold of the relay element 5, which changes the sign at the output from positive to negative. At the new interval t ₈ -t ₉ , the lower transistor of module 12 and the upper module 13 will open. The load current will again decrease under the influence of the voltage difference minus U _n and counter EMF, which coincides in sign with the current I _n , reaching the level I _n -Δ at the point t ₉ and, therefore, the threshold of the relay element 5. At its output, a positive signal is set. The upper transistors of the two-key modules are closed again and in the shorted load circuit the current again increases under the action of the counter-EMF (interval t ₉ -t ₁₀ ). Further, the process can be repeated in the described sequence.

Now let the opposite EMF become equal to zero and the initial conditions correspond to the moment t ₁₀ . The increase in current in the load circuit shorted by the upper transistors will stop, and due to the resistance in this circuit, the current will begin to slowly decrease. After the time delay t has expired at time t _{11, the} relay element 6 is switched from the output of the delay element 3 to a positive signal. As a result, at the interval t ₁₁ -t ₁₂ the upper transistor of module 12 and the lower transistor of module 13 are open. The load current increases under the action of voltage plus U _n , while the output of the logical element 8 there is a signal in the form of a logical unit, i.e. the output of delay element 3 is zero. At time t _{12, the} current reaches the value of I _ass. + Δ, and with it the threshold of the relay element 5, which switches to the negative output position, and the load circuit is shorted by the lower transistors of the modules. The time delay τ begins. The current slowly decreases again (interval t ₁₂ -t ₁₃ ). At time t ₁₃ , the time delay τ ends and a negative signal from the output of the delay element 3 switches the relay element 6. In the new state of the circuit, the lower transistor of module 12 and the upper module 13 are open. The current drops under the action of voltage minus U _n (interval t ₁₃ -t ₁₄ ) At time t ₁₄ it reaches the value of I _ass. -Δ, i.e. the threshold of the relay element 5, which switches to the position with a positive output. The load circuit is again shorted by the upper transistors of the modules, while the load current continues to slowly decrease, increasing the error at the output of the summing device and at the same time reducing the holding time τ (interval t ₁₄ -t ₁₅ ).

At time t ₁₅ , the shutter speed τ ends and the relay element 6 is switched at the output of the delay element 3. The outputs of the relay elements 5 and 6 are positive, at the output of the logic element 8, the signal is in the form of a unit, the output of the delay element 3 is “zeroed”, and in the power the upper transistor of module 12 and the lower module are open to the circuit. The current in the load circuit increases under the action of voltage plus U _n (interval t ₁₅ -t ₁₆ ). At time t _{16, the} current reaches the value I _ass + Δ, and the error signal reaches the negative threshold of the relay element 5. After switching, a negative signal is generated at the output and the load circuit is again short-circuited by open lower transistors of modules 12 and 13 (interval t ₁₆ -t ₁₇ ) Further, the process can continue in the described sequence.

Now let the current task become equal to zero and the initial conditions will correspond to the moment t ₁₇ . Under the influence of a large absolute value of the negative error at the output of the summing device, a negative signal rapidly increases modulo the output of the delay element 3 and the relay element 6 switches to the negative output state (moment t ₁₈ ). On the interval t ₁₈ -t ₁₉ the lower transistor of module 12 and the upper module 13 are open. The load current drops under the influence of voltage minus U _n and at time t ₁₉ reaches the value minus Δ, i.e. positive threshold of the relay element 5, which returns to the state with a positive signal at the output. The load circuit is again short-circuited by the upper transistors of modules 12 and 13, and the current slowly decreases in absolute value until the end of the time delay τ (interval t ₁₉ -t ₂₀ ). At time t _{20, the} relay element 6 is switched from the output of the delay element 3, and on the interval t ₂₀ -t ₂₁ the upper transistor of module 12 and the lower transistor of module ₁₃ are open. The load current rises to plus Δ and, therefore, to the negative threshold of the relay element 5. On the interval t ₂₁ -t ₂₂ the load circuit is again shorted by the lower transistors of the modules. At time t ₂₂ , the relay element 6 again switches under the influence of the negative signal of the delay element. Next, the process continues in the described sequence, as shown in figure 1.

So, we examined the operation of a device that implements a method of regulating current in all possible modes of operation of the inverter, but without taking into account the signal switch 4 and trigger 7. It is easy to verify that in such a circuit during prolonged operation of the inverter to the load circuit with unidirectional current and counter EMF, for example when working on an anchor of a DC motor, an uneven current loading of transistors and reverse diodes of modules 12 and 13 occurs. This is due to the fact that the zero pause of the output voltage is constantly generated due to Access the state of only the upper or only the lower transistors two-key modules. At these moments, the current flowing through one of them and the reverse diode of the other will cause a stronger overheating of such more current-loaded elements. To avoid this, you can periodically swap the inputs for connecting relay elements using the signal switch 4, connecting the input of the relay element 5 to the output of the summing device 2, then to the output of the delay element 3, and the input of the relay element 6, respectively, then to the output of the delay element 3, then to the output of the summing device 2. The frequency of such switching can be achieved using a trigger 7 with a counting input, using the output of the logical device 8 as a signal for switching.

Information sources

1. Brodsky V.N., Ivanov E.S. Drives with frequency-current control. M .: Energy, 1974.

2. A.S. No. 1309221 dated 01.07.87, Bull. Number 17. N.V. Donskoy, V.A. Matison. A method of controlling the current at the output of a bridge transistor inverter.

Claims (3)

1. The method of regulating the current at the output of a bridge transistor inverter made of parallel two-key modules connected to the source with logic devices providing an open state of either the upper or lower transistors of the two-key modules, in which the instantaneous value and sign of the current at the inverter output are measured, and the measured value is compared with the current reference signal, determine the sign and value of their difference (error signal), characterized in that after the error signal reaches the threshold value of ne They turn off the transistors in only one of the two-key modules and when only the upper or only lower transistors of the modules are open, they start the time delay τ, and if the sign of the error signal is not changed, the transistors of the second two-key module are switched, and when the sign of the error signal is changed and the threshold value is reached, the transistors of the first module to the end of the time delay τ. 2. The method according to claim 1, characterized in that the time delay t is reduced with an increase in the error signal. 3. The method according to claim 1 or 2, characterized in that the transition of the two-key modules in the same state is performed, providing alternation of open upper with open lower transistors in them.

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