RU2325684C2 - Device for communication means control - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: invention is related to the sphere of gauging equipment and may be used in systems of automated control and radio-electronic objects diagnostics. The specified result is achieved due to introduction of interval estimate unit in device for communication means control (for determination of upper and lower limits of confidence interval of investigated complex signal in two-dimensional feature space). Validity of signal distortion extent is achieved by images recognition of monitored and investigated state diagrams (SD), which were obtained as result of monitored object output signal division into two components, which differ from each other by the value less than the period and form a closed figure on the plane. Suggested diagnostics method with application of two-dimensional feature space allows increasing validity of monitored communication facility technical condition estimation.

EFFECT: improves accuracy of communication facilities technical condition class recognition in diagnostic control.

1 dwg

Description

The invention relates to the field of measuring equipment and can be used in systems for automated monitoring and diagnostics of electronic objects.

A device for monitoring electronic products containing a control object, switches, a meter for the coefficient of mutual difference of signals, an analog-to-digital converter, a unit for calculating deviations and parameter estimates, a control unit, a key, a signal shaper, a signal switch, a stimulating signal block and a result output unit control (see RF patent for the invention No. 2071107, CL G05B 23/02, publ. 12/27/1996, bull. No. 36).

The disadvantage of this device is the low accuracy of the assessment of the technical condition of the object in the process of diagnostic control according to the results of measuring a complex indicator in the form of a coefficient of mutual difference between the distorted and reference signals.

The closest in technical essence to the claimed invention relates to a device for monitoring analog objects, comprising a control and stimulating signal generating unit, reference signal generating unit, multiplication units, a frequency converter, a phase shifter, a switch, a frequency shaper, integrators, squaring units, an adder , standardization unit, key, analog-to-digital converter, interval evaluation unit, comparison circuits, memory unit, reference number analysis unit coefficient mutual differences, registers and an information display (see. RF patent №2262128, cl. G05V 23/02, publ. 10.10.2005, Bull. №28).

The disadvantage of this device is the low accuracy of recognition of a failure in a controlled object. This is due to the fact that due to the influence of various destabilizing factors, the result of measuring a complex indicator of the technical condition of the object differs from the true value. However, the known device does not provide for image recognition of a controlled and investigated state diagram (DS) in a two-dimensional feature space.

The main task, the solution of which the claimed device is directed, is to increase the accuracy of recognition of the class of technical condition of communication facilities during diagnostic monitoring.

The specified technical result is achieved by the fact that in the known device for monitoring communications, an interval estimation unit is additionally introduced (to establish the lower and upper boundaries of the confidence interval of the complex signal under study in a two-dimensional attribute space).

The drawing shows a structural electrical diagram of the device.

The device for monitoring communications includes a start button 1, a clock generator 2, a first counter 3, a key 4 element, a first element 5 AND, a key 6, a delay element 7, two analog-to-digital converters 8 and 9, two registers 10 and 11, interval estimation blocks 12 and 13, second element 14 AND, block 15 of operative memory of the evaluation results, third element 16 AND, second counter 17, memory block 18, M comparison circuits 19 ₁ ÷ 19 _m , M registers 20 ₁ ÷ 20 _m and an information output unit 21.

The device operates as follows.

Before starting work, the block 15 of the random access memory of the evaluation results, as well as the registers 10 and 11 are in the initial (zeroed) state. In the cells of the memory unit 18, information about malfunctions in the monitored object is recorded.

When the “Start” button 1 is pressed, the voltage is applied to the input of the 2 clock pulses generator, from the first output pulses are sent to the first input of the first 5 And elements and to the first input of the third 16 And elements, and from the second output pulses are sent to the first 3 counter, which the first pulse switches the key 4 element to position "1". From the output of the key 4 element voltage is supplied to the second input 5 of the first element I.

и верхнего

значений доверительного интервала

(т.е.

по оси абсцисс и формирование нижнего

и верхнего

значений доверительного интервала

по оси ординат (т.е.

двумерной признаковой плоскости. Попадание опорных значений х_i и у_i в доверительные интервалы формирует на выходе второго элемента 14 И сигнал логической «единицы». В противном случае, если хотя бы одно из опорных значений по оси абсцисс или оси ординат не попадет в доверительный интервал, то выходной сигнал второго элемента 14 И будет соответствовать логическому «нулю». С выхода второго элемента 14 И напряжение подается на вход блока 15 оперативной памяти результатов оценки.The studied signal from the output of the control object is fed to the information input of the key 6. The voltage supplied from the starting 1 element through the open first 5 element And to the control input of the key 6, ensures the passage of the values of the studied signal through the delay element 7, analog-to-digital converters 8 and 9, and further, in a transformed form, to the corresponding inputs of the registers 10 and 11. From the outputs of the registers 10 and 11, the signals are fed to the input of the interval estimation blocks 12 and 13, which form the lower

and top

confidence interval values

(those.

abscissa and lower

and top

confidence interval values

y-axis (i.e.

two-dimensional sign plane. The falling reference values x _i and y _i in confidence intervals forms the output of the second element 14 And the signal is a logical "unit". Otherwise, if at least one of the reference values along the abscissa or ordinate axis does not fall within the confidence interval, then the output signal of the second element 14 AND will correspond to a logical “zero”. From the output of the second element 14 And the voltage is applied to the input of the block 15 of the RAM of the evaluation results.

When counting the N-th pulse from the output of the first counter 3, a signal is sent to the key 4 element, transferring it to the state "2", after which the first 3 counter is reset. The device is transferred from the signal evaluation mode to the analysis of results. In this case, the first element 5 And closes, and the voltage from the key 4 element opens the third element 16 And, from the output of which clock pulses are fed to the input of the second 17 counter. The output of the second 17 counter is connected to the control inputs of the comparison circuits 19 ₁ ÷ 19 _m The first information input of the comparison circuits 19 ₁ ÷ 19 _{m is} connected to the output of the memory unit 18, and the second is connected to the output of the memory unit 15 of the evaluation results. With the first clock cycle of the second counter 17, the values of the RAM block 15 are compared with the first technical condition in the memory block 18. The number of coincidence of values in the first comparison circuit 19 ₁ corresponds to the logical units received at the input 20 _{1 of the} register. The number of pulses of the counter 17 corresponds to the number of technical conditions recorded in the memory unit 18. After the M pulse of the second 17 counter, a comparison is made of the values of units in the M comparison circuit 19 _m supplied to the input of the register 20 m. The largest number of logical “units” in one of the 20 ₁ ÷ 20 _m register corresponds to a specific technical condition recorded in the memory unit 18. Information about the register number 20 _α , in which the largest number of logical “units” is recorded, is fed to the input of the information output unit 21. At the time of receipt of information, the information output unit 21 is supplied with an enable signal in the RAM unit 15 of the signal evaluation results for zeroing the values of memory cells .

Since the Mth pulse at the output of the second counter 17 corresponds to the Mth pulse calculated by the first counter 3 at the second stage of the device operation, the key 4 element switches to the “1” position from the output of the first counter 3. The device switches to its original position and works in the first mode - signal evaluation.

Thus, when using a two-dimensional feature plane, it allows to increase the recognition accuracy of the class of the technical condition of communication facilities during diagnostic monitoring.

Claims (1)

A device for monitoring communications, containing a key, a first analog-to-digital converter, a first interval evaluation unit, a memory unit, serially connected comparison circuits, registers and an information output unit, characterized in that the Start button, a clock pulse generator are additionally introduced in series , the first output of which is connected to the first inputs of the first and third AND elements, and the second output is connected to the input of the first counter, the output of which is connected to the input of the key element, the element is delayed ki, whose input is connected to the output of the key, to the information input of which the signal under investigation is fed from the output of the monitoring object, the first register, the input of which is connected to the output of the first analog-to-digital converter, the input of which is connected to the output of the delay element, the second element And, the first input of which connected to the output of the first interval evaluation unit, a random access memory block of the evaluation results, the information input of which is connected to the output of the second AND element, the second input of which is connected to the output of the second inter general assessment, the input of which is connected to the output of the second register, the input of which is connected to the output of the second analog-to-digital converter, the input of which is connected to the output of the key, the control input of which is connected to the output of the first element And, the second input of which is connected to the first output of the key element, the second the output of which is connected to the second input of the third AND element, the output of which is connected to the input of the second counter, the output of which is connected to the control inputs of the comparison circuits, the first information input of which is connected n with a memory unit, and the second information input with the output of the RAM unit of the evaluation results, and the output of the information input unit is connected to the input of the RAM unit of the evaluation results.