RU2298856C2 - Method for manufacturing silicon-on-sapphire mis transistor - Google Patents

Abstract

FIELD: microelectronics; integrated circuits built around silicon-on-sapphire structures.

SUBSTANCE: proposed method for manufacturing silicon-on-sapphire MIS transistor includes arrangement of silicon layer island on sapphire substrate, formation of transistor channel therein by doping silicon island with material corresponding to channel type, followed by production of gate insulator and gate, as well as source and drain regions; prior to doping silicon island with material corresponding to channel type part of silicon island is masked; mask is removed from part of silicon island of inherent polarity of conductivity upon doping its unmasked portion and producing gate insulator; in addition, part of gate is produced above part of silicon island of inherent polarity of conductivity; source region is produced in part of silicon island of inherent polarity of conductivity and drain region is produced in part of silicon island doped with material corresponding to channel type.

EFFECT: improved output characteristics of short-channel transistor at relatively great size of gate.

1 cl, 7 dwg

Description

The invention relates to the field of microelectronics and can be used in the manufacture of integrated circuits based on "silicon on sapphire" (SSC) structures, widely used to create digital, digital-analog and analog-digital CMOS LSIs, as well as CMOS LSIs of increased reliability and resistant to radiation influences .

The indicated element base was most widely used in special radio-electronic equipment for space research, radar, communications and telecommunications, liquidation of consequences of radiation and other environmental disasters, nuclear and chemical waste disposal, as well as in equipment for special and civil purposes.

Known MIS transistor on the SSC with an induced channel, in which an additional inversion region is formed, dividing the channel in the surface region into two parts: one between the source and the inversion region, the other between the inversion region and the drain. Thus, the effective channel length is reduced by the length of the inversion region, which allows to obtain short-channel transistors. (V. Fedorov “Over the hill is worse” in the “Commission” section. Scientific and technical journal "Youth Technology", 1998, No. 2, p. 42).

The disadvantage of the described structure of the MOS transistor on the SPS is the difficulty of reproducing the geometric parameters of the locking areas of the channel and, accordingly, the output characteristics of the transistor with a channel size of less than 1.5 μm, which impairs the reliability of the device and limits the possibility of its use in the implementation of submicron transistors with a channel length of less than 1.5 microns.

The closest in technical essence to the proposed device is a MOSFET - field effect transistor (MOSFET) with an induced channel based on the structure of the SPS. (US Patent No. 4106045, MKI 2 H01L 29/78, published 08/08/1978).

An MOS field-effect transistor (MOSFET) with an induced channel based on the SSC structure contains the source and drain regions of the n ⁺ type of conductivity planarly formed in the island of the silicon layer and the p-type conduction region located between them, in which the channel is induced. In order to increase the speed of the device in the switching mode, a p ⁺ region is created in the silicon layer at the boundary with the sapphire substrate between the n ⁺ region of the source and the p region in which the channel is induced. An additional p + region maintains the substrate potential equal to the source potential, thereby preventing the accumulation of holes in the channel region and eliminating the kink effect.

The disadvantage of this structure is its use only for n-channel transistors. Moreover, the formation of an additional p + region does not provide a noticeable increase in speed, since the effective channel length of the transistor does not decrease.

A known method of forming a MIS transistor on the structure of the SSC. (V. Fedorov “Over the hill is worse” in the “Commission” section. Scientific and technical journal "Youth Technology", 1998, No. 2, p. 42).

In the known method, in the islands of silicon created by lithography, pockets of n-type and p-type conductivity are formed on the sapphire substrate using masking and ion implantation. Next, the surfaces of n-type and p-type silicon islands are thermally oxidized to form a gate dielectric of silicon dioxide. Then, using a photolithography, the gate silica SiO _{2 is} masked, leaving a portion of silicon oxide in the central region of the transistor channel unprotected, while the size of the unprotected region is not more than 1/3 of the length of the transistor channel. And after etching the unprotected gate silica, the mask is removed. Silicon nitride Si ₃ N ₄ is deposited on the surface of the gate silicon oxide and the central regions of the transistor channel free of silicon oxide, while ensuring the formation of an “embedded” channel or inversion region at the Si-Si ₃ N ₄ interface and the locking regions in the transistor channel at the interface of Si-SiO ₂ -Si ₃ N ₄ . Next, a shutter is formed of polycrystalline silicon, the regions of drains and sources are formed by the method of ion implantation, and after the interlayer insulation is applied and the contact windows are opened, the contacts are sprayed.

Since the creation of the proposed inversion region involves the use of different dielectric coatings as a gate insulator (SiO ₂ and Si ₃ N ₄ ) or it is necessary to overcompensate the dopant in the surface region of the channel using ion implantation, the implementation of this method is very time-consuming and expensive, it also requires the use of additional photolithographic equipment with a resolution is several times better than that of the base production, which is not realistic when manufacturing a transistor s with a channel length of less than 1.5 microns.

Closest to the technical nature of the proposed method is a method of manufacturing a structure of a MOSFET (MOSFET) with an induced channel based on the structure of the SSC according to US patent No. 41006045. (US Patent No. 4106045, MKI 2 H01L 29/78, published 08.08.08 .1978).

In the known method, initially islands of silicon (Si) are formed on a sapphire substrate (AL ₂ O ₃ ). Then, to form a p-type channel of conductivity, silicon islands by masking and ion implantation are doped with an impurity of p-type conductivity, subjected to thermal oxidation, and a gate dielectric of silicon oxide and a gate of polycrystalline silicon are formed. After that, areas of drains and sources are made. A feature of the manufacture of n-channel transistors is that they form an additional p + region. An additional p + region is created in the silicon layer at the boundary with the sapphire substrate between the n + region of the source and the p region in which the transistor channel is induced. The formation of the p + region is carried out by bombardment with protons of the corresponding region, followed by annealing at a temperature of 800 ° -1000 ° C, simultaneously with the activation of the impurity in the drain and source regions of the transistors, while in the regions subjected to proton bombardment, aluminum diffuses actively from sapphire to silicon with the formation of p + -regions. Then, after applying interlayer insulation and opening the contact windows, aluminum contacts are made.

The known method does not solve the main problem, namely improving performance, but only allows to exclude the "kink effect" in the n-channel transistor.

The disadvantages of this method are:

- the need to include complex additional equipment in the technological cycle;

- limited application of the method, since the method can be implemented only for n-channel transistors.

The present invention relates to the structure of an MOS transistor on an SSC and a method for its manufacture.

The technical problem to which the invention is directed is the creation of an MIS transistor whose channel structure can significantly reduce its effective length while maintaining the dimensions of the gate and the thickness of the gate dielectric.

The technical result from the use of the invention is:

- a significant improvement in the output characteristics of the transistor in current (speed, gain) while maintaining its reliability by eliminating the possibility of breakdown in the locking region,

- a significant increase in the reliability of the device as a whole,

- expanding the scope of the proposed transistor.

The stated technical problem is solved in that in a MIS transistor on a sapphire-silicon structure containing the source and drain regions formed by planar in an island of silicon layer on a sapphire substrate and an isolated gate located between them, according to the invention, the channel boundary with the source made of silicon of its own type of conductivity.

The stated technical problem is also solved by the fact that in the method of manufacturing an MIS transistor on a sapphire-silicon structure, comprising creating a silicon layer of intrinsic conductivity on a sapphire substrate from an island, forming a transistor channel in it by doping the silicon island with an impurity corresponding to the type of channel, followed by creating gate dielectric and gate, and then the manufacture of the source and drain areas, according to the proposed invention, before alloying a silicon island with an impurity corresponding to the channel’s ip, mask part of the silicon island, and after doping the unmasked (open) part of it and until the gate insulator and gate are created, the mask is removed from the part of the silicon island of its own type of conductivity, in addition, part of the gate is created above the part of the silicon island of its own type of conductivity, source regions are made in a part of a silicon island of their own type of conductivity, and drain regions are made in a part of a silicon island doped with an impurity corresponding to the type of channel.

The formation of the intrinsic type of transistor channel adjacent to the source of the channel from silicon, hereinafter referred to as insert for brevity, allows the effective channel length to be reduced without changing the gate size due to the increased mobility and speed of current carriers in the channel part with the silicon native type of conductivity, providing while high reliability of reproduction of the locking part of the channel. In addition, the absence of a dopant in the “insert” region reduces the number of charge carrier scattering centers. The “insert” also makes it possible to lower the threshold voltage of the transistor due to the low concentration of charge carriers in the region of the “insert” and at the same time increase the mobility, which sharply increases the current output characteristics by more than 1.5 times for the same gate length of the transistor channel. The implementation of the channel part from silicon of its own type of conductivity in the proposed manufacturing method is ensured by a set of operations: masking part of the silicon island of its own type of conductivity, doping the unmasked part of the silicon island with the subsequent formation of a part of the gate over the part of the silicon island of its own type of conductivity. The implementation of the channel part of the intrinsic type of conductivity in the form of a boundary with the source region is provided by the creation of source regions in the part of the silicon island of the intrinsic type of conductivity. High reproducibility of the transistor structure of the proposed method ensures the reliability of the devices.

In addition, the preservation of the gate size due to the implementation of part of the channel from Si of its own type of conductivity will provide output characteristics of a short-channel transistor with a larger thickness of the gate dielectric, which will allow:

- increase the resistance to breakdown from static electricity;

- do not reduce the supply voltage and thereby increase the noise immunity of the transistor.

The technical result from the use of the proposed invention is the implementation and provision of output characteristics of a short-channel transistor with relatively large gate sizes, which allows:

- use a larger thickness of the gate dielectric,

- increase the resistance to breakdown from static electricity,

- maintain the same supply voltage,

- increase the noise immunity of the transistor,

- increase the output characteristics (gain, speed) by more than 1.5 times with the same transistor channel length along the gate by increasing the mobility of charge carriers in the region of the transistor channel made of intrinsic silicon and reducing the effective channel length of the transistor.

To achieve the above technical results in the standard embodiment of the transistor (without "insertion" in the channel) it would be necessary to reduce the channel length of the transistor by the gate by at least 1.3 times.

The invention is illustrated in Fig 1-7, where

figure 1 presents the structure of the p (n) -channel MOS transistor on the SSC in the context;

figure 2 shows the stage of forming the boundary between the locking part of the channel and its part with its own conductivity;

figure 3 and figure 4 shows the steps of forming a gate dielectric and a gate;

figure 5 shows the stage of formation of highly doped areas of the source and drain;

figure 6 shows the stage of formation of lightly doped areas of the source and drain, as well as the boundaries of the induced channel;

Fig.7 shows the output current-voltage characteristics of the known n-channel MOS transistor on the SPS with a channel length of L = 1.5 μm (III) and the proposed design of the n-channel MOS transistor on the SPS with the size of the masked region of 1 / 2L channel (I) and 3 / 4L channel (II), respectively.

MOS transistor on the SSC (figure 1) contains a substrate 1 of sapphire (AL ₂ About ₃ ); an island of semiconductor silicon (Si) 2 with the heavily doped regions 3 and 4 formed in it, the lightly doped regions of the source and drain 5 and 6, respectively. Between the source and drain areas 5 and 6, there is a region of the induced channel 7, which is divided into a doped (locking) part 8 and a part with intrinsic (i) conductivity 9. The device contains a gate dielectric 10, for example, of silicon dioxide (SiO ₂ ); shutter 11, for example of doped polysilicon; pads 12, 13, 14 with leads to the areas 3, 4 of the source and drain and to channel 7, respectively; interlayer insulation 15, for example, from layers of silicon dioxide SiO ₂ and silicon nitride (Si ₃ N ₄ ). The length of channel 7 is determined by the length L of the shutter 11. The length l of the part with its own conductivity type 9 of channel 7 for p- and n-channel MOS transistors is selected taking into account the required characteristics of p- and n-channel MOS transistors, depending on the operating conditions. For example, in a CMOS circuit, it is desirable to have the same gain. If one type of transistor is used, then it is possible to use a design with a maximum gain.

Figure 2, 3, 4, 5, 6, illustrating the sequence of formation of the source, drain and channel areas of the proposed design of the MOS transistor, shows the positions at the intermediate stages of its formation: the boundary 16 between the doped locking part 8 of the induced channel 7 and its part with intrinsic conductivity 9; formed by a mask from photoresist 17 (figure 2); a layer of silicon oxide (SiO ₂ ) 18 to create a gate dielectric 10; a layer of polysilicon 19 and a mask 20 of photoresist to form a shutter 11 (Fig.3, 4); mask 21 from photoresist for the formation of heavily doped areas 3 and 4, respectively, of the source and drain (Fig. 5) and lightly doped regions of 5 and 6 of the source and drain (Fig. 6).

The proposed MOS transistor on the SSC with any type of channel works as follows.

In the absence of a supply voltage (Fig. 1) on the gate 11, the channel 7 of length L is locked mainly by its part 8, since for transistors with any type of channel, the part with the proper type of conductivity 9 in channel 7 has a reduced threshold voltage value. When bias is applied to the gate 11 in part 9 of channel 7 even at small values of U _in (for example, 1 V), due to the low threshold voltage, due to the low concentration of charge carriers in this region, a noticeable charge inversion occurs and a large number of charge carriers of the corresponding type appear. With a further increase in the input voltage at the gate 11, the locking part 8 of channel 7 opens and the value of the current _Iout reaches practically at low power (for example, ≤3V) such values that in known transistors (with a channel without a boundary with the source part of the intrinsic type of conductivity) can not always be achieved with U _in = 5V (see FIG. 7). Such results are achieved due to the increased mobility of current carriers in part 9 of channel 7 and the small number of scattering centers due to the absence of dopant in part 9 of the channel, as well as a significant decrease in the effective length of channel 7, since the locking region in channel 7 is only its part 8 , therefore, the performance of the device increases, which is confirmed in Fig. 7 by increasing the steepness (see output characteristics) of the current-voltage characteristics of the n-channel MOS transistors of the proposed design.

Using the proposed design of p- and n-channel MOS transistors on the SPS, the following technical advantages are achieved.

1. Increases the speed of the device by performing boundary with the source part of the channel of silicon intrinsic conductivity by increasing the mobility and speed of current carriers, as well as reducing the effective length of the channel.

2. The gain is increased by reducing the scattering centers and the number of collisions of current carriers with defects of their own type of conductivity.

3. The reliability and noise immunity of the devices is increased due to the possibility of using a gate dielectric with a larger thickness of silicon oxide in submicron transistors, since the proposed design makes it possible to maintain an increased supply voltage.

4. The efficiency of the proposed devices is increased, since it does not require large expenses for the modernization of production capacities to reduce design standards, and consumers also have the opportunity to maintain the same supply voltage in the devices, since reducing the supply voltage requires additional costs.

It was found that the gain (K _whisker ) 1.5 for an n-channel transistor with a gate length L = 1.5 μm is achieved with a size l of an “insert” made of Si own type of conductivity in part 9 of channel 7, equal to 1/2 (0.75 μm) of the shutter length L. For a p-channel transistor, a gain of 1.5 is achieved with a size l of part 9 of Si intrinsic conductivity type equal to 3/4 of the gate length L (≤1 μm). An increase in the size of part 9 of channel 7 for an n-channel transistor more than 1/2 to 3/4 of the length L of the gate 11 leads to an increase in the gain to 1.8-2. The use of such n-channel transistors is possible in circuits when they are not paired with p-channel transistors, so as not to violate the stability of the circuit, therefore, in the case of CMOS circuits, when n and p-channel transistors work simultaneously, for n-channel appropriate value l of the "insertion" 9 to limit the size of 1 / 2L. The size l of part 9 of channel 7, equal to 3/4 of the length L of the gate 11 for the p-channel transistor, does not impair the characteristics of the p-channel transistor in terms of input currents and breakdown voltage of the drain junction. In order to obtain the same gain for n- and p-channel transistors with the same design standards (gate) due to the different mobility of current carriers (holes and electrons) for n-channel transistors, the masked area of the "insert" must be for example 1/2 from region L, and for p-channel transistors the masked “insert” region l should be 3/4 from region L.

A method of manufacturing an MOS transistor on a sapphire-silicon structure is shown with specific examples of the implementation of n- and p-channel transistors with a channel length L (according to the design gate norms) of 1.5 μm.

Example 1. An example implementation of an n-channel transistor.

In the process of forming channel 7 of the transistor, an island 2 of an intrinsic type Si layer (i-type) with a thickness of 0.3 μm located on an Al ₂ O ₃ substrate 1 is masked with photoresist 17 before doping channel 7 so that the unprotected part of island 2 is laid an admixture of p-type conductivity (boron). In this case, the internal boundary 16 (Fig. 2) of the locking part 8 of the channel 7 is determined in advance. Doping with boron (B) is carried out by ion implantation in 2 modes:

mode 1 - boron is implanted at the Al ₂ O ₃ - Si interface with an energy of E = 150 keV and a dose of D = 0.5 μcul / cm ² ;

mode 2 - boron is implanted in the surface region with an energy of E = 40 keV and a dose of D = 0.3 μcoul / cm ² .

After removing the photoresist layer 17, the gate oxidation is carried out and a silicon oxide 18 layer of 350 Å thick is formed, and a polysilicon layer 19 of 0.4 μm thickness is grown to form a shutter 11 (Fig. 3) and doped with phosphorus diffusion. Then, mask 20 is produced using photolithography (FIG. 3), so that part of it is placed over part of the island of silicon of its own type of conductivity to form a shutter 11 located both above part of the island of Si of its own type of conductivity and above the doped part of the island. In this case, the operation of combining the template after applying the photoresist is done by snapping to the edge of island 2 or to the border 16. In this manufacturing example, with a mask size of 1.5 μm, it was placed over border 16 with an overlap of 0.75 p-type doped part μm (i.e. 1/2 L).

After etching polysilicon 19 and removing the photoresist 20 (Fig. 4), a mask 21 (Fig. 5) is created and highly doped regions 3 and 4 are formed, respectively, of the source and drain of the transistor. Region 3 is formed in the Si part of the intrinsic conductivity type of island 2, and region 4 is formed in the doped part of Si of island 2. For this, phosphorus (P) is ion implanted with an energy of E = 40 keV and a dose of D = 700 μc / cm ² (Fig. 5). Then, mask 21 is removed and repeated ion implantation P is carried out with an energy of E = 40 keV and a dose of D = 100 μcul / cm ² to create lightly doped areas 5 and 6, respectively, of the source and drain, while simultaneously forming the external boundaries of channel 7 (Fig. 6). Alloy impurities are activated at a temperature of T = 850 ° ÷ 900 ° C, interlayer insulation 15 is made of SiO ₂ and Si ₃ N ₄ with a thickness of 0.35 μm, and after opening the contact windows in the interlayer insulation 15 form aluminum contacts 12, 13 and 14 to source, drain and channel 7, respectively.

Example 2. An example implementation of a p-channel transistor.

All stages of the formation of the semiconductor structure of the proposed transistor are similar to the steps described in example 1 in the manufacture of an n-channel transistor. But at the stage of forming the locking part 8 of channel 7, the unprotected mask 17 of the part of the island 2 Si is doped with an n-type impurity (phosphorus) using ion implantation, which is carried out by doubly charged phosphorus. Since the dopant impurity of phosphorus has a large ionic radius, it is possible to dope over the entire thickness of 0.3 μm of a 2 Si film only with a higher ion energy of 200–250 keV. In the presence of the Lada-30 installation, this is ensured by doubly-charged phosphorus ions with an energy of E = 150 keV and a dose of D = 0.1 μcul / cm ² .

The difference in the formation of a mask 20 with a length L = 1.5 μm during the creation of the shutter 11 is the L - l value of the mask 20 overlapping from the boundary 16 to the part of island 2 doped with an n-type impurity impurity (phosphorus), which is for a p-channel transistor can be at least 1 / 3L, that is, at L = 1.5 microns - at least 0.5 microns.

To form heavily doped areas 3 and 4 of the source and drain, boron is used as the dopant, and ion implantation is carried out with an energy of E = 40 keV and a dose of D = 500 μc / cm ²

Re-implantation with boron to create lightly doped areas 5 and 6, respectively, of the source and drain, with the simultaneous formation of the external boundaries of channel 7, is carried out with an energy of E = 40 keV and a dose of D = 30 μc / cm ² .

To create p- and n-channel transistors with the same gain equal to, for example, K _us = 1.5, it is necessary for the p-channel transistor to increase the size C of part 9 of channel 7.

The method described above can be used to create p- and n-channel MOS transistors on a SPS with a short channel and provides reliable reproducibility of the proposed structures and does not require special equipment.

Claims (1)

A method of manufacturing an MIS transistor on a sapphire-silicon structure, comprising creating a silicon layer of intrinsic conductivity on a sapphire island substrate, forming a transistor channel therein by doping the silicon island with an impurity corresponding to the channel type, followed by creating a gate dielectric and a gate, and then manufacturing regions source and drain, characterized in that before doping the silicon island with an impurity corresponding to the type of channel, a part of the silicon island is masked, and after doping the non-mask of its part and before creating a gate insulator and a gate, a mask is removed from a part of a silicon island of its own type of conductivity, in addition, a part of the gate is created above a part of a silicon island of its own type of conductivity, while the source regions are made in the part of a silicon island of its own conductivity type, and the drain areas made in the part of the silicon island doped with an impurity corresponding to the type of channel.

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