RU2287892C1 - Voltage-to-current converter - Google Patents

Abstract

FIELD: electrical engineering; various amplifiers, analog voltage multipliers, and other automation and computer engineering components.

SUBSTANCE: proposed converter has transistors 1, 2, first resistor 3 inserted between emitters of transistors 1 and 2, current-regulating two-terminal networks 4, 5 connected, respectively, between emitters of transistors 1, 2 and negative power supply bus, first current divider 6 whose input is connected to collector of transistor 1, and second current divider 7 whose input is connected to collector of transistor 2; first output of current divider 6 is connected to collector of fourth transistor 9 and functions as current output of device; first output of second current divider 7 is connected to collector of third transistor 8 and functions as second current output of device; second resistor 10 is inserted between emitters of transistors 8, 9; bases of transistors 8, 9 are interconnected and connected to bias source; second output of first current divider 6 is connected to emitter of third transistor 8; second output of second current divider 7 is connected to emitter of fourth transistor 9.

EFFECT: enhanced linearity of input-voltage-to-output-current conversion.

1 cl, 5 dwg

Description

The present invention relates to the field of electrical engineering and can be used in the design of various amplifiers, analog multipliers and other elements of automation and computer technology.

Known voltage-current converters (PNT), having a high linearity of conversion, but with high current consumption [Schlotzhauer K.G., Metz A.J. Cascode feed-forward amplifier // US Patent No. 4322688. - 06/20/1982].

The closest technical solution adopted for the prototype is PNT, given in [Herpy M. Analog Integrated Circuits: Trans. from English - M.: Radio and Communications, 1983. (p. 366, Fig. 8.12)]. Figure 1 shows a simplified prototype circuit comprising a first transistor, the base of which is the first input of the device, a second transistor, the base of which is the second input of the device, a resistor connected between the emitters of the first and second transistors, a first current-stabilizing two-terminal connected between the emitter of the first transistor and negative power supply bus, a second current-stabilizing two-terminal device connected between the emitter of the second transistor and the negative power supply bus, output outputs oystva collectors are respectively first and second transistors.

The disadvantage of the prototype is its low linearity of the conversion of the input voltage to the output current.

The aim of the invention is to increase the linearity of the voltage-current conversion.

To achieve this goal in the prototype circuit containing the first transistor, the base of which is the first input of the device, the second transistor, the base of which is the second input of the device, a resistor connected between the emitters of the first and second transistors, the first current-stabilizing two-terminal connected between the emitter of the first transistor and the bus a negative power source, a second current-stabilizing two-terminal device connected between the emitter of the second transistor and the negative power supply bus, The first and second current dividers, the third and fourth transistors, the second resistor, the input of the first current divider connected to the collector of the first transistor, the input of the second current divider connected to the collector of the second transistor, the first output of the first current divider connected to the collector of the fourth transistor and is the first current the output of the device, the first output of the second current divider is connected to the collector of the third transistor and is the second current output of the device, the second resistor is connected between the emitters of the third and even transistors, the base of the third and fourth transistors are connected and connected to a bias source, the second output of the first current divider is connected to the emitter of the third transistor, and the second output of the second current divider is connected to the emitter of the fourth transistor.

The inventive PNT (figure 2) contains the first transistor 1, the base of which is the first input of the device, the second transistor 2, the base of which is the second input of the device, the first resistor 3 connected between the emitters of the first transistor 1 and the second transistor 2, the first current-stabilizing two-terminal 4, connected between the emitter of the first transistor 1 and the bus of the negative power supply, the second current-stabilizing two-terminal 5 connected between the emitter of the second transistor 2 and the bus of the negative power source, first a current divider 6, the input of which is connected to the collector of the first transistor 1, a second current divider 7, whose input is connected to the collector of the second transistor 2, and the first output to the collector of the third transistor 8 and is the second current output of the device, the collector of the fourth transistor 9 is connected to the first output the first current divider 6 and is the first current output of the device, the base of the third transistor 8 and the fourth transistor 9 are connected and connected to a bias source, the second output of the first current divider 6 is connected to the emitter the third transistor 8, and the second output of the second current divider 7 to the emitter of the fourth transistor 9, the second resistor 10 is connected between the emitters of the third transistor 8 and the fourth transistor 9.

, где ΔU_БЭ - разность напряжений база-эмиттер третьего транзистора 8 и четвертого транзистора 9, a R_K - сопротивление второго резистора 10, результирующее выражение можно представить в виде:The work of the proposed PNT can be explained as follows. The primary conversion of the input voltage to the output current is carried out using the first transistor 1, the second transistor 2 and the first resistor 3. The current at the first current output I _OUT.1 will be composed of the components I _{0 of the} current of the stabilizing two-terminal network, the current increment I _X , due to the presence of the input voltage on the bases of transistors 1 and 2, current I ₂ = (I ₀ -I _X ) · K + I _K , and it can be shown that

where ΔU _BE is the voltage difference between the base-emitter of the third transistor 8 and the fourth transistor 9, and R _K is the resistance of the second resistor 10, the resulting expression can be represented as:

where K is the division coefficient in the current divider DT.

Obviously, the collector current of the first transistor 1 will be described in the same expression as the current at the first current output of the prototype. This expression can be represented as:

where U _X is the voltage at the input of the device;

R ₀ is the resistance of the first resistor 3;

α≈1 is the emitter current transfer coefficient of the used transistors;

r _E = φ _T / I ₀ - differential resistance of the emitter of the first transistor 1; φ _T is the temperature potential.

Since the shoulders of the device are symmetrical, the current at the second current output of the device has the same components as the current at the first current output, but with different signs:

The current increment I _x can be represented as follows:

where φ _T is the temperature potential.

The compensating current I _K can be described by the following expression:

where R _K is the resistance of the second resistor 10.

It can be shown that I ₀ -I _K ≫I _K , then (5) takes the form:

The resulting PNT output current equal to the difference of the currents of the first and second outputs can be represented as:

Substituting expressions (4) and (6) in (7), we obtain:

From the expression (8) it is seen that to obtain the minimum deviation from linearity, the following conditions must be met:

therefore, the value of the second resistor 10 depends on the resistance of the first resistor 3:

Actually, taking into account the volume resistances of the bases of transistors and the influence of the dependence of the emitter current transfer coefficient on the emitter current, the expression is more complex, but in a first approximation, expression (9) shows that the effect of compensating the nonlinearity of the voltage-current conversion is present.

To confirm the analysis, the simulation results in Pspice are presented. A variant of the circuitry implementation of the proposed PNT is shown in figure 3.

Parts of the circuit diagram, enclosed in dashed rectangles, are a special case of the implementation of current dividers DT.

Figure 4 shows the schematic diagrams of the implementation of the claimed PNT and the prototype, for the convenience of comparing the simulation results combined in one file with common power sources and stimulating input signal.

In the left part of the circuit diagram in figure 4 shows the inventive voltage-current converter, in the right part is a prototype of the invention. Resistors R3, R4, R22 and R23 are used as current sensors on the current outputs of the claimed PNT and prototype. Global nodes X1 and X2 represent the inputs of the claimed PNT, and X11 and X12 represent the inputs of the prototype. As transistors, the models of active components GC_05_NPN, which are part of ABMK 1.2 [Dvornikov O.V., Chekhovskoy V.A. Analog bipolar-field BMK with advanced functionality // Chip News, No. 2, 1999. - p.21-23], produced by the NGO "Integral" (Minsk).

The work of current dividers is based on the inequality of the areas of the transistors included in them: let s _i be the emitter area of the corresponding transistor, then

where K is the current division ratio in the divider, which is included in the above relations.

Currents I ₀ in the schemes of the prototype and the claimed PNT are the same.

Figure 5 shows graphs of the relative deviations from the linear transformation of the voltage - current normalized slope ΔI _∑ / ΔU _VX for the prototype circuit and the claimed PNT, which is done for clarity of the results. The expression describing the graphs shown in figure 5, can be represented as:

The expression in parentheses is multiplied by 100% to more clearly display the simulation results, since the deviation from the linear voltage-current conversion for the prototype circuit does not exceed 1%.

), - нормированная крутизна преобразования напряжение - ток для схемы заявляемого ПНТ. В диапазоне изменения входного напряжения от -1В до 1В выигрыш в отклонении от линейного преобразования составляет более 30 раз: 0,023% у заявляемого ПНТ против 0,753% у схемы прототипа. Следует отметить, что в процессе проведения параметрической оптимизации необходимо добиваться одинаковых значений отклонения на краях диапазона входного напряжения и в точке, соответствующей значению входного напряжения, равного 0 В. В этом случае отклонение от линейного преобразования будет минимальным. Получение минимального отклонения от линейного преобразования заявляемого ПНТ достигается изменением значения компенсирующего резистора R_K.The curve marked with a sign (◇) (Fig. 5) is the normalized slope of the voltage-current conversion for the prototype circuit, the curve marked with a sign (

), is the normalized slope of the voltage-current conversion for the circuit of the claimed PNT. In the range of input voltage from -1V to 1V, the gain in deviation from linear conversion is more than 30 times: 0.023% for the claimed PNT against 0.753% for the prototype circuit. It should be noted that in the process of parametric optimization, it is necessary to achieve the same deviation values at the edges of the input voltage range and at a point corresponding to the input voltage value of 0 V. In this case, the deviation from the linear transformation will be minimal. Obtaining a minimum deviation from the linear transformation of the claimed PNT is achieved by changing the value of the compensating resistor R _K.

Thus, the analysis and the results of circuit simulation show that the claimed technical result is achieved - increasing the linearity of the current-voltage converter.

Claims (1)

Voltage converter is a current containing the first transistor, the base of which is the first input of the device, the second transistor, the base of which is the second input of the device, the first resistor connected between the emitters of the first and second transistors, the first current-stabilizing two-terminal connected between the emitter of the first transistor and the negative source bus power supply, a second current-stabilizing two-terminal device connected between the emitter of the second transistor and the negative power supply bus, characterized in that the first and second current dividers, the third and fourth transistors, the second resistor are introduced into the device, the input of the first current divider connected to the collector of the first transistor, the input of the second current divider connected to the collector of the second transistor, the first output of the first current divider connected to the collector of the fourth transistor and is the first current output of the device, the first output of the second current divider is connected to the collector of the third transistor and is the second current output of the device, the second resistor is connected between em itters of the third and fourth transistors, the base of the third and fourth transistors are connected and connected to a bias source, the second output of the first current divider is connected to the emitter of the third transistor, and the second output of the second current divider is connected to the emitter of the fourth transistor.

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