RU2261469C1 - Accumulation-type adder - Google Patents

Abstract

FIELD: computer science.

SUBSTANCE: device has in each digit one RS trigger, eight AND elements, five OR elements, two NOT elements, nine control buses.

EFFECT: lower costs, higher speed of operation, broader functional capabilities, higher efficiency.

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Description

The invention relates to the field of digital computing and can be used in computer processing devices and digital automation devices.

The accumulative type adders (hereinafter referred to as the object) are known, made on the basis of three types of logical elements (LE) AND, OR, NOT (see, for example, the book by MA Kartsev. Arithmetic of digital machines. M., Science, 1969, p. 247, 288; AS No. 911517, class G 06 F 7/50).

The disadvantage of this object is the presence of three RS-registers, which increases hardware costs, power consumption, and a slight decrease in performance.

The closest adopted for the prototype is the object as. No. 538365.

A known object cannot be used in devices that perform multiplication operations, because does not perform elementary operations (EO) shift codes in the direction of the lower and upper digits. The named object contains two RS-flip-flops in each binary digit, which is its drawback.

The objective of the invention is to reduce equipment, improve performance and expand the list of operations (code shift to the left, code shift to the right).

For this purpose, an object is proposed that contains one RS type trigger in each discharge, the installation inputs of which are connected to the outputs of the first and second AND elements, the first inputs of which are combined and connected to the output of the first OR element, the output of the second OR element is connected to the second input of the second AND element through the first element is NOT connected to the second input of the first AND element, whose output through the second element is NOT connected to the input of the third AND element, the second and third inputs of which are connected to the zero output of the trigger and the first bus is controlled II, the output of the said AND element is connected to the first input of the second OR element, its second input is connected to the "single" input of the trigger, and the third input is connected to the second control bus, the output of the fourth AND element is connected to the input of the first OR element, the first and second inputs of which connected to the transfer bus from the low order and the third control bus; also containing a group of AND-OR elements for receiving the code into the adder and a group of OR-AND elements for generating transfer signals to the high order, DIFFERENT in that the first inputs of the fifth and sixth elements AND are connected to the fourth and fifth control buses, the second inputs of these elements are connected to numerical reception buses of direct and inverse codes, respectively, and the outputs of the mentioned AND elements are connected to the inputs of the third OR element, the output of which is connected to the input of the first and fourth OR elements; the second input of the fourth OR element is connected to the output of the seventh AND element, and the third input is connected to the output of the first element NOT; the first input of the fifth OR element is connected to the zero input of the trigger, its second input is connected to the second input of the fourth OR element, and the third input is connected to the transfer bus from the least significant bit and the input of the fourth AND element; the outputs of the fourth and fifth logic gates And are connected to the first and third inputs of the seventh element And, the second input of this element is connected to the sixth control bus, and its output is a transfer bus to the senior bit, in addition, the eighth element And, the first input of which is connected to by the trigger output of the highest order, the second input is connected to the output of the second element NOT, and its third input is connected to the seventh control bus, the output of the mentioned AND element is connected to the fourth input of the second OR element; the eighth control bus is connected to the third input of the first OR element, and the ninth control bus is connected to the fourth input of the second OR element.

The proposed object allows you to build each bit of the object on the basis of only one RS-trigger, at the same time performing the EO of receiving the second term, the first addition modulo two, generating and memorizing the transfer signal, which increases the speed of arithmetic operations. EO is provided for shifting the code in the direction of lower and higher bits and inverting the register code with minimal hardware costs, i.e. expand the functionality of the object. In addition, electricity consumption is reduced by about one and a half times.

We note the main distinguishing features and what they allow to obtain:

1. The connection of the output of the third OR element with the input of the fourth and first OR elements provides the formation of the transfer and invert the code of the first trigger;

2. The connection of the output of the seventh AND element with the second input of the fourth and fifth OR elements provides for “storage” of the transfer signal generated in this category, which makes it possible to exclude the register for storing the second term from the equipment;

3. Connecting the sixth bus to the second input of the seventh element And allows you to quench the transfer potentials simultaneously in all discharges of the object after performing the second addition modulo two;

4. Connecting the inputs of the eighth element AND to the output of the second element NOT, to the "single" output of the high-order trigger and to the seventh control bus provides EO code shift towards the lower bits;

5. The connection of the output of the first element AND with the input of the fifth element OR provides the formation of the transfer in this category.

To explain the operation of the described object, Fig. 1 shows a functional diagram (one bit), and Fig. 2 shows timing diagrams of its operation.

The object contains RS-trigger 1, elements AND 2-9, elements OR 10-14, elements NOT 15, 16, information reception bus number 17, information reception bus inverse code number 18, transfer bus 19, blanking transfer bus 20, invert bus flip-flop 22 (potential), code shift bus 23 to the right, logic bus 24, code receive bus 25, inverse code receive bus 26, modulo two (second) add bus 27, trigger invert bus 28 (pulse), trigger zero bus 29.

The proposed object works as follows.

Addition operation. In the initial state, the code of the first term is stored in the adder register (triggers 1). The code of the second term is received via the information bus 17. To carry out the operation, high potentials are supplied to the control buses 20 and 22, which retain their value during the whole operation (t1, t2, t3). According to the first time cycle (t1), an executive pulse is supplied to bus 25. If on the bus 17 there is a potential corresponding to the unit code, then the executive pulse on the bus AND 2, OR 13, 14 will go to the first inputs of the elements And 6, 7. At the same time, the same pulse will go to the first input OR 11. If before the arrival of t1 in the trigger If the “zero” code was stored, then high potentials from the “zero” output of the trigger and from the output of HE 15 will arrive at the inputs of And 8 and will develop a potential that from the output of And 8 through OR 12 will allow t1 to pass through And 7 to the “single” trigger input 1. The mentioned trigger will be set to “unit”, ie his condition will be inverted. At the same time, t1 from the “single” input of the trigger will go to the input of OR 12 and will support the passage of the pulse to the single input during the duration of the executive pulse. At time t1, if transfer from the low order was received on bus 19, signals from the outputs OR 10, 11 will go to inputs AND 5, which will generate a transfer signal to the high order. This signal will be “stored” until the end of the operation due to communication from the output AND 5 with the input OR 10, 11. If the code “unit” was stored in trigger 1 before t1 arrived, then from the output And 8, through OR 12 to the inputs And 7, HE 16 will not receive a potential allowing the operation of AND 7. At the same time, a high potential from the output of HE 16 will allow t1 to pass to the "zero" input of trigger 1. The trigger will be set to "zero", i.e. his condition will be inverted. At the same time, t1 through HE 15 will prohibit the operation of AND 8 for the duration of the executive pulse and, passing along the OR 10, AND 5 circuit, will generate a transfer signal to the high order. A transfer signal to the high order will also be generated if there is no high potential on the bus 17, and a transfer signal has arrived from the low order on the bus 19. At the same time, the high potential from the output of HE 16 through OR 11 together with the potential of the transfer bus 19 will generate a transfer signal to the high order.

At t2, the propagation of transport signals from the lower digits to the higher digits continues.

By t3, the second addition is performed modulo the two results of the first addition with the carry signal. To perform this EO, an executive pulse is supplied to bus 27. If a transfer signal was received at the And 4 input to the discharge of the adder via bus 19, then the pulse passes through the And 4, OR 14 circuit to the inputs of And 6,7 elements. This pulse inverts trigger 1. On this, in fact, the addition operation ends, but in order to prepare the object for the new addition operation, it is necessary to “extinguish” the transfer potentials by applying the corresponding impulse to bus 20 (Figure 2, a).

The subtraction operation is performed similarly to the addition operation. The difference is that on t1 the inverse code of the number is received into the device. To do this, the actuating pulse is fed to bus 26. The actuating pulse passes through the AND 3, OR 13,14 circuit to the inputs And 6, 7.

The elementary operation of shifting the code to the side of the least significant bits is performed in one time cycle t1 by one bit. To perform an EO code shift, a control potential is supplied to bus 23, and an executive pulse is supplied to bus 28, which, through a chain of OR 14, is supplied to the first inputs of elements And 6, 7. If from the highest bit on bus 21 to input And 9 of the i-th category the potential of "unit" comes in, and from the output of NOT 15 to the second input of the And element also receives a high potential, then from the output of the And 9 element through the OR elements 12, And 7, an actuating pulse will arrive at the "single" input and set trigger 1 to "unit" . If the “zero” code is stored in the object’s highest level, then there will be no high potential at the And 12 output, and a high potential will come from the output of NOT 16 to the And 6 input, allowing the Executive pulse to pass through And 6 to the zero input of trigger 1. Thus, in one time cycle, the code will be shifted by one bit in the direction of the least significant bits (to the right). Upon completion of the shifts from the tires 22, 23, the control potential is removed (Figure 2, b).

The EO of shifting the code toward the higher digits (normalization, multiplying the code by 2, 4, 8, etc.) is performed in four time cycles by one bit. The actuating pulse t1 is supplied to bus 28 and, through OR 14, is supplied to the first input AND 6. The second potential of the element AND is output from the output of the element HE 16 with a high potential if the “unit” code is stored in trigger 1. If there are signals at all three inputs of the And 5 element, a transfer signal to the high order is generated at its output. This signal is "remembered" (fixed) due to the connection of the output AND 5 with the inputs OR 10, 11.

By t2, the triggers 1 of the object are set to "zero" due to the supply of an impulse to the bus 29.

By t3, the code is actually shifted to the left by one bit. To perform this EO, a control potential is supplied to the bus 27, which is fed to the second input And 7 through the OR 12 circuit, and an executive pulse is supplied to the bus 27. This pulse, in the case of the presence of a transfer signal from the least significant bit on bus 19, along the AND 4, OR 14, AND 7 circuit will go to the “single” input of trigger 1 and set it to “one”. EO completed.

At t4, an auxiliary EO of hyphenation is performed, which prepares the object for the next EO. For its implementation, high potential is removed from the bus 20, which prohibits the passage of signals through AND 5. Thus, the carry signals are suppressed in all bits of the object at the same time (Figure 2, c).

The EO of inverting the code stored in triggers 1 is performed in one time cycle t1. For its implementation, a control potential is supplied to the bus 22, and an executive pulse is supplied to the bus 28. If trigger 1 stores the “zero” code, a high potential from the “zero” output through the AND 8, OR 12 elements will go to the first input of the AND 7 element and allow the executive pulse to pass through the OR 14, AND 7 circuit to the “single” input of trigger 1 . If the trigger is stored in the code "unit", then from the output of the element NOT 16 to the first input And 6 will receive a high potential and allow the passage of the Executive pulse to the "zero" input of trigger 1 (Figure 2, g).

Logical addition EO is performed in one time cycle. The code of the first term is stored in trigger 1, the code of the second term is sent via bus 17. The control potential is applied to bus 24, and the executive pulse is applied to bus 25, which is fed to the “single” input via the AND 2, OR 13, 14, AND 7 circuit trigger, if in this category on the bus 17 there is a signal corresponding to the code "unit". The operation is completed (Figure 2, d).

EO logical multiplication is performed in one time cycle. Prior to starting the EO, the first factor is stored in triggers 1. The second factor is received from the information bus 18 in the inverse code. The executive pulse along the AND 3, OR 13, 14, AND 6 circuit passes to the "zero" input of the trigger and sets it to the "zero" state if there is a high potential on bus 18 corresponding to the inverse value of the code of the second factor. The operation is completed.

EO addition modulo two is considered in detail when describing the operation of an object to perform an addition operation.

Thus, the proposed object can improve the performance of operations of addition (subtraction) compared with the prototype in the optimal mode of operation by approximately 20%. (The optimal operating mode assumes t _and = t _n ; T _{lane max} = 2t _and , here t _and is the duration of the actuating pulse; t _n is the duration of the pause between the executive pulses; T _lane is the maximum propagation time of the transfer signal.)

The list of performed EOs is also expanding: the object performs additional operations of left shift (normalization, multiplication by 2, 4, 8, etc.) and right shift (division by 2, 4, 8, etc.). In addition, a certain reduction in energy consumption is achieved due to the exclusion of one trigger register from the equipment.

Claims (1)

The accumulator of the accumulating type, containing in each category one RS-trigger, the first, second, third, fourth, fifth, sixth and seventh elements AND, the first, second, third, fourth and fifth elements OR, the first and second elements NOT, the first, second and a third control bus, the installation inputs of the RS flip-flop connected to the outputs of the first and second AND elements, the first inputs of which are combined and connected to the output of the first OR element, the output of the second OR element is connected to the second input of the second AND element and is NOT connected to the first element second the first input of the first AND element, whose output through the second element is NOT connected to the input of the third AND element, the second and third inputs of which are connected to the zero output of the trigger and the first control bus, the output of the said AND element is connected to the first input of the second OR element, its second input is connected with a "single" trigger input, and the third input is connected to the second control bus; the output of the fourth element AND is connected to the input of the first OR element, the first and second inputs of which are connected to the transfer bus from the least significant bit and the third control bus, respectively, characterized in that the first inputs of the fifth and sixth elements AND are connected to the fourth and fifth control buses, second inputs of these elements are connected to the numerical reception buses of direct and inverse codes, respectively, and the outputs of the mentioned elements AND are connected to the inputs of the third OR element, the output of which is connected to the input of the first and fourth elements ntov OR; the second input of the fourth OR element is connected to the output of the seventh AND element, and the third input is connected to the output of the first element NOT; the first input of the fifth OR element is connected to the zero input of the trigger, its second input is connected to the second input of the fourth OR element, and the third input is connected to the transfer bus from the least significant bit and the input of the fourth AND element; the outputs of the fourth and fifth logical elements OR are connected to the first and third inputs of the seventh AND element, the second input of this element is connected to the sixth control bus, and its output is a transfer bus to the senior bit, in addition, the eighth element And, the first input of which is connected to "single" high-order trigger output, the second input is connected to the output of the second element NOT, and its third input is connected to the seventh control bus, the output of the mentioned AND element is connected to the fourth input of the second OR element; the eighth control bus is connected to the third input of the first OR element.

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