RU2119716C1 - Synchronous flip-flop cell - Google Patents

Abstract

FIELD: digital microelectronics; emitter-coupled logic integrated circuits. SUBSTANCE: newly introduced in cell are first and second pairs of controlled transistors. Emitters of transistors of main and additional flip-flops are combined. Leads of first and second resistors are connected to plus terminal of voltage supply. Other leads function as direct and inverted sync outputs of cell. Bases of first and second control transistors are combined and function as direct and inverted sync inputs of cell. Combined collectors of first and second transistors of additional flip-flop function as direct output of cell. Combined collectors of third and fourth transistors of additional flip- flop function as inverted output of cell. Input levels of sync signals and output logic levels of data signals of synchronous flip-flop cell are matched which is required for setting up stages of such circuits. EFFECT: reduced number of current supplies, reduced power requirement, improved reliability of circuit. 2 dwg

Description

 The proposal relates to digital microelectronics, in particular to devices of pulsed technology with bipolar transistors, and can be used in digital microcircuits built on elements of emitter-coupled logic (ESL).

 Synchronous trigger cells are known whose purpose is to reduce the likelihood of error states being transmitted from one pair of transistors with cross-connections to another pair of transistors. These pairs are driven by an alternately switched current source. They are connected into a ring structure by data transistors, which are controlled by the same output signals of the current source. (EP, application 0153788, A1, CL H 03 K 23/52, 1986).

 When this circuit is connected in cascades, the output logic levels of each previous cell and the input clock levels of the subsequent cell are not consistent with each other, which makes it difficult to connect them to cascades, for example, when operating in counting mode.

 To match the levels, additional elements are used, such as emitter followers or current switches. Such elements require additional current sources and supply of additional electric power.

 Closest to the technical nature of the claimed is a synchronous trigger cell containing the primary and secondary triggers, each of which contains transistors and resistors, a current source, resistors (JP, application 60-38055, A, class H 03 K 23/50, 1985 )

 The known circuit is structurally complex, if it is necessary to build a cascade of circuits for matching input and output levels, it requires an additional current switch with an additional current source.

 The technical result of the proposal is to ensure coordination of the input levels of the clock signals and the output logic levels of the synchronous trigger cell, which is necessary when constructing cascades from such circuits, while reducing the number of current sources and power consumption.

 The proposed synchronous trigger cell contains, in comparison with the prototype, a smaller number of elements, which generally increases the reliability of the work.

 The technical result is achieved by the fact that in the synchronous trigger cell containing the primary and secondary triggers, each of which contains transistors and resistors, a current source and resistors, the first and second pairs of control transistors are introduced, the emitters of the transistors of the primary and secondary triggers are combined and connected to the positive terminal a current source, one of the terminals of the first and second resistors is connected to the positive terminal of the power supply, the other terminal of each of which is combined with the collector The switches of the same name control transistors of the pair are respectively the direct and inverse clock outputs of the cell, the bases of the first and second control transistors of each pair are combined and are respectively the direct and inverse clock inputs of the cell, in each of the triggers the collectors of the first and second transistors are connected to the base of the third transistor and through the corresponding resistor connected to the emitter of the first control transistor of the corresponding pair of control transistors, the collectors of the third and fourth transistor the ditches are connected to the base of the second transistor and connected through the corresponding resistor to the emitter of the second control transistor of the corresponding pair of control transistors, the bases of the first and fourth transistors of the main trigger are the direct and inverse information inputs of the cell, the combined collectors of the third and fourth transistors of the main trigger are connected to the base of the first transistor additional trigger, the base of the fourth transistor of the additional trigger is connected to the base of the third o transistors of the main trigger, the combined collectors of the first and second transistors of the additional trigger are direct, and the combined collectors of the third and fourth transistors of the additional trigger are respectively the inverse outputs of the cell.

 In FIG. 1 shows a schematic diagram of the proposed synchronous trigger cell, FIG. Figure 2 shows the use of the indicated cell in the frequency divider.

The proposed synchronous trigger cell contains a main trigger, consisting of four transistors T ₅ -T ₈ and resistors R ₃ and R ₄ and an additional trigger, consisting of transistors T ₉ - T ₁₂ and resistors R ₅ and R ₆ .

 The definitions of "primary and secondary triggers" are conditional in principle and indicate only that the primary trigger is the master, information signals are supplied to it, and the secondary trigger, it is triggered by the primary trigger. However, the terms "primary and secondary triggers" are generally accepted in the art, therefore, for ease of description of the work, generally accepted terminology is left.

The cell also contains two pairs of control transistors T ₁ and T ₂ ; T ₃ and T ₄ , the first R ₁ and second R ₂ resistors and current source 9, the negative terminal of the supply voltage is indicated - E _n , its positive terminal + E _n , direct 1 and inverse 2 clock inputs of the cell, direct 3 and inverse 4 information cell inputs, direct 5 and inverse 6 information outputs of the cell, direct 7 and inverse 8 clock outputs of the cell, the positive terminal of the current source 9 is indicated by the symbol "+" in the drawing.

For simplicity of description of triggers of a trigger cell T ₅ , T ₆ , T ₇ and T _{8, the} transistors of the main trigger are assigned the names of the first, second, third and fourth transistors, respectively. T ₉ , T ₁₀ , T ₁₁ and T ₁₂ transistors of the additional trigger are assigned the names of the first, second, third and fourth transistors of the additional trigger. The control transistors T ₁ and T _{3 of the} first and second pairs of control transistors are called "first control transistors of the first and second pairs, respectively", T ₂ and T ₄ are "second control transistors of the first and second pairs of control transistors, respectively." In the second embodiment (Fig. 2) for the case of using the circuit as a frequency divider, the input 3 of the cell is combined with output 6, the base of transistor T _{10 of the} additional trigger is connected to the base of transistor T _{8 of the} main trigger and combined with output 5.

 The device operates as follows (Fig. 1).

When a direct clock signal is input to input 1 of a synchronous trigger cell (base of control transistors T ₁ and T _{2 of the} first pair) and an inverse clock signal to input 2 (base of control transistors T ₃ and T _{4 of the} second pair), a different bias voltage is generated on the main one (T ₅ - T ₈ ) and optional (T ₉ - T ₁₂ ) triggers.

At the same time, information signals are supplied to the information inputs of cells 3 and 4 for subsequent conversion by their circuit. These signals are transmitted from the main trigger through an additional to the cell outputs by generating a bias voltage on the emitters of the control transistors of pairs T ₁ , T ₂ and T ₃ , T ₄ , respectively connected transistor T ₁ through resistor R ₃ , transistor T ₂ through resistor R ₄ , transistor T ₃ through resistor R ₅ , transistor T ₄ through resistor R ₆ with the combined collectors of the respective transistors of the primary and secondary triggers. The bias voltage on the emitters T ₁ -T _{4 is} formed by applying a direct and inverse clock signal to input 1 and input 2 of the cell, as described above, while the collectors of the control transistors T ₁ and T _{3 are} connected to the positive terminal of the current source + E _n through the resistor R ₁ , and the collectors of the control transistors T ₂ and T ₄ through the resistor R ₂ .

At each operation cycle, switching the main trigger (T ₅ -T ₈ ) initiates the switching of the additional trigger (T ₉ - T ₁₂ ), while since the output information signals taken from the collectors of the transistors T ₁₀ and T _{12 of the} additional trigger are controlled by the emitter of the control transistor T ₃ through a resistor R ₅ or through a circuit controlled by an emitter of a control transistor T ₄ through a resistor R ₆ , then the output information signals at output 5 and output 6, respectively, will be matched in levels with the information input signals. It should be noted that the levels of clock signals and infomation signals (both direct and inverse) are offset relative to each other by the magnitude of the emitter-base voltage of the control transistors.

When using the proposed cell as a frequency divider (Fig. 2), the base of the transistor T _{5 of the} main trigger is connected to the output σ of the cell, the base of the transistor T _{8 is} connected to the output 5 of the cell and the circuit starts working as a counter with matched outputs, while connecting similar cells to a circuit along the sync outputs with sync inputs of the next cell, and circuits of the frequency divider with a given power consumption can be formed along the information outputs with its information inputs.

Claims (1)

 Synchronous trigger cell containing the primary and secondary triggers, each of which contains transistors and resistors, a current source and resistors, characterized in that the first and second pairs of control transistors are introduced into the cell, the emitters of the transistors of the primary and secondary triggers are combined and connected to the positive terminal of the source current, some conclusions of the first and second resistors are connected to the positive terminal of the power supply source, the other terminal of each of which is combined with collectors of the same name control transistors of pairs and is respectively the direct and inverse clock outputs of the cell, the bases of the first and second control transistors of each pair are combined and are respectively the direct and inverse clock inputs of the cell, in each of the triggers the collectors of the first and second transistors are connected to the base of the third transistor and through the corresponding resistor - with the emitter of the first control transistor of the corresponding pair of control transistors, the collectors of the third and fourth transistors are connected to the base in of the second transistor and through the corresponding resistor - with the emitter of the second control transistor of the corresponding pair of control transistors, the bases of the first and fourth transistors of the main trigger are respectively the direct and inverse information inputs of the cell, the combined collectors of the third and fourth transistors of the main trigger are connected to the base of the first transistor of the additional trigger, the base the fourth transistor of the additional trigger is connected to the base of the third transistor of the main trigger , the combined collectors of the first and second transistors of the additional trigger are direct, and the combined collectors of its third and fourth transistors are respectively the inverse outputs of the cell.

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