RU2117326C1 - Computing system based on matrix of processor elements - Google Patents

Abstract

FIELD: computer engineering, in particular, digital image processing. SUBSTANCE: device has base computer, three memory units, input-output controller, commutator, control unit, unit for setting and checking clock frequency, buffer unit and computing unit which is designed as matrix of processor elements. This results in possibility of parallel processing of heterogeneous and uniform information. Arithmetic and logical processing runs in orthogonal direction with exchange of orthogonal information flows without additional operations. EFFECT: increased speed. 12 dwg, 6 tbl

Description

 The invention relates to computing and can be used to build computing tools that require high-performance information processing, for example, for digital image processing.

 A device for processing a digital signal is known, containing arithmetic units connected in series, combined into two groups of calculators (patent, RF N 2033637, class G 06 F 17/14, 09.07.91).

 The device provides the possibility of parallel processing of information flows, however, its use is limited by the possibility of unidirectional exchange of information.

 The closest analogue prototype is a computing system containing a control (base) computer, memory blocks, an input-output controller, computing blocks and switches, groups of control and information outputs of which are connected to the inputs of the corresponding memory blocks (RF patent, N 2042193, cl. G 06 F 15/16, 08/10/91).

 This computing system has wide functionality due to the increase in the number of groups of computing units working simultaneously on the common bus and the organization of their interaction, however, it requires intermediate operations related to forwarding and restarting teams, which reduces the system’s speed.

 The essence of the invention lies in the fact that in a computing system containing a base computer, memory blocks, an input / output controller, a computing unit and a switch, the first and second groups of control outputs of which are connected to the first groups of control inputs of the first and second memory blocks, respectively, and the first and the second groups of information inputs / outputs of the switch are connected to the groups of information inputs and outputs of the first and second memory blocks, respectively, a control unit, a clock setting and control unit are introduced th frequency and a buffer unit, the group of control inputs and outputs of the base computer connected to the first groups of control inputs and outputs of the control unit and the third memory block, the group of information inputs and outputs of the base computer connected to the group of information inputs and outputs of the third memory block and the third group information inputs and outputs of the switch, and the group of address outputs of the base computer is connected to the first groups of address inputs of the third memory block and the controller an ode-output, the first, second and third groups of address outputs of which are connected to the groups of address inputs of the buffer unit and the first and second memory blocks, the first group of control outputs and the group of address outputs of the control unit are connected to the second groups of address and control inputs of the third memory block, respectively the group of information outputs of which is connected to the groups of information inputs of the control unit and the input-output controller, the group of control outputs of which is connected to the first group branching inputs of the switch, the second group of control inputs of which are connected to the second group of control outputs of the control unit, and the group of control inputs and outputs of the control unit is connected to the group of control inputs and outputs of the I / O controller, and the third group of control outputs of the control unit is connected to the group of control inputs a buffer unit, the group of information input-output of which is connected to the fourth group of information input-output of the switch, while the group of information, address x and the control outputs of the buffer unit are connected respectively to the groups of information, address and control inputs of the computing unit, the first group of information outputs of which are connected to the group of information inputs of the buffer unit, the first group of outputs of the reference and control unit of the clock frequency is connected to the groups of clock inputs of the I / O controller , a control unit and a computing unit, the second group of information outputs of which are connected to the group of inputs of the unit of reference and control the clock frequency, Torah group of outputs coupled to a group of control inputs of the control unit, data input connected to a corresponding output of the computer unit, wherein the host computer output coupled to the control input setting unit and the control clock frequency, and the computing unit is configured as a matrix of processing elements.

 Such a computing system (hereinafter, the NBMPE system) provides the possibility of parallel processing of homogeneous and heterogeneous information. In this case, arithmetic-logical processing and information exchange and transmission processes are also carried out in orthogonal directions with the exchange between information flows of orthogonal directions without carrying out intermediate operations, which significantly improves performance.

 In FIG. 1 shows a block diagram of the NBMPE system; in FIG. 2-12 are functional diagrams of the execution of individual blocks and devices included in these blocks.

 In the table. 1 shows information on the mutual connections of the processor elements of the computing unit, in table. 2 shows the program-accessible blocks and nodes of the NBMPE system, in table. Figure 3 shows the list of conventions used in the description of the teams in table. 4 and 5, the composition of the commands included in the groups of commands of the control unit and the computing unit, respectively, is shown in Table. 6 shows the address decoding.

 The NBMPE system (Fig. 1) includes a base computer 1, made in the form, for example, of an IBM PC computer (386 series) and designed to enter information flows, dispatch them and output processed information, and memory blocks 2-4, made in the form of operational memory devices (RAM) and designed accordingly: block 2 - for storing programs, blocks 3 and 4 - for storing data.

 In this case, block 2 is made on a dual-port memory chip IDT7026S, and blocks 3 and 4 are made on an MT5LC512K8D4 chip.

 The NBMPE system also contains a switch 5, designed for simultaneous and independent connection of information and address inputs of blocks, a control unit 6, designed to generate control commands and provide the exchange of control interrupt codes with the host computer 1, an input / output controller 7, designed to generate signals control, computing unit 8, made in the form of a two-dimensional array of processor elements (PE) that implements SIMD - architecture, and intended for arithmetic ICo-logical processing, exchange and transmission of information, a buffer unit 9, designed to implement the data exchange procedure between the computing unit 8 and the system units, as well as a task and control unit 10 of the clock frequency, designed to generate a single working clock frequency and control the output frequencies of the elements computing unit 8.

 The first and second groups of control outputs of the switch 5 are connected by buses 11 and 12 with the first groups of control inputs of the memory blocks 3 and 4, respectively, and the first and second groups of information inputs and outputs of the switch 5 are connected by buses 13 and 14 to the groups of information inputs and outputs of the blocks 3 and 4 memories.

 The group of control inputs and outputs of the base computer 1 bus 15 is connected to the first groups of control inputs, respectively, of the control unit 7 and the memory unit 2, the group of information inputs and outputs of the base computer 1 is connected by bus 16 to the group of information inputs and outputs of the memory unit 2 and the third group of information inputs - outputs of the switch 5, and the group of address outputs of the base computer 1 bus 17 is connected to the first groups of address inputs, respectively, of the memory unit 2 and the controller 7 input-output.

 The first, second and third groups of address outputs of the I / O controller 7 are connected by buses 18-20 to the groups of address inputs of the buffer block 9 and memory blocks 3 and 4, respectively.

 The first group of control outputs of the control unit 6 of the bus 21 and address buses 22 is connected to the second groups of address and control inputs of the memory unit 2, respectively, the group of information inputs / outputs of which bus 23 is connected to the groups of information inputs of the control unit 6 and the input-output controller 7, respectively.

 The group of control outputs of the input-output controller 7 by bus 24 is connected to the first group of control inputs of the switch 5, the second group of control inputs of which bus 25 is connected to the second group of control outputs of the control unit 6.

 The group of control inputs and outputs of the bus control unit 6 is connected to the group of control inputs and outputs of the I / O controller 7, and the group of control outputs of the bus control unit 6 is connected to the group of control inputs of the buffer unit 9, the information input-output group of which is connected by bus 28 with the fourth group of information inputs / outputs of the switch 5.

 Groups of information, address and control outputs of the buffer unit 9 via buses 29 and 30, 31 are connected respectively to groups of information, address and control inputs of the computing unit 8, the group of information outputs of which is connected by bus 32 to the second group of information inputs of the buffer unit 9.

 The group of outputs of the clock setting and control unit 10 of the bus 33 is connected to the group of clock inputs of the input / output controller 7, the control unit 6 and the computing unit 8. The group of outputs of which bus 34 is connected to the group of inputs of the clock setting and control unit 10, a group of outputs connected a bus 35 with a group of control inputs of the control unit 6, an information input connected to the corresponding output of the computing unit 8. while the base computer 1 is connected to the control input of the task unit 10 and Rola clock.

 The switch 5 (Fig. 2) contains a control unit 36, a data switching unit 37, including eight parallel-connected switching cells 38 and an address switching unit 39.

 The control unit 36 of the group of inputs is connected to the group of control outputs of the switch 5 connected to the bus 25, the group of inputs is connected to the group of inputs of the block 37 of the data switch and is simultaneously connected to the control input of the block 39 of the address switching. The first, second, third and fourth input / output groups of the switching unit 37 are connected to the input / output groups of the switch 5 connected to the buses 13, 14, 16 and 28, respectively, the first and second input group of the address switching unit 39 are connected respectively to the groups of input of the switch 5 connected to the buses 24 and 25, and the first and second groups of outputs of the address switching unit 39 are connected to the output groups of the switch 5 connected to the buses 11 and 12 respectively. The switching cells 38 of the data switching unit 37 are connected with their first input-output to the first group of inputs and outputs of the data switching unit 37, are connected with their second input-output to the second group of inputs and outputs of the data switching unit 37, are connected to the third group of inputs and outputs of the data switching unit 37, and their fourth input-output connected to the fourth group of inputs / outputs connected to the group of inputs of the data switching unit 37, and the group of inputs connected to the group of control inputs of the data switching unit 37.

 The control unit 36 contains (Fig. 3) two multiplexers 40 (40.1-40.2), three inverters 41 (41.1-41.3), four elements AND 42 (42.1-42.4) and two elements OR 43 (43.1-43.2). The multiplexers 40 of the first and second inputs are connected to the corresponding inputs of the group of inputs of the control unit 36 connected to the inputs of the switch 5 connected to the bus 25. The third inputs of the multiplexers 40 are connected to the output of the first inverter 41.1, the input connected to the third input of the group of inputs of the control unit 36. This input is also connected to the first inputs of the parallel-connected elements And 42 included in the control unit 36. The second inputs of the And 42.1 and 42.3 elements are connected to the second input of the group of inputs of the control unit 36, and the second inputs of the And 42.2 and 42.4 elements are connected to the first input of the block input group 36 controls. The outputs of the first and second elements AND 42 (42.1 and 42.2) are connected respectively to the first and second inputs of the OR element 43.1, and the outputs of the third and fourth elements AND 42 (42.3 and 42.4) are connected respectively to the first and second inputs of the element OR 43.2.

 The outputs of the first and second elements OR 43, as well as the first, second and third inverters 41 are connected respectively to the first, second, third, fourth and fifth outputs of the control unit 36, and the inputs of the second and third inverters 41 (41.2 and 41.3) are connected respectively to the first and the second inputs of the input group of the control unit 36, and the outputs of the first and second multiplexers 40 are connected respectively to the outputs of the control unit 36 connected to the output groups of the switch 5. connected to the buses 11 and 12.

 Each i (in the given scheme i = 1, ..., 8), the switching cell 38 (Fig. 4) contains four multiplexers 44 (44.1.i-44.4.i), four three-static buffer elements 45 (45.1.i-45.4. i) and four buffer elements 46 (46.1. i-46.4. i). Here (Fig. 4), the circuit of the switching cell 38.i is shown for the switching cell 38.1 (for i = 1). The first and third multiplexers 44.1 and 44.3 are connected by their first and second address inputs to the outputs of the first and third buffer elements (46.1 and 46.3), and the second and fourth multiplexers (42.2 and 44.4) are connected to the outputs of the second and fourth buffer elements (46.2 and 46.4) respectively. The third control input of the multiplexers 44 is connected to the control input of the switching cell 38 (in the U5 circuit).

 The outputs of the first, second, third and fourth multiplexers 44 are connected to the first input of the corresponding tristatic buffer element (TBE) 45, the second input connected respectively of the first TBE (45.1) to the first input of the group of inputs, the second TBE (45.2) to the third input of the group of inputs, third TBE (45.3) to the second input of the group of inputs, and the fourth TBE (45.4) to the fourth input of the group of inputs of the cell 38 switching. The outputs of the TBE 45 are connected to the inputs and outputs of the first - first group, second - fourth group, third - second group, fourth - third group of inputs and outputs of the switching cell 38. The inputs of the buffer elements 46 are connected to the inputs and outputs of the first (46.1) - fourth group, the second (46.2) - the first group, the third (46.3) - the third group and the fourth (46.4) - the second group of inputs and outputs of the switching cell 38. In this case, the elements of the first switching cell (38.1) are connected to the first input-outputs of the corresponding input-output groups, the second switching cell (38.2) is connected to the second input-output of the input-output groups, etc.

 The address switching unit 39 (Fig. 5) contains two decoders / demultiplexers 47 (47.1 and 47.2), sixteen multiplexers 48 (48.1-48.16) and eighteen inverters 49 (49.1-49.18), while the inputs of the first and second inverters (49.1 and 49.2) ) are connected to the first group of inputs of the address switching unit 39 (bus 24), the outputs of the first eight multiplexers (48.1-48.8) are connected to the first group of outputs (bus 11), and the second eight multiplexers (48.9-48.16) to the second group of outputs of the block 39 switching addresses (bus 12). The control inputs of the decoders / demultiplexers 47.1 and 47.2 are connected to the outputs of the inverters 49.1 and 49.2, respectively.

 The outputs of the first decoder / demultiplexer 47.1 are connected to the inputs from the third to tenth inverters (49.3-49.10), and the outputs of the second decoder / demultiplexer 47.2 are connected to the inputs from the eleventh to eighteenth inverters (49.11-49.18), respectively.

 The outputs of the third and eleventh, fourth and twelfth, fifth and thirteenth, sixth and fourteenth, seventh and fifteenth, eighth and sixteenth, ninth and seventeenth, tenth and eighteenth inverters (49.3-49.18) are connected respectively to the first and second inputs, respectively, from the first to sixteenth multiplexers (48.1-48.16), the third control inputs of which are connected to the control input of the address switching unit 39.

 Multiplexers 40 and 44, inverters 41 and 49 elements AND 42, elements OR 43, tristatic elements 45, buffer elements 46 and decoders / demultiplexers 47 correspond to their functional purpose (Titz U. et al. Semiconductor circuitry. - M .: Mir, 1982 , pp. 33, 326, 328, 366) and performed on programmable LSIs manufactured using CMOS technology, XC 4010-6PQ160C series (XILINX catalog, The Programmble Logic Data Book, 1994, USA).

 The control unit 6 (Fig. 6) contains an input / output port 50, three counters 51 (51.1-51.3), a battery 52, a stack pointer 53, two register 54 flags (54.1-54.2), three interrupt circuits 55 (55.1-55.3) , read-only memory 56 (ROM), two registers 57 (57.1-57.2), a decoder 58, three flip-flops 59 (59.1-59.3) and a multiplexer 60.

 The input / output port 50 by the first group of inputs is connected to the group of inputs of the control unit 6 connected to the bus 23, the second group of inputs is connected to the group of outputs of the multiplexer 60, the third group of inputs is connected to the group of outputs of the counter 51.1. also connected to the first group of inputs of the multiplexer 60 and to the group of outputs of the control unit 6 connected to the bus 33, and the group of outputs is connected to the first groups of inputs of the counters 51, battery 52, stack pointer 53, flag registers 54, register 57.2, decoder 58, and the group of inputs of the 55.3 interrupt circuit.

 The counter 51.1 by the second group of inputs is connected to the output group of the interrupt circuit 55.1, the third group of inputs is connected to the first group of outputs of the stack pointer 53, also connected to the second group of inputs of the multiplexer 60, the fourth group of inputs is connected to the first group of outputs of the counter 51.3, and the fifth group of inputs is connected with the first group of outputs of the register 57.1, also connected to the second groups of inputs of the counter 51.2, accumulator 52, pointer 53 of the stack, registers 54 of flags and register 57.2 and to the first groups of inputs of the circuit 55.1 interrupt and triggers 59.

 The first input counter 51.1 is connected to the output of the trigger 59.3, and the second input is connected to the second input of the group of inputs of the control unit 6 connected to the bus 33.

 The counter 51.3 by the second group of inputs is connected to the group of outputs of the decoder 58, the second group of inputs connected to the first group of outputs of the counter 51.3, the second group of outputs connected to the group of inputs of the ROM 56, and the input connected to the fourth input of the group of inputs of the control unit 6 connected to the bus 33.

 The battery 52 by the group of outputs is connected to the third group of inputs of the multiplexer 60, and the input is connected to the Fifth input of the group of inputs of the control unit 6 connected to the bus 33.

 The stack pointer 53 of the second group of outputs is connected to the third group of inputs of the register 54.2 flags, and the input is connected to the sixth input of the group of inputs of the control unit 6 connected to the bus 33.

 The group of outputs of the register 54.1 flags is connected to the fourth group of inputs of the multiplexer 60, as well as to the group of outputs of the control unit 6 connected to the bus 25, and the input of this register is connected to the seventh input of the group of inputs of the control unit 6 connected to the bus 33.

 Register 54.2 by the group of outputs is connected to the second group of inputs of the interrupt circuit 55.1, the fourth and fifth groups of inputs are connected to the groups of inputs of the control unit 6 connected to buses 15 and 35, the sixth group of inputs is connected to the group of outputs of the 55.2 interrupt circuit, and the input is connected to the eighth the input of the group of inputs of the control unit 6 is connected to the bus 33.

 Interrupt circuit 55.1 by the fourth group of inputs is connected to the group of outputs of the register 57.2, the group of inputs of the circuit 55.2 interrupt and the group of outputs of the circuit 55.3 interrupt are connected respectively to the group of inputs and the group of inputs and outputs of the control unit connected to buses 15 and 26, respectively.

 The inputs of the interrupt circuits 55.1-55.3 are connected respectively to the 9, 10, and 11 inputs of the input group of the control unit 6 connected to the bus 33.

 The group of outputs of the ROM 56 is connected to the first group of inputs of the register 57.1, the second group of inputs and the second and third groups of outputs connected respectively to the group of inputs and output groups of the control unit 6 connected to buses 26, 21 and 27, respectively.

 The inputs of the registers 57.1 and 57.2 are connected respectively to 12 and 13 inputs of the group of inputs of the control unit connected to the bus 33.

 The inputs and outputs of the triggers 59.1 and 59.2 are connected to the inputs and outputs of the input and output groups of the control unit 6, connected to the buses 26 and 27, respectively, and the input of the trigger 59.3 is connected to the input of the control unit connected to the output of the computing unit 8.

 I / O port 50, counters 51, battery 52, stack pointer 53, flag registers 54, interrupt circuits 55, ROM 56, registers 57, descrambler 58, flip-flops 59, and multiplexer 60 correspond to their functional purpose (Titz U. et al. Semiconductor circuitry, pp. 121, 326, 353, as well as the Handbook of Microprocessor Structures. - M .: Radio and Communications, 1990, p. 44, 184, 187, 433-435) and are made on programmable LSIs manufactured using CMOS technology, series XC 4010 - GPQ 160C (XILINX catalog).

 The input-output controller 7 (Fig. 7) contains seven registers 61 (61.1-61.7), three counters 62 (62.1-62.3), read-only memory (ROM) 63, two multiplexers 64 (64.1-64.2), two OR elements 65 (65.1-65.2), decoder 66 and trigger 67.

 The register 61 of the first group of control inputs is connected to the group of inputs of the controller 7 input-output connected to the bus 23, the second group of control inputs is connected to the group of inputs and outputs of the controller 7 input-output connected to the bus 26, and the group of outputs is connected to the bus 68, with which the first groups of inputs are connected registers 61.2, 61.3 and 61.4, a counter 62.2 and a multiplexer 64.2.

 The register 61.2 by the second group of inputs is connected to the group of inputs of the input / output controller 7 connected to the bus 17, and the group of outputs is connected to the group of inputs of the multiplexer 64.1, the first and second groups of outputs connected to the output groups of the input / output controller 7 connected to the buses 19 and 20 respectively.

 The register 61.3 by the second group of inputs is connected to the group of inputs of the I / O controller 7 connected to the bus 26, and the group of outputs is connected to the first group of inputs of the counter 62.1, the outputs connected to the corresponding inputs of the OR element 65.1, and the second group of inputs connected to the bus 69, to which the first group of outputs connected to the decoder 66, and the second group of inputs - registers 61.2, 61.4, 61.6 and 61.7, counters 62.1, 62.2 and 62.3 and the multiplexer 64.2. The inputs of the registers 61.1, 61.3, 61.4, 61.5, 61.6, 61.7 and counters 62.2, 62.3 are connected respectively with 1 to 8 inputs of the group of inputs of the controller 7 input-output connected to the bus 33.

 Registers 61.4 and 61.5 by groups of outputs are connected to the group of outputs of the I / O controller 7 connected to the bus 18, while the register 61.5 by the second group of outputs is connected to the group of outputs of the I / O controller 7 connected to the bus 24.

 Registers 61.6 and 61.7 are connected by the second groups of inputs to the group of outputs of the counter 62.3, also connected to the group of inputs of the ROM 63, the group of outputs connected to the first group of inputs of the register 61.5, the second group of inputs connected to the outputs of the trigger 67, the group of inputs connected to the group of inputs of the input controller 7 output connected to bus 26.

 The group of outputs of the register 61.5 is connected to the first group of inputs of the decoder 66, the second group of outputs connected to the group of outputs of the input-output controller connected to the bus 26.

 The groups of outputs of the registers 61.6 and 61.7 are connected respectively to the third and fourth groups of inputs of the multiplexer 64.2, the group of outputs connected to the second group of inputs of the counter 62.3.

 The counter 62.2 outputs connected to the corresponding inputs of the element OR 65.2, and the counter 62.3 a second group of inputs connected to the group of outputs of the multiplexer 64.2.

 The outputs of the elements OR 65.1 and 65.2 are connected to the corresponding inputs of the decoder 66.

 Registers 61, counters 62, ROM 63, multiplexers 64, OR blocks 65, decoder 66 and trigger 67 correspond to their functional purpose (U. Titz et al. Semiconductor circuitry, p. 121, 353, 370, 377, 403) and are made programmable BIS, 160C (XILINX catalog).

 Computing unit 8 (Fig. 8) contains a matrix (nxm) of processor elements (PE) 70, in which groups of information outputs of each processor element 70j, i (i = 1, ..., n; j = 1, ..., m) are connected to the corresponding groups of information inputs of each neighboring processor element 70j + 1, i + 1. The list of these compounds of the processor elements 70 of the computing unit 8 is given in table. one.

 The groups of information, control, address and clock inputs of each processor element 70 are respectively connected to the groups of information, control, address and clock inputs of the computing unit 8, connected respectively to buses 29, 30, 31 and 33, groups of information outputs of each processor element 70 connected to the group of information outputs of the computing unit 8 connected to the bus 32, and the first output of the group of information outputs of each processor element 70 is also connected to the corresponding th input AND gate 71 whose output is connected to an output computing unit 8.

 When the number of processor elements 70 (and correspondingly their outputs) is such that it is not possible to connect all these outputs to one AND element, they make up a combination (pyramid) of AND elements (not shown), in which the number of AND elements of the first level is selected taking into account the possibility of connecting each output a processor element 70 to the input of the elements, and then the outputs of the AND elements of this level are connected respectively to the inputs of the AND elements of the next level, etc. up to the reduction of all types to one element I. Each first bus line s (not shown) connected to the group of clock inputs of each processor element 70 is connected simultaneously with the corresponding output of the group of outputs of the computing unit 8 connected to the bus 34.

 The processor element 70 contains five multiplexers, four registers, random access memory and arithmetic-logical device. The execution scheme of such a processor element is shown, for example, in patent N 2089936 with a priority of 06/18/96 on the invention of the "processor element".

 The buffer unit 9 (Fig. 10) contains a decoder 72, 2L of registers 73, where L is the ratio n / w, where n is the number of columns in the matrix of processor elements (Fig. 8), and w is the bit depth of words transmitted via bus 28. The internal bit depth of each of the registers 73.1-L of the group is also no more than w-bits.

 The input groups of the decoder 72 and the buffer element 75.1 are connected to the input group of the buffer unit 9 connected to the bus 27.

 The first L outputs (1-L) of the decoder 72 are connected respectively to the inputs of the registers 73.1-73. L, the outputs of which are connected to the group of outputs of the buffer unit 9 connected to the bus 29, and the second L outputs (L + 1-2L) of the decoder 72 are connected respectively to the first inputs of the three-static buffer elements 74.1-74. L (executed on KR1533AP14 chips), the first input groups of which are connected respectively to the output groups of the registers 73.L + 1 - 73.2L, the input groups connected to the input group of the buffer unit 9, connected to the bus 32. The second input groups of the three-static buffer elements 74.1- 74.L and the group of inputs of the buffer element 75.2 are connected to the group of inputs of the buffer unit 9 connected to the bus 18, while the group of inputs of the buffer element 75.2 is connected to the group of inputs of the buffer unit 9 connected to the bus 30.

 The groups of outputs of the three-static buffer elements are connected to the group of outputs of the buffer unit 9 connected to the bus 28, while the group of inputs of the buffer unit 9 connected to the bus 28 is connected to the groups of inputs of the registers 73.1-73. L, the output groups of which are connected to the output group of the buffer unit 9 connected to the bus 29.

 The group of inputs of the decoder 72 and the group of inputs of the buffer element 75.1 are connected to the group of inputs of the buffer block 9 connected to the bus 27, and the group of outputs of the buffer element 75.1 is connected to the group of inputs of the buffer block 9. connected to the bus 31.

 Decoder 72, registers 73, tristatic buffer elements 74, and buffer elements 75 correspond to their functional purpose (Titz U. et al. Semiconductor circuitry, p. 319, 370, 403) and are made on programmable LSIs manufactured using CMOS technology, XC4010- series GPQ160C (XILINX catalog).

 The clock setting and control block 10 (Fig. 11) contains a master oscillator (oscillator) 76, a trigger 77, two inverters 78, two three-stable buffer blocks 79, an OR element 80 and N-frequency controllers 81 (N = nxm and corresponds to the number of processor elements 70 of the computing unit 8).

 The group of outputs of the block 10 of the task and control clock frequency connected to the bus 33 is connected to the outputs of the three-stable buffer blocks 79, the group of inputs of the block 10 of the command and control clock frequency connected to the bus 34 is connected to the first input of the buffer block 79.2 and to the first inputs of the controller 81 frequencies, the output of the clock setting and control unit 10 is connected to the output of the OR element 80, which is also connected to the input of the inverter 78.2 and to the second input of the three-stable buffer block 79.2, and the input of block 10 is connected to the second inputs of the controller 81 hours Ota.

 The output of the master oscillator 76 is connected to the first input of the trigger 77 and the third inputs of the frequency controllers 81, the output of the trigger 77 is connected to the first input of the three-stable buffer block 79.1, to the fourth inputs of the controllers 8! frequency and through the inverter 78.1 to its second input.

 The outputs of the frequency controllers 81 are connected to the inputs of the OR element 80, the output of the inverter 78.2 is connected to the second input of the three-stable buffer block 79.1.

 The frequency controller 81 (Fig. 12) contains three flip-flops 82, an NOR element 83, an NAND element 84, two inverters 85. An AND element 86 and a delay element 87.

 The first input of the frequency controller 81 is connected to the input of the inverter 85.1 and the second input of the trigger 82.2, the second input of the frequency controller 81 is connected to the first inputs of the triggers 82 (82.1-82.3), the third and fourth inputs of the frequency controller 81 are connected respectively to the second and third inputs of the trigger 82.1, and the output of the controller 81 is connected to the output of the trigger 82.3 and the input of the delay element 87.

 The output of the trigger 82.1 is connected to the first inputs of the element NOT-OR 83 and the element And 86, the output of which is connected to the second input of the element NOT-OR 83, the output connected to the third input of the trigger 82.2. The output of the trigger 82.2 is connected to the first input of the inverter 85.2, the output connected to the first input of the AND-NOT element 84, the second input of which is connected to the output of the delay element 87, and the output is connected to the second input of the trigger 82.3.

 In this case, the third input of trigger 82.3 is connected to a + 5V power supply (not shown), and the output of inverter 85.2 is connected to the second input of AND element 86.

 Generator (oscillator) 76, triggers 77 and 82, inverters 78 and 85, three-stable buffer blocks 79, OR element 80, NOT-OR element 83, AND-84 element and delay element 87 correspond to their functional purpose (Titze U. et al. Semiconductor circuitry, pp. 28, 112, 113, 121, 298) and are made on software LSIs manufactured using CMOS technology, XC4010-GPQ160C series (XILINX catalog).

 The operation of the NBMPE system is carried out on the basis of commands divided into a group of commands of control unit 6, including forty-six commands, and a group of instructions of computing unit 8, containing forty-one commands. In this case, the group of commands of the control unit 6 provides the setting of the parameters of the computing unit 8, the transfer of data inside the NBMPE system and the transfer of control, for example, to the input-output controller 7, and the group of commands of the computing unit 8 implements the input-output of data, its transfer, exchange and shift inside computing unit 8, as well as arithmetic and logical operations.

 It should also be noted that the NBMPE system uses 48-bit instructions, and a three-address memory access is selected for arithmetic and logical operations.

 In the given version of the command system, only unsigned integer arithmetic is implemented.

.The generalized command format is: CMOS, modifiers,

.

 The operation code (CPC) is contained in 47-35 bits of the command. Team modifiers (M1, M2) are contained in 37-35. 34-31 bits. M1 (bits 37-35): codes (0-6) h represent the commands of the control unit 6, code 7h - commands of the matrix of computing unit 8. M2 (bits 34-31): Code Eh - is used only for matrix commands in those cases when the command does not contain bit depth (R).

 Before the NBMPE system starts operating, the interrupt processing routines, work programs, and control variables are loaded into memory unit 2 (these data are not shown, since their description is related to solving specific problems, the consideration of which is not advisable here).

In this case, the working area of memory unit 2 is usually divided into four fields:
field of interrupt routines, on which control interrupt routines from the base computer 1 and program-accessible blocks of the NBMPE system are recorded;
field of control variables, where the values of control variables are stored (for example, the number of the current iteration of the program cycle);
a field of output data, where, during operation, the data necessary for viewing and analysis is recorded (for example, when debugging work programs, the state of the internal registers of control unit 6);
field work programs.

In the general case, the computational process consists in sequentially performing the following main steps:
loading the executable program through the base computer 1 to the memory unit 2;
input of the initial data through the base computer 1 and switch 5 into memory blocks 3 and 4;
loading software-accessible subunits of the block 6 control the corresponding programs;
start-up with subsequent data exchange between the base computer 1 and the memory blocks 3 and 4 and the computing unit 8;
receipt of invoice results.

 Input data in blocks 3 and 4 of the memory is produced using the control unit 6, which generates the corresponding signals for the switch 5, and the controller 7 input-output. In this case, the switch 5 is connected to the data bus 16 of the base computer 1 of one of the buses (13 or 14) and, accordingly, of one of the blocks (3 or 4) of the memory, after which data is exchanged between the base computer 1 and the corresponding memory block. The presence of two blocks 3 and 4 of the data memory allows you to organize a continuous stream of data between the base computer 1 and the matrix of processor elements. So, for example, after downloading data from the base computer 1 of the memory block 3, the latter is placed at the disposal of the block of matrices of processor elements and data is received from it under the control of the commands of the controller 7 input-output. At the same time, the host computer 1 may continue to download data to the data memory unit 4. Similarly, the reverse data transmission from NBMPE to the base computer 1 can be organized.

 After loading the working program memory into block 2 and entering the source data into blocks 3 and 4 of the memory, the control unit 6 is started by setting the start address of the program start in the register (not shown) of the counter 51.1 of the control unit 6 and then accessing the memory unit 2 via bus 22 at a fixed address to the first command of the executable program. This command is received (via bus 23) in the control unit 6 and is implemented using it.

 In the General case, through the control unit 6, the computing unit 8 is loaded with the initial data and the processing program is implemented in it, the results are output and stored in the memory blocks 3 and 4, as well as the program termination or an assessment of the need to obtain additional data from the base computer 1 is received decision on the need to transfer the results to the base computer 1.

 In this case, the receipt ("swapping") of additional data from the base computer 1 or the reception of the results of the calculations of block 8 can be carried out directly against the background of the operation of the computing unit 8. In this case, the control unit 6 through the flags of the trigger 59 of the program-accessible registers 54 produces a "notification" base computer 1 about the need to implement the appropriate exchange of information.

 The information exchange between the blocks of the NBMPE system and the base computer 1 is carried out asynchronously by means of mutual interrupts using an eight-bit register (not shown) of the 55.2 interrupt circuit. This register is directly accessible (can interact) to the base computer 1 both for writing and for reading data (the exchange protocol is implemented via buses 15-17).

 In this case, the interrupt code is entered into the interrupt circuit 55.2 from the host computer 1 to the NBMPE system units and the external interrupt flag is set in the control unit 6. This flag is cleared using the RSTINT command. After executing the current command, the control unit 6 executes the hardware command JUMPINT of the transition to the interrupt.

During the execution of this command in block 6 of the control routine perform the following actions:
1. In a register (not shown), the stack pointer 53 increases the level by 1.

 2. At the address indicated in the pointer 53 of the stack, information from the register 57.1 is written to the memory cell of the memory unit 2, into which the address of the next is automatically reset at the end of each command.

 3. Set the flags (triggers 59.1-59.2) to disable interrupts.

 4. Execute the command recorded in the memory cell of the memory block 2 with the address APR, where APR is the contents of the memory cell of the memory block 2 with the address, the low byte of which is stored in the aforementioned register of the 55.2 interrupt circuit, and the high byte is 00h.

The exit from the interrupt program is carried out by means of the RETINT command, during the execution of which the following actions are performed:
1. Remove the flags (via triggers 59.1-59.2) of the interrupt inhibit.

 2. From the memory cell of the memory unit 2 at the address from the above register register 53 stack extract the value of the return address; then in this register they decrease the level by 1.

 3. Use the command recorded in the memory cell of the memory unit 2 with the address AST, where AST is the contents of the memory cell of the memory unit 2 with the address, the low byte of which is stored in the stack register pointer 53 indicated above, the high byte is 00h.

Interruptions on the part of the NBMPE system blocks can be caused in the following cases:
1. Interruption by a flag through trigger 59.3 of a synchronization error in one of the processor elements 70 of computing unit 8 (interrupt source code is 03h, name IERRT).

 2. Interruption by the flag of the register 54.2 flags of the stack overflow of the stack pointer 53 (the source code of the interruption is 04h, name ISTACK).

 3. Interruption by the flag (via trigger 59.2) of the operation code error (interrupt source code - 05h, name INCO).

 4. Interruption by the flag (via trigger 59.1) of the step mode (interrupt source code - 06h, ISTEP name).

 In case of reverse interruption (blocks of the NBMPE system from the side of the base computer 1), the name of the interruption source is INT. and the codes of this interrupt source indicate - (2F, ..., 7F) h.

 The interrupt priorities are set using the MOV Xh PRP command, and the following sequence has been adopted: I work out first: an INT interrupt, then an IERRT interrupt, then ISTACK, and last ISTER.

 Viewing the status of the registers of the control unit 6 is carried out by recording their contents in the memory unit 2.

 After recording (loading) in blocks 2-4 of the source information memory, the task is started by sequentially selecting the operator control unit 6 from the memory unit 2 and exchanging data between the computing unit 8 and the memory units 3 and 4.

 In this case, using the control unit 6, the addresses for the RAM of the processor elements 70 of the computing unit 8 are generated, with the exception of the microcommands of the load, the addresses of the next command are generated, the exchange commands are selected and the reception signals are received by the input / output controller 7.

 From the memory unit 2, commands are sent to the control unit 6 via the bus 23, while the 48-bit command is transmitted in three steps by 16-bit words, which are sequentially downloaded through the port 50 to the registers (not shown) of the counters 51 (51.1-51.3). In control unit 6, these commands are expanded into a sequence of 12-bit microinstructions and 7-bit addresses for computing unit 8. Upon receipt of a data exchange command with computing unit 8 in control unit 6, this command is recognized and an enable signal is issued to the input / output controller 7 and execute the current command. At the same time, in the control unit 6, the flag F0 is set, the trigger 59.1 is closed as a sign of busyness of the input-output controller 7. After the controller 7 completes the execution of the I / O execution of the exchange command, the F0 flag is removed (trigger 59.1 is opened) and thus inform the control unit 6 of the readiness of the I / O controller 7 to execute the next exchange command. If the previous command is not executed in the I / O controller 7, then, until the flag F0 is cleared, the control unit 6 executes a micro-wait command. When the I / O controller 7 clears the flag F0, the control unit 6 is returned to the micro-command on which the execution of the exchange command was interrupted. Such an organization allows the control unit 6 to execute data processing instructions without waiting for the end of loading of the matrix of processor elements 70 of the computing unit 8.

 The I / O controller 7, having received a data exchange command between the computing unit 8 and one of the memory blocks 3 or 4, generates control signals and feeds them through the bus 18 to the buffer block 9, and through the buses 19, 20 and 24 to blocks 3 and 4 memory and switch 5, respectively. The buffer unit 9 switches the bi-directional bus 28 with the bus 29 (when writing data to the computing unit 8) or with the bus 32 (when reading data from the computing unit 8), the corresponding control signals are transmitted via the buses 30 and 31 of the computing unit 8.

 The computing unit 8 implements the possibility of independent work when loading, unloading and processing data. This significantly reduces the processing time of the "window" of data loaded into the computing unit 8, since the exchange commands have a long duration. The optimal alternation of exchange commands with other commands ensures the processing time of the "window" of data, determined only by the input-output time. With the simultaneous execution of the exchange command by the I / O controller 7 and the processing command by the control unit 6, it is possible to simultaneously access the internal RAM of the processor elements 70 of the computing unit 8 in a single clock cycle.

 In this case, the priority belongs to the I / O controller 7, and the control unit 6 delays the execution of its micro-command by one clock cycle. This priority is due to the fact that in the process of executing exchange commands, the invertibility of the I / O controller 7 to the computing unit 8 is usually much less common than the corresponding invertibility of the control unit 6. Moreover, the duration of exchange commands is usually comparable to or longer than the duration of data processing.

 When loading the computing unit 8, information through the buffer unit 9 is recorded in the first row of the matrix of processor elements 70 with a simultaneous shift of the information of all rows of the matrix in the vertical direction (NS or SN). Thus, for each individual row of the matrix, a sequential shift of the data array is performed.

 Simultaneously with loading and unloading, it is possible to perform arithmetic-logical operations on data already in memory and registers of processor elements 70.

 The number of repetitions of the shift cycles during loading depends on the number of rows of the matrix of processor elements 70.

 The array is unloaded in the reverse order.

 Unit 10 of the job and control the clock frequency during operation of the entire device monitors the correct functioning of the computing unit 8 at the level of the clock frequency. This control is necessary due to the fact that block 8 is a homogeneous distributed computing environment, where the synchronization of the care of all its components is especially acute. Block 10 according to the scheme described above (Figs. 11 and 12) constantly compares the clock frequency output to block 8 via bus 33 with the clock frequency coming back via bus 34, and in case of a discrepancy in these frequencies, it generates a signal that is transmitted via bus 35 enters the control unit 6. In control unit 6, a flag is set in register 54.2 for this signal, according to which base computer 1 determines that a hardware failure has occurred in computing unit 8 that requires the intervention of a complex maintenance specialist, and base computer 1 sends a stop signal to the NBMPE system units.

Claims (1)

 A computing system based on a matrix of processor elements, containing a base computer, memory blocks, an input-output controller, a computing unit and a switch, the first and second groups of control inputs of which are connected to the first groups of control inputs of the first and second memory blocks, respectively, and the first and second groups information inputs and outputs of the switch are connected to groups of information inputs and outputs of the first and second memory blocks, respectively, characterized in that a control unit, a block of control and clock frequency and the buffer unit, and the group of control inputs and outputs of the base computer is connected to the first groups of control inputs and outputs of the control unit and the third memory block, the group of information inputs and outputs of the base computer is connected to the group of information inputs and outputs of the third memory block and the third group of information inputs / outputs of the switch, and the group of address outputs of the base computer is connected to the first groups of address inputs, respectively, of the third block memory and I / O controller, the first, second and third groups of address outputs of which are connected to the groups of address inputs of the buffer unit and the first and second memory blocks, the first group of control outputs and the group of address outputs of the control unit are connected to the second groups of address and control inputs, respectively the third memory block, the group of information outputs of which is connected to the groups of information inputs of the control unit and the input-output controller, the group of control outputs of which is assigned to the first group of control inputs of the switch, the second group of control inputs of which is connected to the second group of control outputs of the control unit, and the group of control inputs and outputs of the control unit is connected to the group of control inputs and outputs of the I / O controller, and the third group of control outputs of the control unit is connected with the group of control inputs of the buffer unit, the group of information inputs / outputs of which is connected to the fourth group of information inputs and outputs of the switch, while the groups information, address and control outputs of the buffer unit are connected respectively to groups of information, address and control inputs of the computing unit, the first group of information outputs of which is connected to the group of information inputs of the buffer unit, the first group of outputs of the unit for setting and controlling the clock frequency is connected to the groups of clock inputs of the input controller - output, control unit and computing unit, the second group of information outputs of which is connected to the group of inputs of the task unit and clocking frequency, the second group of outputs connected to the group of control inputs of the control unit, the information input connected to the corresponding output of the computing unit, and the base computer is connected to the control input of the clock setting and control unit by the output, and the computing unit is made in the form of a matrix of processor elements.

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