RU2168270C2 - Process of coding of digital signals and device for its implementation - Google Patents

Abstract

FIELD: communication, transmission systems of various assignment. SUBSTANCE: given process of coding is based on processing of initial signal by signal of clock frequency. Initial digital signal is delayed in advance, delayed and initial signals are compared, packages of "1" and "0" and alternating "1" and "0" are detected in digital signal and are transformed into three-level pulse signal with duration corresponding to those of packages, four clock pulse trains with duration of pulses and pauses equal to duration of one symbol are formed and shifted relative one another through intervals multiple of number of halves of duration of single symbol. After this they are utilized to process initial digital signal. Pulses or pauses with duration multiple of number of halves of one bit and exceeding one bit whose start coincides with start of this or that clock pulse train are formed at points of transition from one packages to other packages. Duration of time intervals between pulses of transition is analyzed and if it does not exceed maximum possible duration of pulse transition then pulses of one bit duration are formed in these intervals. In opposite case they are formed by duration exceeding duration of pulses of transition whose starts coincide with start of any clock pulse train. Specified pulses are sent into communication line when pause with duration not shorter than one symbol between them and pulses of transition or between pulses proper can be formed. EFFECT: generation of more qualitative both frequency and time characteristics of coded signal. 4 cl, 32 dwg

Description

 The invention relates to communication technology and the field of coding of digital signals and can be used in transmission systems for various purposes, including the use of optical fiber.

 An arbitrary digital sequence L (t), when transmitted over a communication line, can be encoded in various ways, as shown in FIG. 1a-e [Digital and analog transmission systems: Textbook for high schools / V.I. Ivanov, V. N. Gordienko, G. N. Popov and others. Ed. IN AND. Ivanova - M.: Radio and Communications, 1995, p. 189].

 In FIG. 1a shows the simplest unipolar linear code "NRZ" [non return to zero, i.e. without returning to zero], in which single bits of a digital signal during transmission correspond to pulses of the same duration, and zero bits correspond to the absence of a signal. In this code, one digital bit is transmitted by one signal. If one digital bit is transmitted with two signals, then different codes can be implemented depending on the method of transmitting units and zeros.

 So, if one half of a single symbol is transmitted by a pulse, and the other by a lack of a pulse, and all zero bits are transmitted by the absence of a signal, then we obtain the code "RZ", i.e. returning to zero, shown in FIG. 1b. The biphasic code “BIF” [or Manchester] is obtained if “0” is transmitted by a sequence of pause and pulse, and “1” is transmitted by a sequence of pulse and pause [Fig. 1c], or vice versa. This code is an example of a block code of the form: nBmB [for n = 1, m = 2], where n is the number of encoded digital bits and m is the number of two-level signals transmitted along the line corresponding to n bits, while B defines the binary base of the system number notation "NRZ". If, for example, n = 2, then this means that not one, but two bits are encoded at once, and the value m then indicates the number of bits that replace the original two bits.

 So, for n = 2, m = 3 we get a code of the form 2B3B [Fig. 1g]. The formation algorithm is as follows: the bits "00" are replaced by 001, "01" by 010, "10" by 100, "11" by 011, which provides a certain decrease in the transmission speed in the line as compared to 1B2B codes.

 The CMI code [complemented mark inversion, i.e. with full sign inversion] shown in FIG. 1d In this code, the blocks "11" and "00" are alternately used to transfer the unit, while zeros are transmitted using the combination "01" or "10".

 In the Miller code [FIG. 1e], which relates to block codes of the form 1B2B, the code message “0” of the binary signal is assigned the code word “11” or “00”, and the code message “1” of the binary signal is respectively “01” or “10”, and the sequence zeros of the original binary signal are transmitted by alternating the code words "11" or "00". For other combinations of binary signal bursts, the first codeword of the codeword should be the same as the last of the previous codeword. It should be noted that in a number of publications indicated later in the application, the Miller code in addition to the abbreviation "M" is also referred to as "MFM" from the words: Modified Frequency Modulation Code.

 To obtain the codes mentioned above, a clock signal "C" is usually used, which in one way or another processes the NRZ code, as shown in the time diagrams of FIG. 2 for the case of receiving the Manchester code.

 Along with the simplicity of the implementation of the listed known codes, they also have the disadvantages listed in the above-mentioned book. V.I. Ivanova [L. 1]. So, the code "NRZ" contains a constant component and a significant proportion of low-frequency components in the spectrum when transmitting a long sequence of units, which complicates the coupling of communication equipment located along the transmission line, which, as a rule, contains reactive elements and transformers. When transmitting a large sequence of zeros, there is a danger of losing synchronization.

 It is also impossible to register errors in the "NRZ" code, since any combination of signals is permissible during transmission.

 The code "RZ" practically repeats the shortcomings of the code "NRZ". Therefore, other codes were also developed, including those listed above.

 However, all of them have a disadvantage associated with the fact that when one digital bit of the original signal is transmitted by two signals, the relative transmission rate in the linear path is twice as high as the symbol rate 0, 1 of the digital signal, i.e. Frequency redundancy is introduced into the transmitted signal, which leads to the need to expand the operating frequency band of devices implementing these codes.

 In addition to the above, there are other codes. In particular, bipolar codes are also used along with unipolar codes [i.e. three-level] codes, when the zero signal of a digital signal is associated with a negative signal transmitted over a communication line generated in one way or another, for example, as shown in FIG. 3 for the case of obtaining the simplest bipolar code "NRZ" [bipolar NRZ].

 There are more advanced three-level codes. So, the bipolar code is known [see European patent N 0299639, M. cl. H 03 M 5/18, H 04 L 25/49, publ. 06.27.88] by the American company DAVID SYSTEMS, INC., Named by its authors as "PMFM" [from the words: Pulsed Modified Frequency Modulation], by analogy with Miller's code "MFM", because it is essentially derived from the code "MFM" .

 Timing diagrams illustrating receipt of the "PMFM" code are shown in FIG. 4, from which it can be seen that the original digital signal [FIG. 4a] processing it with a clock signal [Fig. 4b] are first converted to the Manchester code [FIG. 4c], and then from it to Miller's code "MFM" [Fig. 4d]. A further procedure for generating the "PMFM" code is as follows. During the positive edge of the pulses of the "MFM" code, a new pulse of positive polarity is generated with a duration equal to the duration of the clock pulse [CLOCK], and during the negative edge of the pulse of the code "MFM" a new pulse of negative polarity is formed with a duration equal to the duration of the clock pulse.

 The main disadvantage of the PMFM code, like all three-level codes, is the introduction of redundancy, which leads to an increase in the number of electrical levels in the encoded signal [three instead of two, as in unipolar codes].

 Also known is a two-phase code with a half pulse length - Half Pulse Differentially Biphase Code (HPDB), taken as a prototype, which is described in US Pat. France N 2706104, M. cl. H 03 M 5/18, publ. 09/22/95 [author E.Klibanov].

 The author has proposed both a method of encoding an initial digital signal and a method for subsequently converting the resulting code into an analog signal that can remain a carrier of the original digital information.

 This patent was taken as a prototype, since the method of encoding the original digital signal, leading to the implementation of a pulse sequence of a very specific kind, described in French patent N 2706104, has the greatest number of similar features with the claimed encoding method.

(t), как это показано на фиг. 5. При этом через "T" обозначена длительность одного бита исходной цифровой последовательности i(t).The essence of the method of encoding a binary signal according to the specified US Pat. France consists in the fact that the original digital signal i (t) is encoded by a two-phase code K (t) with a constant pulse duration T / 2 equal to the duration of one pulse of the clock sequence h (t) or

(t) as shown in FIG. 5. In this case, the duration of one bit of the original digital sequence i (t) is indicated by “T”.

 According to the method proposed in said patent, 4 [four] binary signal coding algorithms are possible.

(t) во второй фазе, а все символы "0" двоичного сигнала i(t) за исключением того, который следует непосредственно за символом "1", представлены тактовым импульсом h(t) в первой фазе.So, the 1st algorithm is obtained by representing all the symbols "1" of the binary signal i (t) with a clock pulse

(t) in the second phase, and all the symbols “0” of the binary signal i (t), with the exception of the one immediately following the symbol “1”, are represented by a clock pulse h (t) in the first phase.

(t) являются инверсными по отношению друг к другу.As can be seen from the timing diagrams of FIG. 5 clock pulse sequences h (t) and

(t) are inverse to each other.

 The encoded signal obtained in this manner is indicated in FIG. 5 through K1 (t).

 Three other algorithms are implemented in a similar way through the use of one or another clock signal in the corresponding phase when encoding single and zero characters of the original digital signal.

 Three other encoded signals, indicated in FIG. 5 through K2 (t), K3 (t), K4 (t). Moreover, it is characteristic for all four encoded signals that the highest pulse repetition rate in them is twice as high as the repetition rate of alternating symbols of the original digital signal [i.e. 1 and 0], and the pulse duration of such an encoded signal is equal to half the duration of one bit of a digital signal, which naturally degrades the frequency properties of the code compared to the original digital signal.

 A further content of the said French patent relates to the subsequent conversion of the encoded signal obtained in the above manner into analog using a symmetric ladder function in order to improve the frequency properties of the primary encoded signal.

 The spectra of the codes considered above, taken from the aforementioned book. IN AND. Ivanova. Digital and analog transmission systems., And from the French patent description, are shown in the diagrams of FIG. 6. Under the index [M '], these diagrams show the spectrum of the encoded signal, which is close in structure to the Miller code, but in which the shortest pulse duration is 1.5 bits, not 1 bit, which was typical of the Miller code. How this coded signal can be obtained will be discussed later.

 There is also a method of representing a delta-modulated signal before its subsequent processing when decoding in the form of various groups of [packets] of the same type of symbols: single, zero, alternating ["0" and "1"], which is described in patent application N 94040884 / 09, the decision to grant a patent dated 09.29.97 [authors Andreev V.A., Lutsenko A.P.].

 According to the method described in said application, the received delta modulated signal is pre-recorded [i.e. memorized] and then processed accordingly.

 The essence of the method is illustrated by showing the filling of the memory cells of the data registers P1 [Fig. 7b] and P2 comparisons [FIG. 7c] for the case of an arbitrarily taken digital sequence L (t) shown in FIG. 7a.

Moreover, in the high bit D ₇ of the data register P1, which is a sign bit, a log is written in the memory cells A _N. 1 when positive pulses occur in the original digital pulse sequence L (t) of the delta signal and zeros are recorded when there are negative pulses in the delta signal.

In the low bit D ₀ and bit D ₆ of the memory cells of the register P1 write a log. 1 upon receipt of each successive pulse of the delta signal, regardless of the polarity. Then, the data of register P1 is processed by comparing the contents of the sign bit D ₇ for two adjacent cells A _N and A _{N + 1} , as a result of which packets of the same type of pulses, either positive or negative, are isolated in the received delta signal, and the number of pulses in each packet is recorded in that memory cell of the comparison register P2, with which this cell begins [Fig. 7c].

In the case of the delta signal considered as an example [FIG. 7a] there is a packet of three negative pulses, which reflects the entry in cell B _{4 of} register P2 in binary code [ie "11"] and the next packet of four positive impulses, which reflects the binary entry ["100"] in the seventh cell of B _{7 of} register P2.

 Subsequently, the digital code thus obtained, recorded in the memory cells of the register P2, during its reading from these cells controls the digital-to-analog conversion, as a result of which an output voltage corresponding to the binary number read from the memory cells of the register P2 is obtained. By integrating and filtering the signal after digital-to-analog conversion, the analog signal is restored.

 As can be seen from the above, in the well-known solution, the technique of selecting groups of [bursts] of the same type of pulses is applied to an encoded digital signal, which is a delta signal, when it is decoded.

 An examination of the known encoding methods, including the method taken as a prototype, shows that in order to eliminate the numerous drawbacks inherent in the simplest "NRZ" code, it is necessary to use codes that contain redundancy, which can be of two kinds.

 1. The transmission speed of the signals over the communication line is chosen equal to the transmission speed of the original digital sequence, however, additional electrical signal levels are introduced [the so-called three-level or multi-level codes].

2. With a constant number of levels of electrical signals, the transmission speed of the signals themselves over the communication line becomes greater than the transmission rate of the original digital sequence. [B. V. Shevkoplyas. Microprocessor structures, Engineering solutions, M., Radio and communications, 1986, pp. 94-95]. Therefore, despite its advantages in comparison with the simplest NRZ code [lack of constant component accumulation and long pauses, the possibility of regular synchronization, etc.], the known unipolar codes listed also have disadvantages:
firstly, the need to increase the speed of signal transmission over the communication line compared to the original digital sequence, which leads to the expansion of the spectrum and increase the working frequency band;
secondly, it is difficult to detect and correct errors that are possible during code transmission, since the correlation relationships in known codes extend essentially to two adjacent code pulses, and therefore, restore the encoded signal when two or more consecutive code pulses disappear without comparison with the original signal is almost impossible.

 The objective of the proposed method is to obtain higher quality both frequency and time characteristics of the encoded signal.

 The solution to this problem of the invention is achieved by the fact that in the method of encoding digital signals based on the processing of the original digital signal by a clock signal, the difference is that the original digital signal is pre-delayed, after which, by comparing the original and delayed digital signals, they are detected in digital the signal of packets of single, zero and alternating between single and zero characters, convert these packs with a symbol into a three-level pulse signal, consisting of and From positive, negative and zero voltage values with the durations of these pulses equal to, respectively, the durations of the packets of single, zero and alternating symbols, four clock pulse sequences are formed having a pulse repetition rate equal to the pulse repetition rate of the initial digital signal, and the pulse duration and pauses equal to the duration of one character of the original digital signal, while shifted in time relative to each other at intervals, multiple half the duration of one symbol of the original digital signal, after which a three-level pulse signal is processed with these clock sequences, and in the places of transitions from one packet to another, pulses or pauses are shifted to one side or another from the transition boundary, with durations exceeding the duration of one symbol the original digital signal and multiples of half the duration of one character, the beginning of which coincides with the beginning of a particular clock sequence, if there are the signal of two transitions following in succession with an interval equal to the duration of one symbol, in the places of these transitions an impulse is formed with a duration exceeding the duration of the pulses of the other transitions and a multiple of half the duration of one symbol, the beginning of which coincides with the beginning of any clock sequence, then additionally delay the generated pulses for a time equal to the maximum possible duration of the transition pulses, analyze the duration of the time intervals between the pulses moves, and if the duration of these intervals does not exceed the maximum possible duration of the transition pulses, then pulses of one bit duration are generated in these intervals, and if bursts of single characters follow the transition pulses, then this pulse of one bit duration is generated at those times when the positive values of the voltage of the three-level signal coincide with the pulses of the first clock sequence if, after the transition pulses, packs of alternating units are followed and zero symbols, then the indicated pulse with a duration of one bit is generated at those times when the zero voltage values of the three-level signal coincide with the pulses of the second clock sequence inverse to the first, and if bursts of zero symbols follow the transition pulses, then the specified pulse of duration one bit at those times when the negative voltage values of the three-level signal coincide with the pulses of the third clock sequence shifted relative to howling for an interval equal to half the duration of one symbol of the source digital signal, moreover, one-bit pulses generated in this way are transmitted to the communication line only when a pause of at least one character can be formed between them and the transition pulses on each side of this pulse, in cases of the presence in the digital signal of packets of symbols with a duration exceeding the maximum possible duration of the generated transition pulses, in time intervals corresponding to these packets m, between pulses of transitions, pulses are formed with a duration exceeding the duration of one symbol of the initial digital signal and a multiple of the number of half bits that differ from other generated pulses either in their duration or in temporary position, the beginning of which coincides with the beginning of any clock sequence and the number of which is determined by the duration of the processed packets of symbols, and these pulses are transmitted to the communication line only when between them and the transition pulses, or between the of pulses in cases where the number is greater than one pulse duration can be formed by a pause of at least one symbol from each side of said pulses.

 In this case, the method may include processing the initial digital signal both by hardware using discrete elements of digital technology, and using software using computers, moreover, in the case of processing by hardware, the initial digital signal is preliminarily delayed by one bit of the digital signal, and in subsequent processing operations, they are delayed for another time equal to the maximum possible duration of the generated transition pulses, and in the case of abotki original digital signal by software produce a delay of the digital signal immediately at time equal to or greater than the maximum possible length generated during processing transitions pulses.

 Due to the fact that the original digital signal converted in this way in the proposed encoding method is processed by the signals of clock pulse sequences having pulse widths equal to the duration of one symbol of the original digital signal, and not half of this duration, as is the case in known codes, then the frequency the properties of the encoded signal in the proposed method turn out to be better, because it requires a smaller band of working frequencies for transmission, and its spectrum becomes narrower m, rather than in the known codes discussed above.

 The temporal characteristics of the proposed code also turn out to be better due to the fact that both the packs of different symbols of the original digital signal [single, zero, alternating] and the transitions between these packs in the encoded signal correspond to various signs, which were mentioned above, and this , in turn, allows you to detect and eliminate individual errors that are possible during code transfer, occurring at longer intervals than in known codes.

 Indeed, if, as a result of an error [due to interference], for example, one or two or even more code pulses disappearing in succession, then by the type of pulses located at the edges of the “empty” interval formed in the code, one can it is unambiguous to determine whether a started pack of the same type of characters continued in this interval, or if there was a transition to a pack of other characters.

 Knowing the features of the formation of both pulses encoding transitions and pulses encoding various bursts, it is possible to reconstruct the picture of the encoded signal in both of these cases, and without referring to the original digital signal.

 The above discussion of the features of the proposed encoding method shows that it can do without introducing redundancy in relation to the original digital signal [which takes place in the known encoding methods], because in the proposed method the redundancy extends to the original digital signal that has already been converted in this way, and not to its initial view.

The proposed method is illustrated by the structural diagram [Fig. 9], which includes two encoders Ш1 and Ш2. The first encoder Ш1 includes a clock generator installed at the input of the frequency grid forming unit 1, designed to receive signals of six clock sequences: the first and second of which [F ₁ and F ₂ ] have pulse durations four and two times less, respectively one digital signal symbol and intended for synchronizing the operation of the individual blocks, four other sequences F ₃ ... F ₆ have pulse duration equal to one bit, and which obrabatyv dissolved digital signal [are shown in FIG. 10].

 In Ш1, a delay element is also introduced in the form of, for example, a delay line of LZ 4 with a delay time of 1 bit, as well as blocks 2 and 3, respectively, of processing packets of single and alternating characters and block 5 of processing packets of zero characters interconnected in a certain way [as detailed below when considering the device].

 An adder 6 is also introduced in Ш1, the inputs of which are connected to the outputs of blocks 2 and 5. The output of the adder is connected to the input of the second encoder Ш2, which includes blocks 7 and 10, respectively, for processing positive and negative pulses, block 8 for processing zero values of a three-level signal , block 9 - verification and adjustment of the code [bl. P and QC].

 Blocks 7, 8, 9, 10 are connected both with each other and with the output of block 6, as well as with the resolution block of the BR 11. The output block of the VB 12 is connected by its input to the output of the block of BR 11 and the outputs of blocks 9 and 10 [in more detail from this is stated in the description of the device].

 The initial digital sequence L (t) is supplied to the input of the delay line element LZ 4 with a delay time equal to 1 bit of the input digital signal, at the same time, the signal L (t) is fed to the first inputs of the processing units of packets of single symbols [block 2] and packets of alternating symbols [ block 3].

 The output signal LZ 4 is fed to the second inputs of blocks 2 and 3, which makes it possible to compare the initial and delayed signals in these blocks and to isolate packets of single and alternating symbols in the original signal, if any.

The input digital signal is also fed to the input of the frequency grid forming unit [block 1] in order to synchronize its operation in accordance with the input signal, while the clock frequency signal F ₂ with a pulse repetition period of 1 bit is fed to the third inputs of these blocks 2 and 3, synchronizing their work.

 The output signals of blocks 2 and 3 are fed to the first and second inputs of the processing unit of packets of zero characters [block 5]. Moreover, in the absence of corresponding signals at inputs 1 and 2 of block 5, i.e. in the case when there are neither packs of units or packs of alternating characters in the digital signal, a signal characterizing the presence of packs of zero characters in L (t) appears at the output of block 5.

 The output signals of blocks 2 and 5 are supplied respectively to the first and second inputs of the adder 6, at the output of which a three-level pulse signal is generated with pulse durations corresponding to the durations of packets of various symbols in L (t).

 A three-level signal from the output of the adder 6 is fed to the input of the second encoder Ш2, which is connected to the inputs of the processing blocks of positive pulses [block 7], negative pulses [block 10], zero values [block 8], and also with the input of the code verification and correction block 9 [block П and КК], the name of which indicates the functions performed by this block.

 The outputs of the frequency grid forming unit are also connected to the corresponding inputs of the indicated blocks [bl. 1], on which the signals of four clock pulse sequences are generated, having pulse and pause durations equal to the duration of one symbol of the input digital signal and shifted relative to each other by intervals that are multiples of half the duration of one symbol.

 Using these clock sequences, a three-level pulse signal of the first encoder is processed in order to generate pulses encoding particular symbol packets, as well as transitions between these symbol packets of the original signal.

 Another clock signal with a pulse repetition period of 0.5 bits is supplied from the output of block 1 to the corresponding inputs of the blocks located in the second encoder, ensuring synchronization of their joint work.

 Formed at the outputs of these blocks 7, 8 and at the first output of block 9 [block P and KK] pulses, which are a coded signal, are fed to the corresponding inputs of the resolution block BR 11, the output signal of which is fed to the input of the output block WB 12, to which is connected also the second output of block 9.

 From the output of block 12, matching the output of the second encoder with the communication line, the final encoded signal is sent to the code transmission line.

 Devices [encoders] that implement the known encoding methods discussed above contain an encoder with the necessary number of logic elements that are interconnected in a certain way so that the source digital signal can be processed by a clock signal according to one or another encoding method.

(t).So, for example, the functional diagram of the encoding device, taken as a prototype [Fig. 11], which implements the algorithm for processing the initial digital signal considered earlier, is an encoder that contains a matching circuit 12, one of the inputs of which is connected to the output of the digital signal source i (t), and the other is connected to the output of a clock generator issuing a sequence of pulses

(t).

(t).The output of circuit 12 is connected to one of the inputs of circuit 17 EXCLUSIVE OR. The output of the digital signal source i (t) is connected through an inverter 13 also to one of the inputs of the matching circuit 14, the other input of which is connected to the output of a clock generator that produces a pulse sequence of the form h (t), inverse with

(t).

 The output of the circuit 14 is connected to the input of the D-delay trigger 15, the synchronization input of which is connected to the output of the clock generator h (t). The output Q of the D-flip-flop 15 is connected to one of the inputs of the matching circuit 16, the other input of which is connected to the output of the circuit 14. The output of circuit 16 is connected to one of the inputs of the matching circuit 17, the other input of which is connected to the output of circuit 12. An encoded circuit is generated at the output of circuit 17 signal of the form K1 (t).

 The operation diagrams of the device shown in FIG. 12, requiring no special explanation. They also show the types of signals that occur at individual points in the circuitry of the device in accordance with the notation given in FIG. eleven.

 The above also considered a method in which, when decoding, the technique of extracting symbol packets in a digital signal was used. A block diagram of a device that implements the specified method of restoring the original analog signal from a digital delta signal is shown in FIG. 8 and contains a polarity determiner OP2, one of the inputs of which is connected to the input of the device, and the other is connected to the output of the clock generator TG1 connected to the input of the device. The output of OP2 is connected to the first input of the arithmetic-logic device ALU 3, the second input of which is connected to the input of the device, and the third input of ALU is connected to the output of the clock generator TG1. ALU 3 carries out a parallel exchange of information with a read-only memory ROM 4. The joint use of ALU 3 and ROM 4 allows you to process and transcode the information received at the input of the device in order to decode any kind of DM signals in the presence of ROM 4 corresponding data buses.

 The ALU 3 output is connected to the input of the alternating digital-to-analog converter DAC 5, the output of which is connected to the input of the integrator 6, and its output is connected to the low-pass filter input of the low-pass filter 7, the output of which is the output of the device.

 The operation of the device [Fig. 8] is as follows.

 The incoming pulses of the DM signal L (t) are fed to the input of the clock generator TG1, to one of the inputs of the ALU 3, and also to one of the inputs of the polarity determiner OP2, to the other input of which positive pulses from the output of TG1 are supplied.

Thus, the output pulse of OP2 appears and arrives in ALU 3 only if there are negative pulses in the DM signal, whereas if there are negative pulses in the DM signal, there will be a zero signal at the output of OP2. In the sign bit D ₇ of the memory cells of the ALU 3 data register, in the presence of output pulses OP2, a log will be recorded. 1, otherwise zeros are stored.

 Then, according to a predetermined algorithm, the contents of the sign bit [bits] are compared for two sequentially located cells of the data register, in order to detect bursts of the same type of pulses in the delta signal, with the results of this processing being recorded in another register [comparison register], in which they will thus be written in binary code, the number of pulses belonging to a particular packet. At the next stage of processing, the binary code is fed to the input of an alternating DAC 5, the output voltage of which, proportional to the number of pulses in the packet, is supplied to the integrator 6, the output of which is connected to the low-pass filter input of the low-pass filter 7, filtering the integrator signal, thus obtaining the restored analog signal .

 As can be seen from the above, the reception of the allocation of groups [packs] of the same type of pulses is applied in the known device directly to the encoded signal, which is the delta signal during its decoding.

 At the same time, the technique of isolating packets of "same type" characters can be applied to the original digital signal itself before its subsequent encoding, which is the case in the proposed method.

As the analysis of the known devices for encoding digital signals shows above, their disadvantages, caused primarily by the imperfection of the known encoding methods, are:
firstly, the expansion of the operating frequency band of the device in connection with the introduction of frequency redundancy into the encoded signal compared to the original digital signal,
secondly, the noise immunity is not high due to the fact that correlation relationships in known encoding devices extend to no more than one or two adjacent code pulses.

 The objective of the proposed device for encoding digital signals is to increase its noise immunity while reducing the frequency band in comparison with known devices.

 The solution to this problem of the invention is achieved by the fact that in the device for encoding digital signals containing an encoder, the input and output of which are the input and output of the device, which includes a clock, the input of which is connected to the input of the device, and the output is connected to the corresponding output of the encoder, the second encoder and the delay element, the input of which is the input of the device and connected as the output of this delay element to the corresponding inputs of the first encoder, into which the block mesh the one whose input is connected to the output of the clock included at the input of this block, and the outputs of the frequency grid forming unit are connected to the corresponding inputs of both encoders, the first encoder also includes a unit processing unit of single characters, a unit of processing units of alternating characters and a unit of processing zero units characters, and the first and second inputs of the first two of these blocks are connected respectively to the input and output of the delay element, and their third input is connected to one of the outputs of the forming unit I of the frequency grid, and the first and second inputs of the third of these processing units are connected to the outputs of the processing units of packs of single and alternating characters, respectively, and the output of the processing unit of bundles of single characters is also connected to the first input of the adder, to the second input of which the output of the processing unit of zero packets is connected characters, and the output of the adder is connected to the input of the second encoder, which contains a processing unit for positive pulses, a processing unit for negative pulses, a processing unit for zero signal and a code verification and adjustment block [P and QC block], while the first input of this block and the inputs of three other indicated blocks are connected to the input of the second encoder, and the second and third inputs of the “P and QC” block are connected to the corresponding outputs of the processing blocks positive pulses and zero signal values, and one of the outputs of the negative pulse processing unit is connected to the second input of the signal zero processing unit, the P and QC unit is also connected by a communication bus to the negative pulse processing unit, the first the output of the “П and КК” block is connected to one of the inputs of the resolution block, the other two inputs of which are connected to the outputs of the processing blocks of positive pulses and zero values of the signal, and the outputs of the blocks of resolution and processing of negative pulses, combined with the second output of the block “П and КК ", connected to the input of the output unit, the output of which is the output of the device.

 Structural and schematic diagrams of both encoders included in a device that implements the proposed encoding method are shown in FIG. 9, 13, 18. First, we will consider the structural diagrams of the first and second device encoders shown in FIG. 9.

The first encoder Ш1 encoder comprises a frequency grid forming unit 1, at the input of which a clock generator is included, it is designed to generate [t. e. receiving] signals of six clock pulse sequences with equal pulse and pause durations inside each of them, the first F ₁ and second F ₂ clock sequences having pulse durations four and two times less than the duration of one symbol of the original digital signal, and the third F _3, F _4, fourth, fifth and sixth F ₅ F ₆ clock pulses of the sequence have a duration equal to the duration of one symbol of the original digital signal and shifted in time relative to each other int tore, multiple 1T ₁ [wherein 1T ₁ - half the duration of one symbol].

 The form of these sequences is shown in FIG. 10a.

Moreover, as can be seen from the consideration of time diagrams [Fig. 10a], the beginning of the first pulse of the sequence F ₃ coincides with the beginning of the first single symbol delayed by one bit of the original digital signal L ^* (t) [Fig. 10b).

The sequence F ₄ is inverse with respect to F ₃ , and therefore, its beginning is shifted relative to the beginning of the sequence F ₃ by an interval equal to 2T ₁ .

The beginning of the pulses of the sequence F _{5 is} shifted relative to the beginning of the pulses of the sequence F ₃ by an interval equal to 1T ₁ [which corresponds to half the duration of one symbol of the original digital signal].

The sequence of F ₆ is inverse to F ₅ .

 For clarity, consideration of the diagrams in FIG. 10b shows an arbitrarily taken digital signal: initial and delayed.

Moreover, if we designate the pulse repetition rate of the second clock sequence F ₂ , with the help of which the source digital signal L (t) is processed in the first encoder Ш1, by f _t [i.e. F ₂ = f _t ], then the pulse repetition rate of the first clock sequence F ₁ , which is the signal of the master clock TG synchronized with L (t), from which other clock signals are then formed, will be F ₁ = 2f _t , and the frequency following the pulses of the third, fourth, fifth and sixth pulse sequences will be the same and equal: F ₃ = F ₄ = F ₅ = F ₆ = 0.5f _t .

In order to distinguish between these sequences when specifying them through f _t , they are indicated respectively as F ₃ = 0.5f ^' _t [with a prime], F ₄ = 0.5f _t [without dash], F ₅ = 0.5f'' _t [with two strokes] and F ₆ = 0.5f ''' _t [with three strokes].

The repetition periods of the pulses of the first and second sequences are denoted by T ₁ and T ₂ , and the other four by T ₃ . The period of alternating characters of the source digital signal is denoted by T _c , with T ₃ = T _c .

The outputs of the frequency grid forming unit [with the signals of the above clock frequencies] are connected to the corresponding inputs of the various blocks of the first and second encoders Ш1 and Ш2 of the encoder device. The input of block 1 is connected to the input of the device. The block diagram of the encoder Ш1 in addition to block 1 also contains an input delay element L3 4 [Fig. 9], the input of which is the input of the device with a delay time equal to the duration of one symbol [bit] of the original digital signal, ie t _ass = T ₂ according to FIG. 10a, for which a delay line can be taken.

 The first encoder Ш1 also includes a unit 2 for processing packets of single symbols and a unit 3 for processing packets of alternating symbols.

In this case, the first and second inputs of blocks 2 and 3 are connected respectively to the input and output of the delay element LZ 4, and the third input of blocks 2 and 3 is connected to the output of block 1, issuing a clock signal with a pulse duration equal to half the duration of the symbols of the original digital signal [output T ₂ ], while block 3 is also connected with block 2.

 In the first encoder Ш1, another block 5 for processing packets of zero symbols is introduced, the first and second inputs of which are connected respectively to the outputs of blocks 2 and 3 of processing packets of single and packets of alternating symbols, the output of block 2 Ш1 is also connected to the first input of adder 6, and the output of the block 5 Ш1 is connected to the second input of the adder 6, the output of the adder 6 is the output of the first encoder Ш1 encoder.

 In the second encoder Ш2 [Fig. 9] introduced a block 7 for processing positive pulses, block 8 for processing zero values of a three-level signal Ш1, block 10 for processing negative pulses of output voltage Ш1, block 9 for checking and adjusting the code [block П and КК].

Moreover, the first input of block 9 and the inputs of blocks 7, 8, 10 are connected to the output of the adder 6 of the first encoder Ш1, and the second and third inputs of block 9 are connected to the corresponding outputs of blocks 7 and 8. Block 9 is connected by two-way communications with block 10, and connected to the outputs of all clock generators F ₁ - F ₆ . The output 1 of block 9 is connected to one of the inputs of the block of permission BR 11 [allowing or prohibiting the connection of blocks 7 and 8 to the output of the encoder], the other two inputs of block BR 11 are connected to the outputs of blocks 7 and 8. One of the outputs of block 10 is connected to one of inputs of block 8. The outputs of the resolution block BR 11 and the processing unit of negative pulses [bl. 10], combined with the second output of block 9 [bl. P and KK], connected to the input of the output unit WB 12, which ensures coordination of the output of the device with the communication line. The output of the block WB 12 is the output of the device.

 An example of a specific implementation of the circuit diagram of the first encoder Ш1 is shown in FIG. 13. Scheme Ш1 comprises a block 1 for forming a frequency grid, a block 2 for processing packets of single symbols, a block 3 for processing packets of alternating symbols [i.e. 1 and 0], a unit 4 for processing packets of zero characters, as well as an operational amplifier OA 17, which is used as an adder, and a D-trigger delay 6.

Block 1 includes a clock generator TG 1 located at its input with a pulse repetition rate equal to 2f _t , the input of which is connected to the input of the device. The output of TG 1 is connected to the input of the counting trigger ST 2 and to one of the inputs of the second encoder Ш2, and the output of ST 2 is connected to the input of a counting trigger ST 3 similar to it. At the outputs of these triggers pulse signals are generated with pulse repetition frequencies equal respectively to f _t and 0.5f _t , the last of which coincides with the repetition rate of alternating characters [bits] of the original digital signal L (t).

The trigger output CT 3 is connected to the input of the delay trigger D-trigger 4, at the output of which there is a 0.5f ' _t clock signal [with a stroke], i.e. delayed by one bit output signal CT 3.

The output of the D-flip-flop 4 is connected to one of the inputs Ш2, as well as to the input of the pulse forming unit FI 5, the output of which is formed by the clock sequences: F ₄ , F ₅ , F ₆ , having the form shown in the time diagrams of FIG. 10a. The schematic diagram of the block FI 5 is shown in FIG. 10c and contains an inverter in. 1 and delay line LZ 1 [with t _ass = 1T ₁ ], connected by their inputs to the output of D-flip-flop 4, at the outputs of which clock pulse sequences are formed: F ₄ and F ₅ . As F ₄ can be used and the signal output CT 3.

The output of LZ 1 is connected to the input of the second inverter in. 2, at the output of which a sequence F ₆ is formed [Fig. 10a].

Since the output three-level signal Ш1, as will be shown below, corresponds to the initial digital sequence delayed by one bit, denoted by L ^* (t), then for the origin of reference T ₀ in the diagrams [Fig. 10] and all subsequent diagrams, the beginning of the sequence L ^* (t) was accepted, coinciding with the beginning of the first pulse of the clock signal 0.5f ' _t [with a prime], from which sequences F ₄ , F ₅ , F ₆ can be formed. At the input of the first encoder Ш1, a D-delay trigger 6 is activated, synchronized by a clock signal of frequency f _t , the input of which is an encoder input and connected directly to one of the inputs of two-input matching circuits 11 and 19, and also connected through one inverter to one of the inputs of the matching circuit 22.

 In the block diagram of the encoder [Fig. 9] this D-flip-flop 6 is designated as the delay line LZ 4. The second inputs of the matching circuit 11 and 22 are connected to the output of the D-flip-flop 6 directly, and the second input of the matching circuit 19 is connected to the output of the D-flip-flop 6 through the inverter 18.

The output of the D-flip-flop 6 is connected through the inverter 7 also to the reset input R of the synchronous RS-flip-flop 8, synchronized by the clock signal f _t . The input of the installation S of this trigger is connected to the output of the matching circuit 11, which is also part of block 2 Ш1. The output Q T8 is connected to one of the inputs of the matching circuit 10 located at the output of block 2 Ш1. The second input of the circuit 10 through the inverter 9 is connected to the output of the matching circuit 16 located in block 3 Ш1.

 The output of circuit 10 is connected to the input of inverter 12, and also through a balancing voltage divider R2, R5 is connected to the non-inverting input of the operational amplifier OA 17, which performs the function of an adder.

The output of the inverter 12 is connected to one of the inputs of the matching circuit 14, which, together with this inverter, is a part of block 4 Ш1. The second input of the matching circuit 14 through the inverter 13 is connected to the direct output Q of the trigger T 24, synchronized by a clock signal f _t located at the output of block 3 Ш1.

 The output of circuit 14 through an isolation resistor R1 is connected to the inverting input of the op-amp 17 [Fig. 9 is an adder 6].

 The output of the op-amp 17 is the output of the first encoder Ш1 and is connected to one of the inputs of the second encoder Ш2 through the decoupling resistor R3.

The outputs of matching circuits 19 and 22, which are part of block 3 Ш1, are also connected through an OR circuit 20 to the input of the D-trigger delay delay 15 of block 3 Ш1 and to one of the inputs of matching circuit 16 of this block, the second input of which is connected to the output of the D-trigger T 15 synchronized by a clock signal of frequency f _t

 The output of circuit 16 is connected directly to the input of the installation S of the RS flip-flop T 24, as well as through an inverter 23 with a reset input R T 24, the output Q of which is connected directly to the input of the inverter 13 of block 4 Ш1.

 The operation of the first encoder Ш1 encoder [Fig. thirteen].

 In this case, we first note the following.

If it were possible in some way as a result of joint processing of the original L (t) and delayed L ^* (t) sequences of a digital signal, to obtain a new signal having a pulse repetition period that is two [or more] times the sequence period of alternating symbols of the original digital signal [i.e. receive a signal having a smaller compared with the original signal] transmission rate of, for its encoding clock signal has the frequency of 0,5f _m could be used [Fig. 10a] with a pulse repetition period equal to the repetition period of the alternating bits of the original digital signal, while in known codes the repetition period of the clock signal should be equal to half the repetition period of the alternating bits of the original digital signal.

 In this case, the final encoded signal would have a transmission rate equal to the transmission rate of the original digital signal. The necessary processing of the source digital signal is carried out by the first encoder Ш1 of the encoder.

Before starting work Ш1, the master clock generator TG 1 is started, which can be either external or internal, synchronized with the original digital sequence L (t). In this case, the entire block of the frequency grid begins to function, generating the above-mentioned clock sequences [Fig. 10a]. The device issuing the trigger signal U _zap TG 1 may also be external to Ш1.

Further, when an electric signal corresponding to the original digital signal L (t) is received at the input of the encoder, i.e. electrical levels log. "1" which corresponds to single bits, and the electrical levels are log. "0" correspond to the zero bits L (t), the input electrical signal, as indicated, is previously delayed for a while. equal to one period of the clock frequency signal f _t , which is carried out using the input delay line LZ 4 [the delay time is equal to the duration of one bit]. Then the work of the 1st encoder is as follows.

 1. If there are a bunch of single characters in the original digital signal.

In this case, at the output of coincidence circuit 11, positive pulses appear with a duration of 1 bit each time that the previous and next bits [characters] in L (t) match and are equal to the log. 1, i.e. when there will be a coincidence of single bits in the original L (t) and delayed L ^* (t) digital signals at both inputs of the matching circuit 11.

The output signal of the circuit 11 is then fed to the input of the installation S of the trigger T8, triggered on the front of the input signal. In this case, a positive pulse with a duration equal to the duration of the processed packet of single bits is formed at the direct output Q T8. In the zero state, the trigger T8 is translated by the log signal. 1, received at the reset input R T8 from the output of the inverter 7, connected between the output of the delay D-trigger 6 and the input R T8, with the end of the last single bit present in this packet of single bits from the delayed digital sequence L ^* (t). From the output of Q T8, the signal is fed to one of the inputs of the matching circuit 10, open at its other input by a log signal. 1 coming from the output of the inverter 9, because there is no signal from the output of the circuit 16 of block 3 Ш1 in this case.

 From the output of circuit 10, the signal is fed to the input of the inverter 12 located in block 4 Ш1, as a result of which the zero output of the inverter 12 blocks the matching circuit 14 from one of its inputs and thus, block 4 Ш1 in this case does not take part in the work.

 On the other hand, the output signal of the circuit 10 passes to the non-inverting input of the operational amplifier OA 17 [the gain of which can be taken close to 1] and from its output a pulse of positive polarity is fed to the input of the second encoder.

 2. If there are packs of alternating characters in the original digital signal.

In this case, pulses of positive polarity will appear alternately either at the output of the two-input matching circuit 19, then at the output of another similar matching circuit 22, then their signals through the OR circuit 20 are fed to the input of the D-trigger delay 15, synchronized by the clock frequency signal f _t .

The output Q T15 is connected to one of the inputs of the matching circuit 16, the other input of which is connected to the output of the OR circuit 20. From the output of circuit 16, the signal is supplied to the inputs of inverters 9 and 23, as well as to the input of installation S of trigger T 24, which is triggered by the pulse front and synchronized by a clock signal f _t , while the reset input R T 24 is connected to the output of the inverter 23. From the direct output Q T 24 the signal is fed to the input of the inverter 13 of block 4 Ш1. In this case, the zero output signal of the inverter 13 blocks the coincidence circuit 14 for one of its inputs for a time equal to the duration of the packet of alternating characters ["1" and "0"] present in the original digital signal L (t).

 Therefore, a burst of alternating symbols in L (t) at the output of the op-amp 17 will correspond to a zero signal having a duration equal to the duration of a burst of alternating symbols. The minimum size of a packet of alternating characters will thus contain two bits: either 1 and 0, or 0 and 1, depending on which characters the packet of alternating bits went after.

 3. If there is a pack of zero characters in the original digital signal. In this case, neither the coincidence circuit 10 of block 2 Ш1 nor the direct output Q T 24 of block 3 Ш1 will have output signals, and thus the log signals simultaneously appear at the outputs of inverters 12 and 13 of block 4 Ш1. 1 and, therefore, the same signal log. 1 will also appear at the output of matching circuit 14, at the inputs of which the indicated inverters are switched on.

 From the output of circuit 14, the signal is fed to the inverting input of the op amp 17, at the output of which in this case a pulse of negative polarity is formed with a duration equal to the duration of the packet of zero bits in L (t).

The foregoing is illustrated by the timing diagrams shown in FIG. 14 and 15 for the case of two arbitrarily taken as an example, the digital sequences L ₁ (t) and L ₂ (t).

Thus, as a result of the operation of the 1st encoder Ш1 of the encoder, a three-level pulse signal is generated at its output, which carries complete information about the original digital signal L (t), or rather, about this signal delayed by 1 bit. Therefore, the reference point in the diagrams "t ₀ " was taken to be the beginning of the initial digital sequence L ^* (t) delayed by 1 bit [as mentioned above].

 It can be noted right away that during the subsequent processing of this three-level signal in the second encoder Ш2 of the encoder, negative pulses in the corresponding Ш2 block will again be converted before processing into positive pulses of the same duration so that it would be possible to use only positive logic logic elements in the second encoder , which makes the Ш2 circuit simpler and improves its operation.

Trigger T8 is reset to zero by the output signal of the inverter 7, which appears with the end of the last single pulse in the burst of the delayed sequence L ^* (t), which is reflected in the timing diagrams [Fig. 14 and 15].

 We also note that when the original digital signal L (t) contains either one single bit inside the packet of zero bits, or vice versa, when one zero bit is inside the packet of single bits, this leads to the appearance of the first encoder Ш1 in the process the output of the coincidence circuit 16 Ш1 of a single pulse with a duration equal to the duration of one bit, as shown in the time diagrams [Fig. 16 and 17], which, in turn, leads to the appearance in the output signal of the OS 17, which in the cases under consideration is either negative or positive, a pause of the same duration equal to one bit.

 How to process such output signals of op-amp 17 then in the 2nd encoder encoder [taking place when there are two transitions in the original digital signal that follow in succession with an interval of one bit], it will be shown later when considering the operation of the code verification and adjustment unit located in the second encoder.

 In the meantime, we note that the availability of complete information about the original digital signal L (t), which is available in the output three-level signal of the first encoder Ш1 encoder, allows, on the one hand, to significantly simplify the scheme of the second encoder Ш2 encoder, and on the other, allows additional control over the operation of the second encoder Ш2 by comparing the output signals of various blocks Ш2 with the output signal of the first encoder Ш1.

 Regarding the construction of the timing diagrams shown in FIG. 14 ... 17, then no special explanations are required, given the simplicity of the first encoder circuit [Fig. thirteen].

 Naturally, by changing the order of connecting the outputs of blocks Ш1 to the inverting and non-inverting inputs of OS 17 [performing the function of an adder], one can also change the order of formation of pulses responsible for certain symbol packets in L (t) even at different voltage values of a three-level signal in comparison with the above formation order, which is unprincipled.

A schematic diagram of a second encoder encoder is shown in FIG. 18 and contains the following elements and blocks - block 1, intended for processing positive pulses present in a three-level signal supplied to the input of the second encoder Ш2 from the output of the first encoder Ш1, includes a two-input matching circuit 25, one of the inputs of which is connected to the output Ш1 and the other is connected to the output of the D-flip-flop T4 of the frequency grid forming block Ш1, which generates a clock signal with a pulse repetition rate of 0.5 f ' _t [with a stroke], shown in FIG. 10a.

The output Ш1 is also connected to the input 1 of the code verification and correction block [П and КК unit], as well as to the inverting input of the OS 38. The output of circuit 25 is connected to the input of the delay line LZ 26 with a delay time of 4T ₂ [where T ₂ is the signal period clock frequency f _t ], and the output of LZ 26 is connected to one of the inputs of the OR 32 circuit and then through the enable input of the PROHIBIT 34 and a decoupling diode D1 with a non-inverting input of the output operational amplifier OU 37, the output of which is the output of Ш2 and simultaneously the common output of the encoder.

 The inhibitory input of the circuit 34 is connected through an inverter 33 to the output 6 of the block P and KK 36. The output of the circuit 25 is also connected to the input 4 of the block P and KK.

Block 2, designed to process the zero values of the pulse signal coming from the output of Ш1 encoder, includes two inverters 27 and 29, connected by their inputs to the output of Ш1 and to the output of the D-trigger delay T4 of block 1 of Ш1, which generates a clock signal of frequency 0 , 5f ' _t [with stroke]. The outputs of the inverters 27 and 29 are connected to the first inputs of the matching circuits 28 and 30, respectively, the second input of the circuit 28 through the inverter 35 is connected to the output of the operational amplifier OA 38 of block 3 Ш2, and the second input of the circuit 30 is connected to the output of the circuit 28.

The output of circuit 30 is connected to the input of the delay line LZ 31 with a delay time of 4T ₂ [where T ₂ is the period of the clock signal f _t ], as well as to input 3 of the block P and KK Ш2, the 9th and 2nd inputs of which are connected respectively, with the outputs of the clocks f _t and 2f _t . The input 10 of the block P and KK is connected to the output of the clock generator 0.5f ' _t [with a stroke].

 The output of LZ 31 is connected to one of the inputs of the OR 32 circuit, and its output is connected to the enable input of the PROHIBIT 34, the output of which is connected through a decoupling diode D1 to the non-inverting input of the output operational amplifier OU 37.

 Elements of the circuit Ш2, indicated by numbers 32, 33, 34, as well as the diode D1 are part of the resolution block BR 11 Ш2 [Fig. 9].

 Block 3, designed to process negative pulses from the output Ш1, includes an operational amplifier ОУ 38, the inverting input of which is connected through the resistor R1 to the output of the 1st encoder Ш1, and also through the feedback resistor R3 is connected to the output of this ОУ. The gain of the OS 38 can be taken close to "1", because its task is only to invert the signal supplied to its input from the output Ш1, which allows processing the negative voltage values of a three-level signal in block 3 Ш2 in positive logic, those. as in blocks 2 and 1 Ш2. Block 3 Ш2 does not respond to positive impulse values, since in this case the negative output signal of the op-amp 38, entering one of the inputs of the two-input matching circuit 39, blocks its operation.

So, the output of the op-amp 38 is connected through an isolation resistor R4 to one of the inputs of the circuit 39, the other input of which is connected to the output of the 0.5f '' _t clock [with two strokes]. The output of the circuit 39 is connected to the input of the delay line LZ 41, as well as to the input 7 of the block P and KK.

The output of LZ 41 [with a delay time of 4T ₂ , i.e. as with LZ 26 and LZ 31] it is connected to one of the inputs of the matching circuit 42, the other input of which is connected to the output of the inverter 40, the input of which is connected to the output 6 of unit P and KK 36. The output of the circuit 42 is connected via a decoupling diode D2 to a non-inverting one the input of the OS 37 and the output 5 of the block P and KK.

Block П and КК, containing a number of logical elements forming separate channels, intended, firstly, to analyze the types of certain combinations of two adjacent pulses of the code in the process of its formation, taking into account both their durations and the durations of time intervals between them,
secondly, to form corrective impulses in the places of transitions in those cases when it is required,
thirdly, to form pulses that block the outputs of blocks 1, 2, 3 of the second encoder for the time necessary for the correct passage of correcting pulses to the output of the encoder.

 More details about the work of bl. P and QC will be discussed later. The logical elements that are part of the encoder encoder circuits are finished products made on one or another type of logic, for example, based on TTL.

 Digital delay lines can be implemented, for example, on D-flip-flops or on memory circuits, shift registers.

 Operational amplifiers, which are standard products of analog circuitry of widespread use, are also miniature, i.e. comparable in size to logical elements. Thus, the practical implementation of the encoder does not cause technical difficulties.

 The operation of the second encoder Ш2 [Fig. 18].

 1. Work Ш2 upon receipt of pulses of positive polarity at its input.

In this case, block 1 Ш2 is turned on, in this case unipolar pulses of positive polarity will also be generated in the code, moreover, coinciding in time with pulses of a clock signal of 0.5f ' _t [with a prime] and equal to, as already noted, the repetition rate of alternating characters of the original digital signal L (t) and with a duration equal to the pulse width of this clock signal.

 The generated code pulses from the output of the matching circuit 25 are received through the delay line LZ 26 to one of the inputs of the OR circuit 32 of the permission unit and from its output to the enabling input, the PROHIBIT 34, from the output of which through the decoupling diode D1, are fed to the non-inverting input of the op-amp 37. From the output of this op-amp, the encoded signal enters the code transmission line.

 The foregoing is illustrated by the timing diagrams shown in FIG. 19b. Moreover, for greater clarity, a joint review of the diagrams of FIG. 19a [illustrating the operation of the first encoder for this case] and FIG. 19b [explaining the operation of Ш2] the encoded signal is shown so far without taking into account the action of the output delay line LZ 26 of block 1 of Ш2, which is not important here.

 As for LZ 26, it, like the other two delay lines LZ 31 and LZ 41, located respectively at the outputs of blocks 2 and 3 of the second encoder, provides equalization of the signal propagation time in various channels Ш2, with the aim of their synchronous operation.

 Blocks 2 and 3 Ш2 themselves are blocked during the operation of block 1 Ш2 and do not participate in Ш2 operation. In this case, block 2 is blocked by a zero signal coming from the output of the inverter 27 to one of the inputs of the matching circuit 28, since in this case there is a positive signal at the input of this inverter, and block 3 Ш2 is blocked by a negative signal coming from the output of the op-amp 38 to one of the inputs of the matching circuit 39, which is equivalent to a zero signal at this input, since the input anti-ring diodes of the logic of the positive logic are open and keep the circuit from being triggered.

The repetition period formed in 1st Block Sh2 pulse code T _K is equal to the repetition period T _p interleaved symbols of the original digital signal L (t), as required.

 2. Work Ш2 upon receipt at its input from the output Ш1 of the zero level of the pulse signal.

In this case, the operation of block 1 Ш2 is stopped, because the matching circuit 25 is blocked on one of the inputs by a zero signal Ш1. At the same time, block 2 Ш2 begins to function, and only at those times when the signal of the clock frequency 0.5f ' _t [with a prime] will also have zero values, or in other words, when a clock signal of 0.5f _t [without a dash], which is provided by the output signal of the inverter 29, at the input of which a frequency signal 0.5f ' _t [with a dash] acts, since the output of this inverter is connected to one of the inputs of the matching circuit 30.

 At the same time, it is also impossible to send a signal directly from output Ш1 to the second input of coincidence circuit 30 either through an inverter, because there is not two but a three-level pulse signal at output Ш1, and therefore coincidence circuit 30 could start to respond not only to zero, but also to negative values of the output signal Ш1 and that would disrupt the normal operation of the second encoder Ш2, since the presence of anti-ring diodes at the input of logic elements [as mentioned above] reduces the levels of negative voltages at their input to a value not exceeding 0.7 V, n that circuit is responsive to both the zero signal.

 That is why, in block 2 Ш2, a two-input matching circuit 28 with inverters 27 and 35 included at its inputs is additionally introduced. In this case, the signal is log. "1" although it will occur at the upper input of circuit 28 if there are not only zero, but also negative voltage levels at output Ш1, however, at the lower input of coincidence circuit 28, the log signal. "1" will not occur at negative voltages at the output of Ш1, because the output of Ш1 is connected to the inverting input of the OS 38, the output of which is no longer negative, but a positive signal, being fed to the input of the inverter 35 connected to one of the inputs of the circuit 28, will block its operation on this input with the zero output signal of the inverter 35. Thus, the signal is log. "1" at the lower input of the matching circuit 30 will appear only at zero levels of the pulse signal coming from the output Ш1, which is required.

 Moreover, in the code, as in the first case considered above, unipolar positive pulses will also be generated and, again, with a duration equal to the duration of one bit of the original digital signal, following with the repetition rate of alternating symbols of this signal.

The time of occurrence of these code pulses corresponds to zero values of a 0.5f ' _t clock signal [with a dash], or otherwise coincides with a 0.5f _t clock signal [without a dash], since the signals of these clock frequencies are shifted relative to each other by a time equal to half the period of their impulses, i.e. in antiphase [Fig. 10a].

 The foregoing is illustrated by the timing diagrams shown in FIG. 20b, with FIG. 20a are timing diagrams explaining the operation of the 1st encoder encoder for the case in question.

 The action of the output delay line LZ 31 of block 2 Ш2 when plotting the diagrams of FIG. 20b for better clarity of their consideration in conjunction with the diagrams of FIG. 20a has not yet been taken into account [which is unprincipled].

 3. Work Ш2 upon receipt of pulses of negative polarity at its input. In this case, block 3 Ш2 is included in the operation, and the operation of blocks 1 and 2 is blocked, respectively, by the absence of a log signal. "1" at the lower input of the matching circuit 25 and the zero output signal of the inverter 35, at the input of which there will be a positive signal taken from the output of the OS 38 located in block 3 Ш2.

The negative pulse present at the output of Ш1, and consequently at the inverting input of the op-amp 38, creates a pulse of positive polarity at the output of this op-amp 38, as a result of which the coincidence circuit 39 will be unlocked at its upper input for a time equal to the duration of the negative pulse that takes place at the output of Ш1. In this case, the pulses of the 0.5f '' _t clock [with two strokes] will pass through LZ 41 and coincidence circuit 42 to the non-inverting input of the op-amp 37 and from its output to the code transmission line. The foregoing is explained by the timing diagrams shown in FIG. 21b. In the diagrams of FIG. 21a shows the signals of the individual blocks of the 1st encoder, corresponding to the case under consideration. The effect of the output delay line LZ 41 of block Ш2 has not yet been taken into account for a more visual joint consideration of the diagrams shown in FIG. 21a and 21b [which is unprincipled].

 Since the formation of the proposed code is accompanied by operations such as sequentially breaking [marking] the initial digital signal L (t), followed by encoding, the resulting code can be abbreviated [named] as “ALC” code, by analogy with the known codes type: NRZ, AMI, CMI, MFM, etc. [the decoding of which was previously given], indicated by the first letters of English words.

Indeed, if you take into account the translation of English words:
Alternative - alternating, alternating,
Lay-out - breakdown, markup,
Code - code
then the first letters and get "ALC".

 4. The work of the 2nd encoder encoder at time instants corresponding to transitions in the original digital signal from packs of some characters to packs of other characters.

 In this case, two characteristic cases may occur.

1. The last symbol of the packet preceding the transition coincides with the clock signal F ₃ = 0.5f ' _t [with a prime], FIG. 10a.

2. The last symbol of the burst preceding the transition coincides with the clock signal F ₄ = 0.5f _t [without dash], FIG. 10a.

Or, if we take as the reference point [t ₀ ] the time that coincides with the moment of the appearance of the first pulse of the clock signal 0.5f ' _t [with a prime], as was done when constructing the time diagrams and assume that the first packet under consideration starts at moment t ₀ , then it is possible to characterize these two cases and otherwise, namely, depending on whether the number of bits in the packet before the transition starting at the time of occurrence of the clock signal F ₃ = 0.5f ' _t [with a prime] is even, or odd.

 In the process of generating pulses of the code at the transition points, two other cases can also occur: when the code adjustment is not required and when it becomes necessary to adjust the code. Further, these cases will be considered.

The output signals of blocks 1, 2, 3 Ш2 at the time of checking the correctness of the formation of code pulses by the block П and КК should, of course, be delayed, for which purpose the delay lines LZ 26, 31, 41 are placed at the outputs of these blocks. Consideration of the features of the formation of the encoded signal when using four clock pulse sequences F ₃ ... F ₆ shows the following.

1. So, when generating pulses of the code in the places of transitions from packs of single symbols [bits] to bursts of zero bits, in case of coincidence of the last single bit of the burst with the clock signal F ₄ , correction of the received encoded signal is not required, and code decryption is provided.

If the last bit of a unit symbol pack coincides with a clock signal F ₃ , then a code pulse with a duration of 3T _{1 is} generated in the encoded signal at the transition point, the beginning of which coincides with the beginning of the pulses of the clock sequence F ₃ . In this case, the transition boundary is separated from the beginning of this code pulse by a distance equal to 2T ₁ , in this case, the code correction is not required, and its decryption is provided.

The foregoing is illustrated by the timing diagrams shown in FIG. 22b, c, which also shows the type of output voltage of the first encoder U _output Ш1 corresponding to the cases of transitions under consideration, the method of obtaining which was discussed above.

2. When generating code pulses at the points of transition from packs of zero bits to packs of single bits if the last zero bit matches the clock signal F ₄ , the transition boundary is accurately reflected in the received encoded signal, however, the period of the code pulses at the transition point is value of 3T ₁ , which degrades the frequency properties of the code [for the period of the pulse of the code must be at least 4T ₁ ].

Therefore, in this case, you need to adjust the code, for example, by forming a pulse of 3T ₁ duration, the beginning of which coincides with the signal "F ₆ ", while the code is decrypted.

If the last zero bit of the burst coincides with the signal of the clock frequency F ₃ , a pulse with a duration equal to 1T ₁ arises in the received encoded signal at the transition point, which also degrades the frequency properties of the code, and the transition boundary is not exactly decrypted. Therefore, a code correction is required here [using a code verification and adjustment block], which can be carried out, for example, by forming a code pulse of 3T ₁ duration at the transition point, the beginning of which coincides with the beginning of the clock signal F ₅ with a transition boundary at a distance equal to 1T ₁ from its beginning. The foregoing is illustrated by the timing diagrams shown in FIG. 22g, d, which also shows the type of output voltage of the first encoder, corresponding to these cases.

3. When generating code pulses in the places of transitions from packets of alternating bits to packets of zero bits, if the last single bit of a packet of alternating bits coincides with a clock signal F ₄ , then two code pulses with a duration of 2T are formed at the transition point ₁ , following each other with a period equal to 3T ₁ , which for this reason affects the frequency properties of the code. In this regard, a code correction is required, for example, by generating a pulse at the transition point with a duration of 3T ₁ , the beginning of which coincides with the beginning of the clock frequency signal F ₄ , with a transition boundary located at a distance of 2T ₁ from its beginning, which is not difficult to take into account when subsequent code decryption. This pulse replaces two code pulses in the transition zone, which were present there before the code correction.

If the last single bit of the packet of alternating bits coincides with the signal of the clock frequency F ₃ , then a pulse with a duration of 1T _{1 is} generated at the transition point when generating the code according to the considered method, which also degrades the frequency properties of the code, therefore, in this case, correction is also required code before sending it to the communication line, for example, by forming a site code transition pulse duration equal to 3T ₁ whose beginning coincides with the beginning of a clock signal frequency F _3, with the transition boundary, is located constant distance equal to 2T ₁ from the beginning, it is not difficult to consider when decryption code.

 The foregoing is illustrated by the diagrams shown in FIG. 23 b, c.

4. When generating code pulses in the places of transitions from packets of zero bits to packets of alternating bits, if the last zero bit of the packet is a signal of clock frequency F ₄ , then code correction is required, as can be seen from the diagrams of FIG. 23g, for example, by forming a correction pulse with a duration of 4T ₁ at the transition point, the beginning of which coincides with the clock signal F ₆ , as shown in FIG. 23g The transition boundary is located inside this pulse at a distance equal to 1T ₁ from its beginning, which is also not difficult to take into account when decoding the code if there is a similar frequency grid forming unit in the decoder [as in the encoder], which also includes a generator with a pulse repetition period equal to 1T ₁ .

If the last zero bit of the packet coincides with the signal of the clock frequency F ₃ , a pulse with a duration equal to 3T _{1 is} formed at the transition point, the beginning of which coincides with the signal of the clock frequency F ₅ , i.e. as with the correction pulse shown in FIG. 22d, therefore, an adjustment is necessary here, for example, by generating a pulse of duration not 3T ₁ but 4T ₁ [Fig. 23d].

 5. In the process of generating code pulses in the places of transitions from packs of single bits to packets of alternating bits and vice versa, you can do without correcting the code in all four cases, because the frequency properties of the code do not deteriorate and code decryption is provided.

The foregoing is illustrated by the timing diagrams shown in FIG. 24b, c, d, d. These diagrams, as previously shown, also show the type of output voltage of the first encoder U _output Ш1, corresponding to the cases of transitions under consideration, the method of obtaining which was discussed above.

 Compared with the two-phase code with a half pulse length [HPDB code], taken as a prototype, the proposed code according to the method of its generation [discussed above] is, by analogy with the prototype, a three-phase code, and not with half, but with the full pulse length, equal to the duration of one bit of the original digital signal [or more at the transition points], which, of course, improves the frequency properties of the encoded signal.

 The allocation of individual packets of different symbols in the original digital signal allows you to increase the correlation between the pulses and thus facilitates the search and elimination of individual errors that are possible when transmitting the code.

 This is also facilitated by the fact that corrective pulses can be formed in such a way that the appearance of each of them will indicate which particular symbols in the source digital signal are being transferred to in a particular case.

As follows from the foregoing, in the encoded signal obtained according to the proposed encoding method, there are pulses of different durations that are a multiple of half the duration of one bit [but not less than the duration of one bit]: 2T ₁ , 3T ₁ , 4T ₁ [where T ₁ - half bit length].

Moreover, in the case of successive different transitions in the original digital signal, the pulses encoding them can be connected to each other, forming longer pulses, for example, of the form 6T ₁ [when two pulses merge with a duration of 3T ₁ ], or 7T ₁ [when fusion of pulses of the form 3T ₁ and 4T ₁ ].

 It should be noted that due to the appropriate choice of the types of the correcting pulses of certain transitions themselves, it is possible to avoid the appearance of unwanted durations in the code of pulses.

 We now turn to the consideration of the construction and operation of unit P and QC.

Block verification and code adjustment [block P and QC]
As previously noted, the П and КК block is intended for checking the process of generating code pulses at the places of transitions from packets of some symbols present in the original digital signal to packets of other symbols and making the necessary code corrections before sending them to the communication line, including with alternating polarity of pulses in those cases when it is required.

 The essence of the adjustment process for various types of transitions was also considered above.

 As for the specific circuit solutions for the implementation of the block P and QC, then they can be different.

 In this regard, the authors draw the attention of the examination to the fact that they declare both a method and a general block diagram of the device [and not some particular circuit implementation of the proposed device structure], which allows the encoding method to be considered.

 In the structural diagram of the device [Fig. 9], containing two encoders, there is also a block P and KK with an indication of its electrical connections with other blocks.

 The application also considered an example of a specific circuit implementation of the device, including circuit diagrams of the blocks of both encoders [Fig. 13 and 18], with the exception of block P and QC given in FIG. 18 in a general form, but with a description in the description of time diagrams [FIG. 22-24], explaining his work, which was enough to consider the nature and features of the proposed encoding method.

 Now about the construction of the scheme of the block P and QC.

 It should be noted that in order to carry out the code correction, the P and QC block must include a number of logic circuits forming together separate channels, each of which is responsible for the formation of one or another correction pulse.

 It should also be emphasized that the construction of the channel circuits of the P and QC blocks is of the same type, and therefore it is sufficient to consider the circuit implementation of one or two channels of this block.

 The circuit of each of the channels of the П and КК unit includes one or several input matching circuits providing recognition of one or another predetermined combination of code pulses, as well as two triggers, one of which forms a correction pulse of a given duration, the beginning of which coincides with the beginning of one or a different clock pulse sequence of the frequency grid forming unit.

 Another trigger generates a blocking pulse of the required duration, depending on the location of the code pulses being adjusted in the transition zone.

 This pulse should timely start blocking the outputs of the blocks of the second encoder encoder for the time necessary for the correct passage of the correcting pulse to the encoder output.

The time-coordinated action of these pulses is provided by delay lines located in the channels of the P and CC units. Schemes of the 1st and 2nd channels of the block P and KK are shown in FIG. 25. The first channel of the block P and KK contains a three-input matching circuit 44, the first input of which through the delay line 43 with a delay time equal to 1T ₂ , is connected to the output of the circuit 39 of block 3 Ш2 [Fig. 18], in which code pulses are formed, which are responsible for coding bursts of zero symbols present in the original digital signal. The second input of the matching circuit 44 is connected to the output of the clock generator f _t of the frequency grid forming unit, and the third input cx. 44 is connected to the output of circuit 25 of block 1 Ш2, in which code pulses are formed, which are responsible for encoding packets of single symbols.

The output of circuit 44 is connected to the input of the S installation of the RS flip-flop T 46, as well as through the delay line LZ 45 [with a delay time of 3T ₁ ] with the reset input of this flip-flop.

Direct output QT 46, on which a correction pulse is generated with a duration equal to 3T ₁ in this case, is connected via LZ 47 [with a delay time equal to 7T ₁ ] to the first input of the OR circuit 48, the output of which is connected to the non-inverting input of the operational amplifier ОУ 37 Ш2 .

The output of circuit 44 of unit P and KK is also connected to the input of the S installation of the RS flip-flop T 50, as well as through LZ 49 [with a delay time of 5T ₁ ] with the reset input R of this flip-flop. [recall that T ₁ is half the duration of one bit of the original digital signal].

Direct output QT 50, on which a pulse is generated blocking the operation of blocks Ш2 [with a duration equal to 5T ₁ in this case] through LZ 51 [with a delay time equal to 5T ₁ here too] connected to the first input of the OR circuit 52, the output of which is connected to the inputs of inverters 33 and 40 Ш2 [Fig. 18].

 The operation of the 1st channel of block P and QC is illustrated by the timing diagrams shown in FIG. 26, requiring no special explanation. The combination of code pulses located in the transition zone, which is corrected in the case under consideration, was previously considered [Fig. 22g]. The presence of the output pulse in the matching circuit 44 [Fig. 25] and means the appearance in the encoded signal of the combination of pulses of the code shown in FIG. 22g.

For greater clarity, consideration of timing diagrams [Fig. 25] the encoded signal on them is shown both without taking into account the total delay equal to 4T ₂ [where T ₂ is the duration of one bit of the original digital signal], and taking it into account due to the action of the delay lines LZ 26 and LZ 41 [Fig. 18].

The 2nd channel of block P and KK contains a three-input matching circuit 54, the first input of which is connected through a delay line LZ 53 with a delay time equal to 1T ₁ , with the output of circuit 39 of block 3 Ш2 [Fig. 18], in which code pulses are formed that are responsible for packets of zero characters. The second input of the circuit 54 is connected to the output of the clock frequency f _t , and its third input is connected to the output of the first encoder Ш1 of the encoder.

The output of circuit 54 is connected to the input of the installation S of the RS flip-flop T 56, as well as through LZ 55 with a delay time of 3T ₁ with the reset input R of this flip-flop.

The direct output QT 56, on which a correction pulse of 3T ₁ duration is formed, is connected through LZ 57 [with a delay time equal to 7T ₁ ] to the second input of the OR circuit 48, the output of which is connected to the non-inverting input of the OA 37 Ш2.

The output of circuit 54 is also connected to the installation input S of the RS flip-flop T 59, and also through LZ 58 [with a delay time of 5T ₁ ] with the reset input R of this flip-flop.

Direct output QT 59, on which a blocking pulse is formed with a duration equal to 5T ₁ in this case, through LZ 60 with a delay time equal to 7T ₁ , is connected to the second input of the OR circuit 52, the output of which is connected to the inputs of inverters 33 and 40 Ш2.

 The operation of channel 2 of block P and QC is illustrated by the timing diagrams shown in FIG. 27, similar in construction to the diagrams shown in FIG. 26, and therefore not requiring further explanation. Schemes of other channels of block P and QC are constructed in a similar way. All delay lines located in the block P and KK are, of course, digital, implemented, for example, on D-flip-flops, or shift registers. The encoded signal shown in FIG. 27 was previously discussed in FIG. 22d

 It should be noted that, with the help of the code verification and adjustment block, the transition points that were previously encoded by pauses can also be subjected to the correction process, if for some reason there is a need to code all transitions without exceptions only with pulses.

For example, in FIG. 28 is a diagram of the Nth channel of block P and QC, allowing the transition indicated in FIG. 22b, to encode not with a pause, but with a pulse in this case with a duration equal to 3T ₁ , the beginning of which begins with a whole bit at the end of the pulse of the clock sequence F ₃ [otherwise, coinciding with the beginning of the pulse of the clock sequence F ₄ , according to FIG. 13a].

This channel block P and KK [Fig. 28] contains a three-input matching circuit 63, the first input of which through the delay line LZ 61 with a delay time equal to 1T ₂ is connected to the output of the circuit 25 of block 1 Ш2 [Fig. 18], in which code pulses are formed, which are responsible for encoding bursts of single bits present in the original digital signal.

The second input of the matching circuit 63 is connected to the output of the first encoder, and its third input is connected through the inverter 62 to the output of the clock generator f _t .

The output of circuit 63 through LZ 64 with a delay time of 1T ₂ is connected to the first input of matching circuit 65, the second input of which is connected through the inverter 62 to the output of the clock frequency f _t , and its third input is connected to the output of circuit 39 of block 3 Ш2.

The output of circuit 65 is connected to the input of the installation S of the RS flip-flop T 67, as well as through the delay line LZ 66 [with a delay time of 3T ₁ ] with the reset input R of this flip-flop.

Direct output QT 67, on which a correcting pulse is generated with a duration equal to 3T ₁ in this case, is connected through LZ 68 [with a delay time equal to 5T ₁ ] to the first input of the OR 69 circuit, the output of which is connected to the non-inverting input of the operational amplifier ОУ 37 Ш2 .

The output of the circuit 65 is also connected to the input of the installation S of the RS flip-flop T 71, as well as through LZ 70 with a delay time of 7T ₁ with the reset input of this flip-flop.

Direct output QT 71, on which a pulse is generated blocking the operation of blocks Ш2 [duration, in this case equal to 7T ₁ ], through LZ 72 with a delay time of 3T ₁ , is connected to the first input of the OR circuit 73, the output of which is connected to the inputs of inverters 33 and 40 Ш2 [Fig. 18].

 The operation of the Nth channel of block P and QC is illustrated by the timing diagrams shown in FIG. 29, not requiring special explanation. The presence of the output pulse in the matching circuit 65 [Fig. 28] and means the appearance in the encoded signal of a combination of pulses and pauses in the transition zone shown in FIG. 22b.

Moreover, as before, when constructing diagrams [Fig. 26, 27] the encoded signal in FIG. 29 is shown both without taking into account the general delay, and taking it into account. When coding the transitions from bursts “1” to bursts “0” and vice versa with 3T ₁ pulses, and to alternating 4T ₁ pulses, _one can receive pulses of 6T ₁ and 7T ₁ duration in the encoded signal [where T ₁ is half the duration of one character of the original digital signal], as shown in FIG. 30 and 31.

A method of obtaining one or another output voltage of the first encoder U _out Ш1, taken as an example [in FIG. 30, 31] was considered earlier in the description of the application and does not require special explanations, as well as the construction of time diagrams.

Now, with regard to cases where the original digital signal L (t) will contain either one single bit inside a packet of zero bits, or vice versa, when one zero bit will be inside a packet of single bits. In both of these cases, at the output of the matching circuit 16 of the first encoder [Fig. 13] there is a single pulse with a duration equal to the duration of one bit, as previously mentioned. Timing diagrams were also given at the same time [Fig. 16 and 17], explaining these cases, from the point of view of obtaining one or another type of output voltage of the first encoder U _output Ш1.

 A view of the encoded signals corresponding to these types of output voltages of the first encoder is shown in FIG. 32, 33. The construction of time diagrams [Fig. 32, 33] taking into account the output pulses of blocks 1, 2, 3 Ш2 [these are the output pulses of circuits 25, 30, 39], obtained in accordance with the encoding method under consideration, does not require additional explanations.

From the consideration of diagrams [Fig. 32, 33] it is also seen that if there are two transitions in the original digital signal that follow in succession with an interval of one bit, the encoded signal received initially requires adjustment at the transition points. This is done, for example, by generating code pulses with a duration equal to 5T ₁ , the beginning of which coincides with the beginning of any clock sequence [as shown in FIG. 32, 33], or by, for example, encoding only one, the second transition, which is possible in cases where the form of the correcting pulses unambiguously indicates to which symbol packet one or another transition takes place.

The presence in the encoded signal of pulses with durations of 2T ₁ , 3T ₁ , ... 7T ₁ shows that the spectrum of such a code is very close to the spectrum of the Miller code.

 An even greater improvement in the frequency response of the encoded signal [v. e. narrowing the spectrum and shifting it to the low frequencies] in the proposed encoding method can be achieved by encoding all transitions between packets of different symbols only with pulses of more than one bit in duration, formed as indicated above [each of which should unambiguously determine which ones exactly symbols, a transition takes place in each case], while if the duration of the time intervals between the transition pulses does not exceed the maximum possible pulse duration of the transition s [of the order of 4 bits], then 1-bit code pulses generated between transition pulses as described above are not transmitted to the communication line at all.

 However, the issues associated with one or another code transfer to the communication line do not directly relate to the formation of the encoded signal itself according to the proposed method.

 In cases where there are bursts of symbols in the original digital signal with a duration exceeding the maximum possible duration of the generated transition pulses [taking into account the merging of pulses of closely spaced transitions among themselves], in the time intervals corresponding to these packs, pulses of duration exceeding the duration of one symbol are formed between transition pulses the original digital signal and a multiple of half bits differing from other generated pulses either in their duration or in the time position method, the beginning of which coincides with the beginning of any clock sequence and the number of which is determined by the duration of the processed symbol pack, and these pulses are transmitted to the communication line only when there can be between them and the transition pulses, or if there are several of them a pause is formed with a duration of at least one character on each side of the indicated pulses.

In this case, the shortest pulse duration of the code in the above cases is not 2T ₁ [as in the Miller code], but 3T ₁ [i.e. one and a half times larger], and therefore the spectrum of such an encoded signal will be about one and a half times narrower, as shown in FIG. 6 [curve under the index M '].

 The outputs of blocks 1, 2, 3 of the second encoder Ш2 during the implementation of this method of code transmission are blocked by applying a signal to the inputs of inverters 33 and 40 Ш2. The output signals of circuits 25, 30, 39 Ш2 are used in this case only for recognition of the corresponding combinations of pulses in the transition zone with the subsequent formation of certain pulses in the time intervals between transition pulses, when necessary.

 Implementation of the proposed method of encoding digital signals using a computer. As already noted, encoder encoder circuits can be performed using only discrete elements of digital technology [triggers, AND, OR circuits, etc.] and what was discussed above, or using directly the arithmetic logic device [ALU] or microcomputer.

 A block diagram of a device that implements the proposed encoding method, including ALU, is shown in FIG. 34 and contains a block for forming the frequency grid of the FSF 1, the input of which is connected to the first input of the ALU 2, which is the input of the device, and the output is bl. FSH 1 is connected to the second input of ALU 2.

 The output of ALU 2 is connected to the input of the output unit [output. bl. 4], the output of which is the output of the device. ALU 2 is connected by two-way communications with read-only memory ROM 3, so ALU 2 and ROM 3 are essentially a microcontroller, with the mutual exchange of information between the ALU and ROM units.

 The block for forming the frequency mesh of the FSF 1 is made similarly to the same block included in the circuit of the first encoder encoder, discussed earlier. The purpose of the output unit was also discussed above. The operation of the clock generator of the FSF 1 is synchronized with the digital sequence L (t), for which the input of the FSF 1 is connected to the input of the device.

 Timing diagrams of the clock pulse sequences generated by the block of the FSF 1 were considered earlier [Fig. 10].

 The device [Fig. 34] works as follows.

Before starting work in all the memory cells of the data register "A" and all other registers [except for register P ⁰ , fixing packets of zero characters], in which the results of processing the input digital sequence L (t) will be entered, zeros are set. As for the register P ⁰ , in its first few cells [depending on the processing algorithm, on which the initial delay time determined by the number of bits will depend] in the low bit D _{0 are} written before the unit starts, and zeros are written in the remaining memory cells . More details about the work of ALU and about filling the memory cells of various registers will be discussed later.

 1st stage of ALU work.

So, the incoming digital sequence L (t) arriving at the first input to the ALU [Fig. 34], is recorded in the low-order bit D ₀ of the memory cells of the data register "A", and each cell corresponds to one bit.

The order of filling the memory cells a _i of the data register "A" is shown in FIG. 35 for the case of an arbitrarily taken as an example digital sequence L (t) containing a packet of 3 single characters, a pack of 4 alternating characters, a pack of 3 zero characters and a stack of 2 single characters located behind it also shown in FIG. 35.

 At the same time, as will be seen from consideration of the proposed ALU operation algorithm for the correct processing of a digital sequence for the allocation of packets of various symbols [single, zero, alternating] in it, i.e. To analyze the belonging of the next considered bit to one or another packet, it is necessary to know information about 3 bits of the sequence L (t).

In this regard, the recording of the 1st unit bit L (t) corresponding to the time t ₀ conditionally taken as the reference point of the sequence L (t) received at the input of the device is performed in the 4th memory cell a ₄ of the data register "A", whereas in the first three cells in the low bit D _{0 of} this register zeros will be written.

 2nd stage of ALU work.

This step is turned on in the processing of the contents of the data register "A" with the results of this processing recorded in registers in which the presence in L (t) of either packets of zero bits [register P ⁰ ] or packets of single bits [register P ¹ ] is recorded.

 The order of filling the memory cells of these registers for the case of the digital sequence L (t) considered as an example is also shown in FIG. 35.

At the same time, we note that by a pack of zeros or ones we mean two or more zero or single characters following in a row. If this condition is not met, then one or another character of the digital sequence is considered to belong to a pack of alternating characters, which reflects the recording of information in the registers P ⁰ and P ¹ [Fig. 35], because at time instants corresponding to a packet of 4 alternating bits, zeros remain in the memory cells of the registers P ⁰ and P ¹ . Note that this feature allows you to select a packet of alternating bits in the sequence L (t) by comparing the contents of the memory cells of the same register numbers P ⁰ and P ¹ .

The case when one of the characters L (t) is located inside a pack of characters opposite to it [t. e. or ... 0,0,1,0,0, ... or ... 1,1,0,1,1,. . .] will correspond to the simultaneous presence of zero in the bit D _{0 of} only one of the memory cells of the registers P ⁰ and P ¹ .

It should be noted that if the recording of the sequence L (t) in the data register "A" was synchronized by the clock sequence of the block for forming the frequency grid of the FSF 1 [Fig. 34], previously designated by F ₂ , having a pulse repetition period equal to the duration of one bit L (t) [Fig. 10], then the reading of information from the memory cells of the register R containing the results of processing the registers P ⁰ and P ¹ should then be carried out in accordance with the clock sequence of the FSF block 1, previously indicated by F ₁ [Fig. 10], having a pulse repetition period equal to the duration of half a bit.

 The foregoing is carried out using the ALU operation algorithm presented in the upper part of the flowchart [Fig. 36], which includes entering into memory the next symbol L (t), denoted by a [i], and then checking that two conditions are fulfilled [or not fulfilled], namely, whether the symbol a [i-1] preceding it belongs to a unit pack , or a bunch of zeros. If none of these conditions is met, then this will mean that the character a [i-1] belongs to a stack of alternating characters.

 Explanations of the notation used in the block diagram of the ALU operation algorithm [Fig. 36].

 By a [i] the i-th memory cell of the data register "A" is designated. The following characters are also used.

 1. Equal sign =, which is used when checking the fulfillment of any conditions.

2. Assignment mark: =, which is used when a character indicated after this is entered into a cell or a log. 0, or a log. 1
For example, the entry a [i] = 1, means that in the condition checking block the contents of this cell are compared with the log. 1, whereas the notation a [i]: = 1, means that the cell a _i needs to be assigned a log. 1 [i.e. put "1" in this cell].

Or, for example, the entry p ¹ [i-1]: = 1, as well as the entry p ⁰ [i-1]: = 1 mean that in the first case the log. 1 is assigned to the memory cell [i-1] of the register P ¹ , and in the second, the same cell of the register P ⁰ . Recall that in the registers P ¹ and P ^{0, the} units of units and the units of zeros present in L (t) are fixed, respectively. Thus, after entering the value a [i], which is responsible for the i-th character of the original digital sequence L (t), the entry: a [i-1] = 1 and (a [i-2] = 1 or a [i] = 1),
means checking the condition: whether bit a [i-1] belongs to a pack of single characters or not.

Further, in the ALU operation algorithm [Fig. 36], the condition is checked: a [i-1] = 0 and (a [i-2] = 0 or a [i] = 0),
meaning whether bit a [i-1] belongs to a packet of zero characters or not.

 Based on the foregoing, it is easy to notice that the upper part of the ALU operation algorithm flowchart [Fig. 36] meets the functional features of the 1st encoder encoder, discussed in detail earlier.

Moreover, as already noted, the simultaneous presence of zeros in the same numbers of memory cells of the registers P ⁰ and P ¹ will mean that the symbol L (t) recorded in these cells belongs to a packet of alternating bits.

When encoding, such an integer attribute as 0.5 bits is used. This is expressed in the fact that two new cells of the result R are mapped to the cell a _i , which is reflected by a record of the form: R [2i-1], R [2i].

Similarly to cell a [i-1], two cells are mapped:
R [2 (i-1) -1], R [2 (i-1)].

 For cell a [i-2], the entry has the form: R [2 (i-2) -1]; R [2 (i-2)], etc.

As indicated, the R register is a register that stores the results that go to the output of the encoder. In view of the above, the first cell in the R register will be allocated two others, denoted below by r - small, and under the numbers 1 and 2, i.e. r ₁ and r ₂ .

Similarly to the second cell [t. e. for i = 2] two others are put in correspondence: R [2 • (2) -1], ie r ₃ and R [2 • (2)], i.e. r ₄ etc.

The registers P ^1.1 , P ^0.0 , P ^1.0 , P ^0.1 are shown in FIG. 37 and 39 for a more visual examination of the coding features of various types of transitions [it is not necessary to reflect them in the ALU operation algorithm] and we will talk about them later.

 3rd stage of ALU work.

It is turned off in processing the contents of the registers P ⁰ and P ¹ , which contain information about the presence in the digital sequence L (t) of packets of zero and single characters, respectively, as well as the number of bits themselves in these packets. Moreover, as already noted, by comparing the contents of the same memory cells of these registers [in which zeros are present], information can also be obtained on the presence in the digital sequence of packs of alternating characters and their number in these packs.

After analyzing the contents of the registers P ⁰ and P ¹ , the transitions between the detected bursts are encoded according to a predetermined law and only by pulses [as described above in the application description in detail], which is carried out according to the flowchart presented in the lower part of FIG. 36.

 In this case, the record of transitions in the algorithm is reflected as follows.

For example, if the beginning of a pack of zeros comes from cell a [i-2], then this is checked as follows:
p ⁰ [i-3] = 0 and p ⁰ [i-2] = 1
If on the contrary, for example, a unit of single characters would start from cell a [i-2], then this is checked as follows:
p ¹ [i-3] = 0 and p ¹ [i-2] = 1
Or, for example, the fulfillment of a condition of the form:
p ⁰ [i-3] = 1 and p ⁰ [i-2] = p ¹ [i-2] = 0,
means that from the character L (t) recorded in cell a [i-2], a pack of alternating characters begins, and from a single bit, because p ⁰ [i-3] = 1. At the same time, compliance with the conditions of the form: p ⁰ [i-1] = 0, means that this packet of alternating bits does not consist of one bit, while in the presence of the condition p ⁰ [i-1] = 1, taking into account the other above conditions, this would mean that in the original digital sequence L (t) in this place, one single character is located inside the packet of zero characters [... 0,0,1,0,0 ...].

 Formally, such a symbol [bit] is perceived as a "pack" of alternating bits of one bit length, which results in the presence of two transitions located one after another with an interval of one bit. A similar situation can naturally arise in the case of the presence of a single zero bit among a pack of single characters [... 1,1,0,1,1 ...]. As already mentioned, two transitions that follow with an interval of 1 bit are also encoded by one correcting pulse [like other transitions] with a duration different from the durations of pulses encoding other transitions. Moreover, under certain conditions, depending on the selected type of pulses encoding transitions in a normal situation [i.e. with an interval between them of 2 bits or more], it is possible to encode only one [second] transition, if they are located with an interval of 1 bit.

It should be noted that when processing the contents of the register P ⁰ and P ¹ two characteristic cases can occur:
3.1. Only transitions between bursts of different symbols are encoded, while time intervals between transitions by pulses of clock sequences are not encoded.

 3.2. Not only are transitions encoded between bursts of one or another symbol encoded, but also time intervals are encoded [on certain conditions] between transitions using pulses of clock sequences.

 Both of these cases were considered for the schemes of the 1st and 2nd encoders, executed only on discrete logic elements, from which the application was started, because in this case the features of the proposed encoding method were most clearly visible.

 Now, these 2 cases will be considered in relation to encryptors implemented using ALU or microcomputers.

 3.1. Transition coding only.

 It is carried out using the ALU operation algorithm presented at the bottom of the flowchart shown in Fig. 36.

 It contains four blocks for verifying the fulfillment of certain conditions, which mean when considering them from top to bottom.

1st block of verification of conditions:
p ⁰ [i-3] = 0 and
p ⁰ [i-2] = 1
means checking for a jump to a packet of null characters starting with bit a [i-2].

2nd block of verification of the fulfillment of conditions:
P ¹ [i-3] = 0 and
P ¹ [i-2] = 1
means checking for a transition to a pack of single characters from bit a [i-2].

3rd block to verify the fulfillment of the conditions:
p ⁰ [i-3] = 1 and
p ⁰ [i-2] = p ¹ [i-2] = 0 and
p ⁰ [i-1] = 0
means checking for a transition to a pack of alternating characters of the form: 1,0,1 ..., i.e. starting with a single bit.

4th unit for verifying the fulfillment of conditions:
p ¹ [i-3] = 1 and
p ⁰ [i-2] = p ¹ [i-2] = 0 and
p ¹ [i-1] = 0
means checking for a transition to a pack of alternating characters of the form: 0,1,0 ..., i.e. starting with a zero bit.

 If the conditions specified in the blocks are met, one or another type of pulse encoding the transitions selected in advance will be implemented according to the algorithm written to the right of each condition checking block [Fig. 36].

 The filling of the memory cells of the respective registers, the contents of which shows how the transitions are specifically encoded for the case of the sequence L (t) containing four transitions considered as an example, is shown in FIG. 37.

Moreover, in the register designated by P ^1,1 [Fig. 37], the filling of bit D ₀ of memory cells in the places of transitions to packs of single characters is shown according to the coding order of such transitions considered earlier in the application, namely, with a pulse having a duration equal to 3T ₁ starting from 0.5 bit = T ₁ [where T ₁ is a period of a clock signal indicated in FIG. 13 through F ₁ ], with a transition boundary that is 0.5 bits apart from the beginning of this pulse.

In the register P ^0,0 [Fig. 37] shows the filling of bit D _{0 of} this register at the places of transitions to packets of zero symbols, and the transition itself is encoded here by a pulse having a duration also of 3T ₁ , but starting from a whole bit, with a transition boundary spaced apart from the beginning of this pulse, equal to 2T ₁ .

In the register denoted by P ^0.1 [Fig. 37], the filling of bit D ₀ is shown in the case of the presence in L (t) of a packet of alternating symbols starting with a zero symbol. Such a transition is encoded by a pulse of 4T ₁ duration with a transition boundary that is 2T ₁ away from its beginning. The encoding of bursts of alternating characters, but starting with a single character, is fixed in the register denoted by P ^1,0 and since there are no such bursts in the digital sequence taken as an example, zeros are stored in this register in all cells [Fig. 37].

 In more detail, the features of the formation of transition pulses have already been considered in the application description earlier.

 In the register designated by "R" [FIG. 37] shows the resulting pattern of filling the memory cells, reflecting all the transitions that were in the considered sequence L (t).

 As already mentioned, when encoding transitions and intervals between them, two memory cells are allocated to the registers for each bit of the original digital sequence, which reflects the contents of the registers [Fig. 37]. For clarity, in FIG. 37, the filling of the memory cells of the data register "A", which was discussed earlier, was also repeated.

 In view of the foregoing, it can be seen that the lower part of the block diagram of the ALU operation algorithm [Fig. 36] meets the functional features of the 2nd encoder encoder, also already considered in the description of the application.

 3.2 Coding of both transitions between packs and time intervals between them, which are a continuation of particular packs. This case corresponds to the complete block diagram of the ALU operation algorithm, including the determination of packets of various symbols in the original digital sequence, and the coding of transitions between detected packets [all of which are discussed above], and the coding of time intervals between transition pulses, according to the operation algorithm, shown in FIG. 38, which is a continuation of the algorithm shown in FIG. 36.

 The complete block diagram compared to the block diagram [FIG. 36] contains three additional blocks for checking the corresponding conditions indicated in them, upon fulfillment of which the program given to the right of these blocks is implemented [Fig. 38].

В качестве примера на фиг. 39 рассматривается заполнение содержимого этого регистра, а также и других регистров [ранее упомянутых] для случая кодирования цифрового сигнала, содержащего пачку из 7 единичных символов и следующую за ней пачку из трех нулевых символов, обозначенного через L'(t).At the same time, two more registers are added to the registers mentioned earlier, which are included in the device for implementing the proposed encoding method. In one of them, denoted by P _F3 [Fig. 39], write the clock pulse sequence F ₃ having the form shown earlier in FIG. 10. This sequence is entered into the register P _F3 by alternately assigning to the cells of this register either log 1 or log. 0, as indicated by the block [Fig. 38], in which is written:

As an example in FIG. 39, filling out the contents of this register, as well as other registers [previously mentioned], is considered for the case of encoding a digital signal containing a packet of 7 single characters and a subsequent packet of three zero characters, denoted by L '(t).

As for the clock pulse sequence, denoted by F ₅ [Fig. 10] and shifted in time relative to the sequence F ₃ by an interval equal to half one bit, this sequence can be obtained, in particular, from the existing sequence F ₃ [for which a separate register is reserved], but it is possible to select for the sequence F ₅ its register P _F5 [as shown in FIG. 39].

It should also be noted that the pulses of the clock sequences in the case of coding of the intervals between the transition pulses should neither coincide [or add] with these pulses nor be close to them, that is, with an interval equal to 1T ₁ , while this interval must be at least 2T ₁ .

 To comply with the above, it is required that, firstly, the distance between the end of the previous transition pulse and the beginning of the next pulse of a particular clock sequence be at least one bit long, and secondly, the distance between the end of each pulse used to encode the clock sequence and the beginning of the next transition pulse would also be no less than the duration of one bit of the original digital sequence.

Since in order to fulfill these conditions it is necessary to know the location of both the previous and subsequent transition pulses [obtained in the encoding process], then, taking into account the pulse duration of the clock sequences themselves, equal to 2T ₁ , placed between the transition pulses, in fact, when processing a digital sequence in this case, the initial delay should already be provided not in three bits [as in the first case when coding only one transitions], but in five bits, which reflects as a block diagram of the algorithm ALU bots [Fig. 38], as well as the contents of data register "A", which shows the filling of its memory cells for the case of the digital signal L '(t) in question [Fig. 39].

 In FIG. 39 also shows the filling of the memory cells of various registers, fixing the presence of transitions in this sequence L '(t), respectively, to packs of units, packs of zeros and packs of alternating characters.

 The final result of all processing is shown in the contents of the memory cells of the register "R" [Fig. 39].

 The block diagram of the ALU operation algorithm [Fig. 38] contains three blocks to verify compliance with the relevant conditions.

So, one of the condition check blocks in which it is written:
p ¹ [i-5] = 1 and f ₃ [i-5] = 1 and
R [2 (i-6) -1] = R [2 (i-6)] =
R [2 (i-4) -1] = R [2 (i-4)] = 0
means, firstly, checking whether there is a pulse of frequency f ₃ for the bit [i-5] and whether this bit belongs to a pack of units, and secondly, the condition of the presence of a free interval to the left and to the right of it is also checked at a distance equal to 2T ₁ .

 When these conditions are met, the program is implemented, which is shown to the right of this condition check block, i.e. register cells "R", designated as R [2 (i-5) -1] and R [2 (i-5)] are assigned a log. 1. In the next block [Fig. 38], conditions similar to the aforementioned block are checked, but already for the membership of the checked bit in a packet of zeros.

 In the last of these blocks [Fig. 38] there is a check of similar conditions, but already on the belonging of the bit in question to the original digital sequence, a pack of alternating characters, etc.

 It should be noted that the execution of all logic elements included in the encoder circuitry and other circuit elements, their implementation, is known, for example, from the reference book (V.L. Shilo. Popular digital microcircuits. Chelyabinsk: Metallurgy, 1989).

Claims (4)

 1. A method of encoding digital signals, which consists in processing the original digital signal with a clock signal ft, characterized in that the original digital signal is delayed, the original digital signal is compared to the delayed digital signal, and bursts of "1", "0" are detected in the original digital signal alternating "1" and "0", which are converted into a three-level pulse signal in the form of positive pulses, negative pulses and zero signal values with durations equal to the durations of bursts "1", "0" and alternating "1" and "0", with Responsibly, they form four clock pulse (TI) sequences with a pulse repetition rate of 0.5 ft equal to the frequency of alternating "1" and "0" of the original digital signal, which are shifted in time relative to each other at intervals multiple of T1, where T1 is half the duration of one symbol of the original digital signal, and the duration of pulses and pauses of four TI sequences is 2T1, form an encoded signal by converting a three-level pulse signal using four TI sequences moreover, at the places of transitions from one burst of pulses to bursts of pulses of a three-level pulse signal, positive code pulses or pauses are generated, shifted to one side or another from the transition point with durations longer than 2T1 of the original digital signal and multiples of T1, and the beginning of the formed positive pulses coincides with the beginning of one or another TI sequence, in the case when code pulses of duration equal to T1 or pulses are received at the places of transitions when processing a three-level signal code following each other with an interval of duration equal to T1, 2T1 or 3T1, in the places of transition from packs "0" to packs "1", the code is adjusted by generating positive pulses of 3T1 duration, the beginning of which is shifted to T1 to the left of the place the transition to coincidence in time with the beginning of the pulses of one of the two inverse TI sequences coinciding with the middle of the symbols of the original digital signal, in the places of transition from bursts of alternating "1" and "0" to bursts "0", the code is adjusted by forming 3T1 pulses of duration, the beginning of which is shifted 2T1 to the left of the transition point until one of the two inverse TI sequences coincides with the beginning of the pulses, coinciding with the beginning of the symbols of the original digital signal, and in the places of transition from bursts "0" to alternating bursts “1” and “0” correct the code by generating positive pulses of 4T1 duration, the beginning of which is shifted by T1 to the left of the transition point until it coincides in time with the beginning of any of the two inverse TI sequences, which give the middle symbol of the source digital signal, and if there are two transitions in a three-level pulse signal processed in succession with an interval of 2T1, positive impulses are formed in the places of their transitions with a duration exceeding the duration of the pulses of other transitions that is a multiple of the number T1, the beginning of which coincides with beginning with any TI sequence, the generated pulses are additionally delayed for a time equal to the maximum possible duration of the transition pulses, the duration is analyzed these time intervals between transition pulses, and if the duration of the intervals does not exceed the maximum possible duration of transition pulses, then pulses of positive polarity of 2T1 duration are formed in these intervals, and if bursts of "1" follow after the transition pulses, then this pulse of 2T1 duration is generated at time instants, in which the positive pulses of the three-level pulse signal coincide with the pulses of the first TI sequence, if bursts of transitions are followed by bursts of alternating "1" and "0", then the specified pulse of 2T1 duration is generated at those times when the pulses of the zero level of the three-level signal coincide with the pulses of the second TI sequence, inverse to the first TI sequence, and if bursts follow the bursts, then "0" , then form a positive pulse with a duration of 2T1 at those times when the negative pulses of the three-level signal coincide with the pulses of the third TI sequence shifted relative to the first TI sequence by an interval equal to T1 of the initial digital signal, if there are bursts of certain symbols in the digital signal that are longer than the possible duration of the generated transition pulses, in the time intervals corresponding to these packs, positive pulses are formed between the transition pulses with a duration exceeding the duration of 2T1 of the original digital signal and a multiple of T1, which differ from other generated positive impulses either in duration or in temporary position, the beginning of which coincides with the beginning of which or TI sequences and the number of which is determined by the specific duration of the processed symbol pack.  2. The method according to p. 1, characterized in that in the case of processing the original digital signal by hardware using discrete elements of digital technology, the digital signal is preliminarily delayed by one bit of the digital signal before processing, and in subsequent processing operations it is delayed for another time equal to the maximum possible duration of the generated transition pulses.  3. The method according to claim 1, characterized in that in the case of processing the initial digital signal using software devices using computers, the digital signal is delayed immediately by a time equal to or greater than the maximum possible duration of the transition pulses generated during processing.  4. A device for encoding digital signals containing a first encoder and a clock, the inputs of which are interconnected and are the input of the device, characterized in that the first encoder is made in the form of a delay line, a block for forming a frequency grid, series-connected block processing unit of alternating "0 "and" 1 ", unit processing unit" 1 "and unit processing unit" 0 "and the adder, to the other input of which the output of unit processing unit" 1 "is connected, while the input of the clock generator is connected to the first inputs of the processing unit ki of packs "1" and a unit for processing packs of alternating "1" and "0" and through the delay line - with the second input of a unit for processing packs "1" and a unit for processing packs of alternating "1" and "0", to the third inputs of which the first the output of the frequency grid forming unit, to the input of which the output of the clock generator is connected, and the other output of the processing unit of bursts of alternating "1" and "0" is connected to the corresponding input of the processing unit "0", the output of the adder is connected to the input of the entered second encoder, which input floor processing unit included life pulses (PI), a block for processing zero signal values (NC), a block for processing negative pulses (OI) and a code correction unit, the first outputs of a processing unit PI, a processing unit for NCS and a code correction unit are connected to the corresponding inputs of the resolution block, the output of which, the second output of the correction unit and the first output of the OI unit are combined and connected to the input of the output unit, designed to coordinate the output signal with the communication channel, in addition, the second outputs of the PI processing unit, the NZS processing unit, and the unit OI processing units are connected to the corresponding inputs of the code adjustment unit, the third output of which is connected through the OI processing unit to the corresponding input of the UI processing unit, and the corresponding outputs of the meshing unit are connected to the clock inputs of the ladies of the UI processing unit, the NZS processing unit, the OU processing unit and the correction unit frequencies.

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