RU202507U1 - Digital harmonic signal generator - Google Patents

Abstract

The utility model relates to digital converting equipment and can be used to synthesize a digital harmonic signal in processing systems for angular position sensors of AC and DC electric drives. The technical result is an increase in the accuracy of reproduction of a digital harmonic signal (for example, sinusoidal). The digital harmonic signal generator contains a clock generator of rectangular pulses of a fixed frequency 1, a master generator of multiple frequencies 2, consisting of dividers-counters of a binary code, a k-bit counter of a binary code 3, a three-digit counter of a binary code 4, a logic block 5, a four-channel gate 6, ( k + 5) -bit counter of binary code 7, a set of (k + 4) -two-input adders 8 modulo two.

Description

The utility model relates to digital converting equipment and can be used to synthesize a digital harmonic signal in processing systems for angular position sensors of AC and DC electric drives.

Known digital generator of sinusoidal signals (RF Patent No. 2670028, Н03В 19/00, publ. 10/17/2018, BIPM No. 29), which uses digital formation of a symmetrical sinusoid with the ability to increase the output signal capacity.

However, in this device, as the bit depth increases, the error between the generated code and the exact value of the digital code of the sinusoid increases due to the fact that the piecewise linear reproduction of the digital code at the generator output differs from the nonlinear digital value of the sinusoid.

The technical result obtained during the implementation of the claimed utility model is expressed in increasing the accuracy of reproduction of a digital harmonic signal (for example, sinusoidal).

This is achieved by the fact that a master multiple frequency generator is introduced into the digital harmonic signal generator device containing a clock generator, the input of which is connected to the clock generator, the output of the multiple frequency master oscillator is connected to a binary code pulse counter and the outputs are connected to the first inputs of the four-channel gate, the senior the discharge from the output of the counter of the pulses of the binary code is fed to the input of the three-bit counter of the binary code, the outputs of which are fed to the logic block, the outputs of which are connected to the second inputs of the four-channel gate, the output of which is connected to the input of the binary pulse counter, the senior bit of the counter is fed to all the second inputs of the two-input digital adder modulo two, and the outputs of the least significant bits of the counter go to the first inputs of the adder, the output code of which determines the digital harmonic signal.

FIG. 1 shows a block diagram of the proposed device; in fig. 2 - electrical block diagram of the master generator of multiple frequencies; in fig. 3 is a diagram of the operation of the master generator of multiple frequencies, FIG. 4 is a diagram of the operation of the proposed device.

The digital harmonic signal generator (Fig. 1) contains a clock generator of rectangular pulses of a fixed frequency 1, a master generator of multiple frequencies 2, consisting of dividers-counters of a binary code 9, 10, 11, 12, a k-bit counter of a binary code 3, a three-digit counter of a binary code 4, logical block 5, four-channel gate 6, (k + 5) -bit counter of binary code 7, a set of (k + 4) -two-input adders 8 modulo two.

The proposed device works as follows.

Pulses of stable frequency ƒ _Т = const from the clock generator are fed to the input of the master generator of multiple frequencies, which generates signals with frequencies ƒ = ƒ _Т / 12, 2ƒ = ƒ _Т / 6, 3ƒ = ƒ _Т / 4, 4ƒ = ƒ _Т / 3 , which are fed to the first inputs of the four-channel gate 6. The output of the divider-counter of binary code 9 equal to ƒ = ƒ _T / 12 is fed to the input of the k-bit counter of binary code 3, the most _{significant bit a k of} which is fed to the input of the three-digit counter of binary code 4, outputs a ₁ , a ₂ , and _{3 of} which are the inputs of logical block 5, at the output of which four signals q ₁ , q ₂ , q ₃ , q _{4 are formed} , represented by the following dependencies:

which are fed to the second inputs of the four-channel gate 6. Gate 6 forms at its output an alternating sequence of pulses with a frequency of ƒ and ƒ / 2, which is fed to the input of a binary counter of pulses 7 with a width of 2 ^{k + 5} , from the lowest (k + 5) outputs a digital the code of half the period of the sinusoid, which is fed to the first inputs of the (k + 5) -two-input adders 8 modulo two. _{The high-order bit b k + 5 of the} counter 7 is supplied to the second inputs of the adder 8 to form the second half of the sinusoid.

Thus, on the buses of the output signal, a digital code appears at ₁ , at ₂ , ..., at _{k + 2} , at _{k + 3} , at _{k + 4} with a change law close to the reproduction of a harmonic signal (for example, sinusoidal), the frequency of which is linear is related to the clock generator frequency and is equal to ƒ _T / 12⋅2 ^{k + 4} .

All transformations in the device are performed in a discrete form and a complete implementation in an integrated version is possible.

Claims (1)

A digital harmonic signal generator containing a clock generator, characterized in that a multiple frequency master oscillator is introduced into it, the input of which is connected to the clock generator, the output of the multiple frequency master oscillator is connected to a binary code pulse counter and the outputs are connected to the first inputs of the four-channel gate, high-order bit from the output of the counter of the pulses of the binary code is fed to the input of the three-bit counter of the binary code, the outputs of which are fed to the logic block, the outputs of which are connected to the second inputs of the four-channel gate, the output of which is connected to the input of the binary pulse counter, the senior bit of the counter is fed to all the second inputs of the two-input bit-by-bit adder modulo two, and the outputs of the least significant bits of the counter go to the first inputs of the adder, the output code of which determines the digital harmonic signal.

Images