RU2040778C1 - Method of measurement of sizes of particles and device for its realization - Google Patents

Abstract

FIELD: measurement technology. SUBSTANCE: this method provides for additional measurement of duration of trailing edge of signal from particle. Description of invention presents formula for determination of size of particle and specifies device for implementation of method. EFFECT: increased accuracy of determination of size of particle and reduction of random error in result. 2 cl, 9 dwg

Description

 The invention relates to methods for monitoring the parameters of objects, more specifically to methods for determining particle sizes, and can be used to determine particle size, particle size and concentration in powders, suspensions and aerosols, to control technological processes using these materials in biomedical research, as well as to control the contamination of liquids, in particular, in environmental studies.

 Known methods for determining the distribution of particle sizes by the angular distribution of scattering intensity, as well as by fluctuations in the scattering intensity of laser radiation as a result of Brownian motion [1] These methods have low accuracy, and their implementation requires complex, expensive equipment.

, (1) где a_изв длина проекции частицы на направление движения частиц;
l длина зоны измерения в направлении движения;
τ_пф длительность переднего фронта сигнала от частицы;
τ_в длительность вершины сигнала от частицы.Closest to the proposed one is a method of determining particle sizes [2] intended for the study of dispersed particles in a two-phase flow, which consists in the fact that a measuring zone is formed in the studied flow using a radiation beam, exceeding the maximum particle size, and pulse signals arising when the particles cross the measurement zone, in particular, the durations of the leading edge and the apex of each pulse are measured. The magnitude of the projection of the particle on the direction of motion is determined using the formula
a _reference =

(1) where a length of the projection _keV particles in the direction of particle motion;
l the length of the measurement zone in the direction of movement;
τ _{pf the} duration of the leading edge of the signal from the particle;
τ _{in the} duration of the peak of the signal from the particle.

 The specified method has insufficient accuracy, since the calculation of the particle size is based on measuring the duration of two elements of the signal: its leading edge and vertex. In this case, the influence of interfering factors causing a random error in measuring the duration of the leading edge and the peak of the signal is fully affected. Such influencing factors include fluctuations in the radiation intensity and its spatial distribution, fluctuations in the particle velocity vector and noise processes in the measuring equipment.

 This method is implemented on a device consisting of a radiation source, a transmitting forming system, a scanning unit, for example, in the form of a flow cell with a pumping system, a receiving forming system, for example, in the form of a diaphragm, a radiation receiver, an analog-code pulse-width converter, representing is a set of n comparison blocks with predetermined levels of discrimination, a reference voltage source that specifies the specified n levels, and a computing unit connected to a radiation receiver and converts the latitudinal mpulsny code in a form suitable for calculating and generating calculation by formula (1), wherein one input of each comparator connected to the output of the radiation receiver, and the other input of each comparator unit with a reference voltage source outputs.

 The aim of the invention is to increase the accuracy of determining particle sizes, in particular, to reduce the random error of the result.

, (2) где a размер частицы, определяемый как длина ее проекции на направление движения частиц;
l длина зоны измерения в направлении движения частиц;
τ_пф длительность переднего фронта сигнала;
τ_в длительность вершины сигнала;
τ_зф длительность заднего фронта сигнала.The goal is achieved by the fact that in a method involving the formation of a radiation beam in a region containing particles, the measurement zone exceeding the maximum particle size, registration of pulsed signals that occur when particles cross the measurement zone, measuring the duration of the leading edge and the peak of the signal, additionally measure the duration trailing edge of the signal, and the particle size is determined using the formula
al

, (2) where a is the particle size, defined as the length of its projection onto the direction of motion of the particles;
l the length of the measurement zone in the direction of motion of the particles;
τ _{pf the} duration of the leading edge of the signal;
τ _{in the} duration of the signal peak;
τ _{sf the} duration of the trailing edge of the signal.

 The proposed method is implemented on a setup that differs from the known one in that the analog-to-code converter, in addition to one comparison unit with a fixed discrimination level, includes an analog-to-digital converter, random access memory, an address counter made reversible, a peak detector, a second comparison unit, a third a gated comparison unit, two adders, a digital-to-analog converter, a control unit, a vertex counter, a trailing edge counter, a vertex register, a trailing edge register. The output of the first comparison unit is connected to the signal registration input of the control unit, the output of the radiation receiver is connected to the first input of the second comparison unit, the second input of which is connected to the output of the first adder and the output of which is connected to the registration input of the end of the top of the control unit. One input of the first adder is connected to the output of the radiation receiver, and the other to the second output of the reference voltage source. The output of the radiation receiver is also connected to the input of the analog-to-digital converter, its code outputs are connected to the corresponding data inputs of the random access memory, the address inputs of which are connected to the corresponding outputs of the bits of the address counter, and the data outputs to the corresponding inputs of the digital-to-analog converter. The output of the latter is connected to one of the inputs of the second adder, the other input of which is connected to the third output of the reference voltage source, and the output to the input of the third comparison unit. The other input of the third comparison unit is connected to the output of the peak detector, and the output to the registration input of the end of the leading edge of the control unit. The start input of the analog-to-digital converter and the increment input of the address counter are connected to one of the outputs of the control unit, the decrement counter input of the address and the increment input of the vertex counter are connected to the second output of the control unit, the write enable and read enable inputs of the random access memory are connected to the third and fourth the outputs of the control unit, the gating input of the third comparison unit and the incrementing input of the trailing edge counter are connected respectively to th and sixth outputs of the control unit. The outputs of the bits of the address counter are also connected to the corresponding inputs of the data of the leading edge register, the outputs of the bits of the counter of the vertex are connected to the corresponding inputs of the data of the vertex register, the outputs of the bits of the counter of the leading edge are connected to the corresponding inputs of the data of the register of the leading edge, the recording permission inputs of these registers are connected to each other and the seventh output of the control unit, and their respective data outputs are interconnected and with the corresponding data inputs of the computing unit. In addition, the read permission input of each of the mentioned registers is connected to one of the address outputs of the computing unit, and its fourth address output is connected to the reset inputs of the address, vertex and trailing edge, peak detector and control unit counters, and the request for the interrupt of the computing unit is connected to eighth output of the control unit.

 In FIG. 1 shows a functional block diagram of a device; in FIG. 2 control unit, an embodiment, in FIG. 3 computing unit based on EC1841 computer, embodiment; in FIG. 4 graphs of the change in the flux of radiation interacting with the particle as the particle passes through the measurement zone; in FIG. 5 graphs explaining the operation of the device; in FIG. 6 is an algorithm for exchanging information between a particle size calculating unit and other device nodes; in FIG. 7 and 8 graphs proving the advantages of the proposed method over the known; in FIG. 9 is an example of a histogram of particle size distribution obtained using the proposed method.

 The device includes a radiation source 1, for example, a laser, which transmits a forming system 2, for example, a lens, a scanning unit 3 for moving a substance with measured particles, and, for example, a flow cell with a hydraulic or pneumatic system for pumping suspensions (hydrosols) can be taken as a scanning unit ) or aerosols or a surface with particles deposited on it, scanned with a mechanical scanner; receiving forming system 4, a radiation receiver 5, made, for example, in the form of a photoelectronic sensor with an amplifier, a first comparison unit 6 (BSI), made, for example, in the form of a comparator, a reference voltage source 7 (hereinafter, I), having three outputs : first, second and third reference voltages, control unit 8 (BU) having four inputs and eight outputs, analog-to-digital converter (ADC) 9, which can be standard, for example, type K1108PV1, address counter 10 (CA), made on standard chips random access memory (RAM) 11, made according to the usual rules, a peak detector 12, a second comparison unit 13 (BS2), made, for example, according to a comparator circuit, a first adder 14, made according to well-known principles, a digital-to-analog converter (DAC) 15, which can be standard, for example, type K1108PA1A, the third comparison unit 16 (BS3), made, for example, according to the gated comparator circuit, the second adder 17, similar to 14; a vertex counter 18 and a trailing edge counter 19, made according to the usual principles, a leading edge register 20, a vertex register 21 and a trailing edge register 22, made in a known manner on standard microcircuits, for example, type КР580ИР82, a computing unit 23 based on a computer, for example, EU 1841, and having data inputs, an interrupt request input, and four address outputs. One possible embodiment of control unit 8 is shown in FIG. 2. BU 8 includes a master oscillator 24, made in the usual way on the chip K555LAZ, a counter 25, made on the chip K555IE7, a read-only memory (ROM) 26, made on the chip K155RE3, the first fourth input triggers, respectively, 27-30, executed on the chip D -triggers K555TM2, inverter 31, made on a chip K555LNT, logic 2xI 32 and 3xI 33, made on a chip K555LIZ, and RS-trigger 34, made on a chip K555TP2.

 BU 8 has four inputs: input 1 signal registration input; input 2 input registration vertex end; input 3 input registration front end; input 4 reset input.

 BU 8 has eight outputs: output 1, the output of the ADC start 9 and the increment of the address counter 10; output 2 output decrementing counter 10 addresses and incrementing counter 18 peaks; output 3 write enable output in RAM 11; output 4 read permission output from RAM 11; output 5 gating output of the third block 16 comparison; output 6 increment output of the counter 19 trailing edge; output 7; output of permission to write to registers; output 8 interrupt request output.

четвертого входного триггера 30 подключен к входу A4 ПЗУ 26. Инверсный выход Q третьего входного триггера 29 подключен к входу данных D второго входного триггера 28, а неинверсный выход Q третьего входного триггера 29 к одному из входов схемы 3хИ 33 и к входу данных D первого входного триггера 27. Неинверсный выход Q первого входного триггера 27 и инверсный выход

второго входного триггера 28 подключены к входам схемы 2хИ 32, выход которой подключен к входу A2 ПЗУ 26. Выходы ПЗУ 26 B1, соединенный с первым выходом БУ 8, и В3, соединенный с третьим выходом БУ 8, соединены соответственно с входами установки S и сброса R RS-триггера 34, выход Q которого соединен с вторым входом схемы 3хИ 33, а выход B3 ПЗУ 26, кроме того, соединен с третьим входом схемы 3хИ 33, выход которой соединен с входом A8 ПЗУ 26. Четвертый вход БУ 8 соединен с входами сброса R первого четвертого входных триггеров 27-30. Выходы B1 B8 ПЗУ 26 соединены соответственно с выходами 1-8 БУ 8.The output of the master oscillator 24 is connected to the input "+1" of incrementing the counter 25, the outputs Q0 and Q1 of the two least significant bits of which are connected to the inputs A0 and A1 of the ROM26. The first input of the control unit 8 is connected to the clock input C of the first input trigger 27 and through the inverter 31 with the same input of the second input trigger 28. The second and third inputs of the control unit 8 are connected respectively to the clock inputs C of the third and fourth input triggers 29 and 30, data inputs D of which connected to a high voltage source. Non-inverse output

the fourth input trigger 30 is connected to the input A4 of the ROM 26. The inverse output Q of the third input trigger 29 is connected to the data input D of the second input trigger 28, and the non-inverse output Q of the third input trigger 29 to one of the inputs of the 3xI 33 circuit and to the data input D of the first input trigger 27. Non-inverse output Q of the first input trigger 27 and inverse output

the second input trigger 28 is connected to the inputs of the 2xI 32 circuit, the output of which is connected to the input A2 of the ROM 26. The outputs of the ROM 26 B1, connected to the first output of the BU 8, and B3, connected to the third output of the BU 8, are connected respectively to the inputs of the installation S and reset R RS-trigger 34, the output Q of which is connected to the second input of the 3xI 33 circuit, and the output B3 of the ROM 26, in addition, is connected to the third input of the 3xI 33 circuit, the output of which is connected to the input A8 of the ROM 26. The fourth input of the control unit 8 is connected to the inputs reset R of the first fourth input triggers 27-30. The outputs B1 B8 ROM 26 are connected respectively to the outputs 1-8 BU 8.

 An example implementation of a computing unit 23 based on a computer, in particular of the type EC 1841, is shown in FIG. 3.

 The computing unit 23 has a group data input D connected to the computer data bus, an interrupt request interrupt request PR PR connected to the corresponding line of the main computer bus, and four address outputs B1-B4.

 Computing unit 23, in addition to the computer, includes a decoder that implements its communication with the nodes of the device through the address outputs B1-B4. The specified decoder includes two elements of the 8xI-NOT type (DD2 and DD3 chips of the U555LA2 type, the 2xILI-NOT element and two inverters (made on the DD1 chip of the K555LE1 type), as well as the dual chip decoder DD4 of the K555ID4 type.

 The address lines of the fourteen senior addresses A2-A15 of the EC 1841 computer address bus are connected to the permission input D of the first half of the DD4 chip and the input E of its second half through the logic elements DD1-DD3. To the permission inputs V1 and V2 of the first and second half of the dual decoder DD4 are connected lines for reading permission for reading and writing permissions for the main bus of the EC 1841 computer bus, and for its address inputs A and B there are lines of lower addresses A0 and A1 of its address bus. The address outputs of the microcircuit DD4 and D0, D1, D2, EO are connected respectively to the address outputs B1, B2, B3, D4 of the computing unit 23.

 The individual nodes of the device are connected as follows.

 Behind the radiation source 1, in the direction of radiation propagation, a transmitting forming system 2, a scanning unit 3, a receiving forming system 4, and a radiation receiver 5 are sequentially arranged. The output of the radiation receiver 5 is connected to the input of the first comparison unit 6, the other input of which is connected to the first output (the output of the first reference voltage) of the source 7 and the output of which is connected to the signal registration input BU 8. The output of the radiation receiver 5 is also connected to the inputs of the peak detector 12, the output of which is connected to the first input of the second comparison unit 13, the second input of which is connected to the output of the first adder 14 and the output of which is connected to the registration input of the end of the vertex BU 8. One input of the first adder 14 is connected to swing radiation receiver 5, and the other input to the second output (output of the second reference voltage) source 7.

 The output of the radiation receiver 5 is also connected to the input of the ADC 9, the code outputs of which are connected to the corresponding data inputs of the RAM 11. The address inputs of the RAM 11 are connected to the corresponding inputs of the bits of the counter 10 of the address, and the data outputs of the RAM 11 to the corresponding inputs of the DAC 15. The output of the latter is connected to the input of the second adder 17, the other input of which is connected to the third output (the output of the third reference voltage) of the source 7 and the output of which is connected to the input of the third comparison unit 16, the other input of which is connected to the output of the peak the vector 12 and the output of which is connected to the registration input of the end of the leading edge of the control unit 8. The input of the ADC of the ADC start 9 and the input "+1" of incrementing the counter 10 of the address are connected to the first output of the control unit 8, the inputs are "-1" decrementing the counter of the address 10 and "+1 "increments of the counter 18 vertices are connected to the second output of the control unit 8, the inputs of the recording permissions and read permissions for reading the RAM 11 are connected respectively to the third and fourth outputs of the control unit 8. The gate input ST of the third comparison unit 16 and the input" +1 "of the increment counter of the trailing edge 19 connected respectively only with the fifth and sixth outputs of the control unit 8. The outputs of the bits of the counter 10 of the address are also connected to the corresponding data inputs of the register 20 of the leading edge, the outputs of the bits of the counter 18 of the vertex are connected to the corresponding data inputs of the register 21 of the vertex, the outputs of the bits of the counter 19 of the falling edge are connected to the corresponding data inputs register 22 trailing edge. The inputs of the write-write permissions of the leading edge register 20, the vertex register 21, the trailing edge register 22 are connected to the seventh output of the control unit 8, and their respective data outputs are connected to each other and to the corresponding data inputs of the computing unit 23. Inputs of the reading permission of the leading edge register 20, top register 21, trailing edge register 22 are connected respectively to the first (B1), second (B2) and third (B3) address outputs of computing unit 23, its fourth address output B4 is connected to reset inputs R of address counters 10, vertices s 18, the trailing edge 19, a peak detector 12 and to a fourth input of ECU 8, and the interrupt request input CRA OL computing unit 23 is connected to the eighth output BU 8.

 The method is as follows (Fig. 1).

 Using the radiation source 1 and the transmitting forming system 2, a measurement zone is allocated in which particles interact with the radiation incident on them, and the substance being investigated contains particles moving through this measurement zone using the scanning unit 3. In this case, the size of the measurement zone in the scanning direction is chosen so that it exceeds the maximum possible particle size. Then, signals due to the interaction of radiation with particles passing through the measurement zone are recorded and their time parameters are measured. Using the receiving forming system 4, a stream is generated that interacted with the radiation particle, so that this stream falls on the radiation receiver 5.

 In FIG. 4, the formation of a signal from a particle as it passes through the measurement zone is explained, and in FIG. 4a-d show the different phases of this passage, and in FIG. 4e and e, the dependences of the radiation flux of the transmitted and scattered, respectively, when a particle passes through the measurement zone.

 The radiation beam 35 selects a measurement zone 38 in the particle 37 containing particle 36 with the first along the scanning (motion) border 39 (front border) and the second (rear) border 40, with borders 39 and 40 parallel to each other, and the distance between them along the direction scan marked l. The arrow shows the scanning direction. The projection length of the particle on the scanning direction is indicated by a.

 Let us consider the dependence of the magnitude of the radiation flux measuring zone I passed on the particle position (Fig. 4e).

In the absence of particles in the measurement zone 38 (in the further zone), the entire radiation flux passes through zone 38, forming a background flux of I _f value at the output from it (section up to t ₁ in Fig. 4e). At the beginning of the particle 36 crossing the front boundary 39 of the zone 38 (Fig. 4a) at time t _1, due to the particle 36 overlapping part of the cross-sectional area of the beam 35, the flux of the transmitted radiation zone 38 begins to decrease. The larger the part of the particle 36 entering the zone 38, the larger the cross section of the beam 35 overlaps and the smaller the radiation passes through the zone 38. Therefore, the transmitted radiation flux decreases (Fig. 4e), reaching I _m at time t ₂ , when all particle 36 completes the intersection of the frontier 39 (Fig. 4b). In this case, a leading edge of the signal is formed with a duration of τ _pf
τ _pf = t ₂ -t ₁ (3)
Starting from time t _{2, the} area of overlapping by the particle 36 of the beam 35 remains unchanged and the flux of the transmitted radiation zone 38 remains at the level of I _m until time t ₃ , when the particle 36 begins to cross the rear boundary 40 of zone 38 (Fig. 4c). In this case, a signal peak with a duration of τ _{in is formed} ,
τ _at t ₃ -t ₂ (4)
Starting from time t _{3, the} area of overlapping by the particle 36 of the beam 35 monotonously decreases and, accordingly, the flux of the transmitted radiation zone 38 increases, reaching at time t ₄ , when the whole particle 36 completes the intersection of the rear boundary 40 of zone 38 (Fig. 4 g), the background value I _f (Fig. 4e). In this case, a trailing edge of the signal with a duration of τ _{sf is formed} ,
τ _sf = t ₄ -t ₃ (5)
The dependence of the scattered (in the range of angles) flux I on the particle position is similar to the dependence for the transmitted flux, but have an “inverted” form (Fig. 4f), since the diffused flux changes its value from I _f (when there is no particle 36 in zone 38 , i.e., there is no interaction with the beam 35) up to a certain I _m (when the entire particle 36 is in zone 38 and the scattering by it is maximum), and then, when the particle 36 leaves the zone 38 (in the process of crossing the rear boundary of the 40 zone 38) the base decreases to I _f .

Thus, from the graphs of FIG. 4e, e shows that the change in the flux due to the interaction of the radiation beam 35 with the particle 36 when it passes through the measurement zone 38 from the moment t _{1 of} its entry into zone 38 to the moment t _{4 of} exit from it is a pulse signal having its leading edge ( from t ₁ to t ₂ ), apex (from t ₂ to t ₃ ) and a trailing edge (from t ₃ to t ₄ ).

 The radiation receiver 5 (FIG. 1) senses changes in the radiation flux and converts them into an electrical signal, shown in FIG. 5a.

In the absence of particles in the measurement zone, the output voltage of the radiation receiver 5 has a certain average background level U _f (region up to t ₁ in Fig. 5a) corresponding to the background flow I _f (Fig. 4 e, f) incident on the radiation receiver 5 (Fig. . 1). From time t _1, when the particle 36 starts crossing the front border 39 of the measurement zone 38 (Fig. 4a), a leading edge of the signal (Fig. 5a) begins to form at the output of the radiation receiver 5 (Fig. 1). The signal rises to time t ₂ , when the particle 36 has completely entered the measurement zone 38 (Fig. 4b), and then the signal peak is formed (Fig. 5a), during which the voltage at the output of the radiation receiver 5 (Fig. 1) remains equal U _m (see Fig. 5a). At the moment t _3, when the particle 36 starts crossing the rear border 39 of the measurement zone 38 (Fig. 4c), the formation of the trailing edge of the signal begins (Fig. 5a), which ends at the moment t _{4 of} the exit of the particle 36 from the measurement zone 38 (Fig. 4d).

Thus, at the output of the radiation receiver 5, a pulse signal from the particle (hereinafter referred to as the signal) is formed, carrying information about the particle size, contained in the durations of the leading edge, vertex and trailing edge. The signal processing in order to extract the specified information can be divided into four stages:
discretization of the signal in the area from the beginning of its leading edge to the end of the peak;
measurement of the durations of the trailing edge, peak and rising edge of the signal;
the exchange of information between the computing unit 23 and the remaining nodes of the device and calculating the result.

 Prior to the start of signal processing, the device is restored to its initial state of readiness by a “Reset” pulse from the fourth address output B4 of computing unit 23 (see the description of the third stage of signal processing) to the reset inputs of counters of address 10, peak 18, and trailing edge 19, peak detector 12 and control unit 8. At the indicated reset pulse, the mentioned counters 10, 18, and 19 are reset, the output voltage of peak detector 12 is reset, and the first fourth input triggers 27-30 (Fig. 2) of control unit 8 are set to state 0 at the inverted outputs Q.

 The first of these steps is carried out as follows.

The moment t ₁ (Fig. 5a) of the beginning of the signal is defined as the moment of reliable recording of the increase in the output voltage of the radiation receiver relative to the background level U _f due to the appearance of the signal. For this, the signal from the output of the radiation receiver 5 is fed to the first input of the first comparison unit 6, the first input of which receives the first reference voltage U ₀₁ from the source 7. The first comparison unit 6 performs two functions:
registers the appearance of the signal by the first voltage drop at its output at time t _{1 of the} equality of the output voltage of the radiation receiver 5 and U ₀₁ (Fig. 5e);
detects the disappearance of the signal at the time t _{4 of} repeated equality of the output voltage of the radiation receiver 5 and U _{01 by the} second (reverse) voltage drop at its output (see the description of step 2 below).

In order to reliably record these events, including false alarms of the comparison unit 6 due to the effect of noise on its inputs, it is assigned a response threshold slightly higher than the background level using the first reference voltage U ₀₁ .

Thus, between the beginning t ₁ and the end t _{4 of the} signal from the output of the first comparison unit 6, a pulse is received at the first input (signal registration input) of the control unit 8, indicating the presence of a signal. Starting from time t ₁ , the control unit 8 generates at its output 1 pulses for starting the ADC 9 and incrementing the counter 10 addresses (pulses of the INK CA), and at its output 3 pulses for writing to RAM 11 (pulses of the RAM RAM), thereby sampling the signal using ADC 9 with subsequent recording of samples in RAM 11. At the same time, in the counter 10 of the address that sets the address of RAM 11 for placing the next sample, the number of samples is actually calculated. This process lasts for the leading edge and peak of the signal and ends at time t ₃ (Fig. 5a, and) the end of the peak (and the 1st stage of signal processing).

третьего входного триггера 29 (этот триггер до момента t₃ окончания вершины находится в исходном состоянии). В результате в момент t₁ на выходе Q первого входного триггера 27 устанавливается напряжение высокого уровня, поступающее на вход схемы 2хИ 32, на другой вход которой поступает напряжение с инверсного выхода

второго триггера 28. Это напряжение также имеет высокий логический уровень, так как второй входной триггер 28 еще находится в исходном состоянии (на его информационный вход D до момента t₂ поступает напряжение низкого логического уровня с неинверсного выхода Q третьего входного триггера 29). Таким образом, на выходе схемы 2хИ 32 в момент t₁устанавливается напряжение высокого уровня, поступающее на вход A2 ПЗУ 26. После этого в соответствии с картой прошивки ПЗУ 26 в течение каждого следующего после момента t₁ периода T_о, начинающегося от переднего фронта импульса r_о (фиг. 5г), формируются импульсы ИНК СА на выходе 1 и ЗП ОЗУ на выходе 3 БУ 8. Импульсы ИНК СА, поступающие на вход ЗАП запуска АЦП 9 и на вход "+1" инкрементирования счетчика 10 адреса, формируются по фронту каждого импульса r_о (совпадающему с фронтом первого в данном периоде T_о импульса r_и) и имеют длительность T_и=T_o/2 (фиг. 5е). При этом на кодовых выходах АЦП 9 формируется код величины сигнала на выходе приемника 5 излучения в текущий момент и этот код поступает на соответствующие входы данных ОЗУ 11, а на выходах разрядов счетчика 10 адреса устанавливается код адреса очередной ячейки ОЗУ 11, поступающий на соответствующие адресные входы ОЗУ 11. Затем по фронту второго в этом же периода T_o импульса r_и БУ 8 на своем третьем выходе (разрешения записи в ОЗУ) формирует импульсы ЗП ОЗУ разрешения записи в ОЗУ 11 (фиг. 5ж) длительностью T_и/2= T_o/4. В ре- зультате происходит запись кода текущей величины сигнала в очередную ячейку ОЗУ 11. Если первый перепад напряжения на выходе блока 6 сравнения произошел в момент t₁ (фиг. 5а), то первое приращение счетчика 10 адреса и выборка с помощью АЦП 9 произойдут в момент t₁ ^o (фиг. 5 д, е), очень близкий к t₁ и отличающийся от него не более чем на T_o. Так как частоту задающего генератора 24 в БУ 8 выбирают достаточно высокой, т. е. T_o достаточно малой, в ходе дальнейших объяснений будем полагать, что моменты t₁ и t₁ ^о совпадают.When implementing control unit 8 in accordance with FIG. 2, the formation of pulses at its outputs during the 1st stage of signal processing is as follows. The pulses of the master oscillator 24 (Fig. 5b) are fed to the counting input of the counter 25, which forms on its output a sequence of clock pulses in the form of a meander r _and with a period T _and (Fig. 5c), arriving at the address input A0 of the ROM 26, and on the other its output is a sequence of pulses (meander) r _о with a period T _о = 2Т _and (Fig. 5 g) supplied to the address input A1 of the ROM 26. The voltage drop arriving at the first input of the control unit 8 at time t ₁ (Fig. 5e), gets to the counting input C of the first input trigger 27, made according to the scheme of the D-trigger and performing anti-bounce stems function. At its information input D at this time, a high-level logic signal is supplied from the inverse output

third input trigger 29 (this trigger is in the initial state until t _{3 of the} end of the vertex). As a result, at time t _1, at the output Q of the first input trigger 27, a high level voltage is supplied to the input of the 2xI 32 circuit, the other input of which receives voltage from the inverse output

the second trigger 28. This voltage also has a high logic level, since the second input trigger 28 is still in the initial state (low voltage of the logic level from the non-inverse output Q of the third input trigger 29 is supplied to its information input D until t ₂ ). Thus, the output circuit 32 2hI at time t ₁ is set the high level voltage supplied to the A2 input of ROM 26. Thereafter, in accordance with the card, ROM EEPROM 26 during each of the next after the time t _{1 of the} period T, starting from the leading edge of the pulse r _o (Fig. 5d), pulses of the INK CA are generated at the output 1 and the RAM RAM at the output 3 of the control unit 8. The pulses of the INK CA arriving at the input of the start-up drive of the ADC 9 and at the input "+1" of incrementing the address counter 10 are formed along the edge each impulse r _о (coinciding with the front of the first in this period T _о them pulse r _and ) and have a duration of T _and = T _o / 2 (Fig. 5E). At the same time, the code outputs of the ADC 9 generate a code of the signal value at the output of the radiation receiver 5 at the current moment and this code is supplied to the corresponding inputs of the RAM data 11, and at the outputs of the bits of the address counter 10, the address code of the next RAM 11 cell arrives at the corresponding address inputs RAM 11. Then, along the front of the second pulse T _o in the same period T _{o and} BU 8 at its third output (write permissions in RAM) it generates pulses of RAM RAM write permissions in RAM 11 (Fig. 5g) of duration T _and / 2 = T _o /4. As a result, the current signal value code is written to the next RAM cell 11. If the first voltage drop at the output of the comparison unit 6 occurred at time t ₁ (Fig. 5a), then the first increment of the address counter 10 and sampling using the ADC 9 will occur in moment t ₁ ^o (Fig. 5 d, e), very close to t ₁ and differing from it by no more than T _o . Since the frequency of the master oscillator 24 in the control unit 8 is selected sufficiently high, i.e., T _{o is} sufficiently small, in the course of further explanations we will assume that the moments t ₁ and t ₁ ^o coincide.

Thus, the code of the magnitude of the signal at the output of the radiation receiver 5 corresponding to time t ₁ will be recorded in the first cell of RAM 11, the code of the signal at time t ₁ + T _o in the second cell, etc. In general, the magnitude of the signal available on the output of the radiation receiver 5, through the interval iT _o (i = 0, 1, 2.), i.e. at the moment t ₁ + iT _o , will be fixed in the RAM cell 11 with the number N _i = i + 1 (Fig. 5 e. g). In other words, in the cell with the number N _{i the} countdown made at the moment
t _i = t ₁ + (N _i -1) T _o (6)
This process of signal sampling continues until the end of its peak (the beginning of the trailing edge). The specified moment t ₃ (Fig. 5a, and) is recorded as the moment of reliable detection of a decrease in the current signal level compared to its level U _m at the top. At this moment, at the output of the second comparison unit 13, a voltage drop is formed as follows.

The peak detector 12 captures the maximum value of the signal at the output of the radiation receiver 5, and during the peak of the signal (and further) its output voltage is U _m (Fig. 5h). This voltage is supplied to the first input of the second comparison unit 13, and its second input is supplied from the output of the first adder 14, the sum of the current value of the output signal of the radiation receiver 5 and the value of the second reference voltage U ₀₂ from the second output of the source 7. This reference voltage provides the initial excess voltage at the second input of the comparison unit 13 above the voltage value at its first input (above the output voltage level of the peak detector 12) during the leading edge and the peak of the signal until t ₃ , when the voltage The phenomena at the inputs of the comparison unit 13 become equal due to a decrease in the signal. In this case, at the output of the comparison unit 13, a voltage drop is generated (Fig. 5i). The specified initial excess of the voltage level at the second input of the comparison unit 13 over the level at its first input is necessary to prevent its false positives, possible until the end of the peak due to the impact of noise on its inputs.

 The voltage drop from the output of the second comparison unit 13 is fed to the second input (input of the registration of the end of the vertex) of the control unit 8. In the FIG. 2 example implementation BU 8 this differential is supplied to the counting input C of the third input trigger 29.

Up to this point, the indicated trigger is in its initial state (there is a low level voltage at its output Q, and a high logic level voltage is present at its information input D). According to the specified difference, the third input trigger 29 is overturned and “latched” in this state, performing anti-bounce functions. Then, a signal of a high logic level from its output Q, passing through a 3xI 33 logic circuit (necessary for the correct connection of subsequent pulses DEC SA, CT RAM, BSB strobe generated by BU 8 at its outputs 2, 4, 5, see the description of the 2nd stage signal processing), goes to input A4 of ROM 26 and sets the new operating mode of BU 8 in accordance with the firmware map of ROM 26. As a result, ROM 26 stops generating pulses of the INK SA and the RAM of the RAM and begins to generate others necessary at the 2nd stage of signal processing (see below). In addition, after the establishment at the time t ₃ at the output Q of the third input trigger 29 BU 8 of a high level voltage supplied to the information input D of the second trigger 28, the latter gets the opportunity to change its state when a positive voltage drop arrives at its counting input C. This difference (see the description of the 2nd stage of signal processing) will signal the end of the signal at time t ₄ (Fig. 5 a, d).

After triggering at the time t _{3 of the} second block 13 of the comparison, the formation of pulses of the INK CA at the output 1 and pulses of the RAM of the RAM at the output 3 of the BU 8 stops.

At the time t _{3 of the} operation of the comparison unit 13, the address counter 10 contains the code N _{3 the} number of steps (without unit) of the signal sampling performed over the total time of the leading edge τ _pf and the peak τ _{in the} signal, and the equality
τ _pf + τ _in = (N ₃ -1) T _o . (7)
From this moment begins the 2nd stage of signal processing, the step of measuring the durations of the trailing edge, peak and leading edge of the signal,
The measurement of the duration of the trailing edge of the signal is implemented using BU 8 and the counter 19 of the trailing edge as follows. During each subsequent period after the time t _{3 of the} period T _o (Fig. 5d), the control unit 8 at its output 6 generates a pulse for incrementing the counter of the trailing edge 19 (pulse of the INK NWF, Fig. 5 k). In the counter 19 of the trailing edge there is an accumulation of pulses up to the moment t _{4 of the} end of the trailing edge and the entire signal (Fig. 5A). The specified moment is determined by the second response of the comparison unit 6 (Fig. 5e) when the signals are reached in the process of decreasing the level specified by the value of the first reference voltage U ₀₁ supplied to the second reference input of the comparison unit 6 from the source 7. At the same time, the output of the comparison unit 6 in the moment t _{4 is} generated by the reverse voltage drop supplied to the first input of the control unit 8.

. С него напряжение низкого логического уровня попадает на вход схемы 2хИ 32 и тем самым на вход A2 ПЗУ 26, изменяя режим его работы в соответствии с картой прошивки.In the embodiment of FIG. 2 example implementation of BU 8, the specified difference after passing through the inverter 31 is fed to the counting input C of the second input trigger 28 (anti-bounce), which is still in its original state ("0" on the non-inverse output Q). At the same time (see above), from the moment t _{3 of the} end of the peak, there is a high level voltage at its information input D coming from the output of the third input trigger 29. As a result, at time t _4, an inverse difference occurs at the output of the first comparison unit 6 of the second input trigger 28 Control unit 8 capsizes and switches to state "0" at the inverse output

. From it, the voltage of a low logical level goes to the input of the 2xI 32 circuit and thereby to the input A2 of the ROM 26, changing the mode of its operation in accordance with the firmware card.

Thus, at time t _{4, the} BU 8 stops the formation of pulses of the NWF NSC at its sixth output. The code N _zf accumulated up to this moment in the counter 19 of the trailing _edge corresponds to the duration of the trailing edge of the signal τ _zf
τ _sf = N _sf ˙ T _o (8)
The peak and leading edge durations are measured at the 2nd stage of signal processing by analyzing the discrete samples recorded in RAM 11 when they are enumerated in the reverse order of recording.

With the specified enumeration, a search is made for the reference that corresponds to the moment t _{2 of the} end of the leading edge (beginning of the peak) of the signal. The search is performed according to a criterion similar to the criterion for recording the moment t _{3 of the} end of the vertex. In other words, the cell number of the RAM 11 is searched for, which contains a sample taken at the time t _{2 of the} end of the leading edge of the signal at the last time, when the signal level was still quite distinct from its level at the top. This check is carried out using BU 8, address counter 10, vertex counter 18, RAM 11, DAC 15, peak detector 12, and third comparison unit 16 with the second adder 17 as follows.

After registering the moment t _{3 of the} end of the top of the BU 8, as mentioned above, it stops the formation of pulses of the INK CA and ZP RAM and begins to generate three sequences of pulses:
impulses of decrementation of the counter 18 peaks (pulses DC SA) at its output 2 (Fig. 5L);
read pulses of RAM 11 (pulses of read RAM) at its output 4 (Fig. 5m);
the gating pulses of the third block 16 comparison (strobe BSZ) at its output 5 (Fig. 5N).

Control unit 8 constructed in accordance with FIG. 2, implements each of these sequences with a period of T _o . Using these three sequences of pulses, the samples of the signal values recorded in RAM 11 are sampled at sampling times t ₁ + iT _o (i = N ₃ -2, N ₃ -3.0) in the corresponding cells with numbers N ₃ -1, N ₃ -2.1 in the reverse order of their recording, that is, it enumerates the samples taken at times from t ₃ -T _o to t ₁ with a step of T _o . In this case, according to the pulses of DEC SA and CT RAM, the next count comes from RAM 11 to the DAC 15 and then, converted into analog form, to the input of the second adder 17, and the third reference voltage U ₀₃ from the third output of source 7 is supplied to its second input. Similarly the time t ₃ was recorded, the first signal of the third comparison unit 16 receives the output signal of the peak detector 12 equal to the maximum value of the signal (at its top), and the second signal from the second adder 17 receives the sum of the signal the mind shenie its value (in this case, the DAC output signal 15) with a fixed voltage U _03. The specified summation is introduced to prevent false alarms of the third comparison unit 16, which may be caused by the influence of noise on its inputs. Comparison of the voltages at the inputs of the third comparison unit 16 is made when the pulse of the ST gate is received at its input; the BSZ strobe is from the fifth output of the BU 8. At the time when this comparison shows that the readout from the next cell of RAM 11 with number N ₂ is converted by the DAC 15 into the analog form, it turned out to be significantly smaller than the value of the signal at its peak, the comparison unit 16 generates a pulse (Fig. 5 s), which is received at the input of the beginning of the peak registration (input 3) of the control unit 8. In the FIG. 2, the implementation of the last on the leading edge of the indicated pulse triggers the fourth trigger 30 (anti-bounce), which was still in its original state (see above), and the high logic level voltage from its output Q goes to the input A3 of the ROM 26 of BU 8 (Fig. 5p). After this, the BU 8 stops generating pulses DEC SA, THB RAM, strobe BSZ, that is, the process of reverse search of discrete samples stops. In this case, the address code N _{2 of the} found RAM cell 11 is stored at the output of the address counter 10.

The record is recorded in the revealed cell N ₂ at the moment t _{2 of the} end of the leading edge defined by the expression (see formula (6)
t ₂ = t ₁ + (N ₂ -1) T _about . (nine)
If N _in denote the number of decrementing steps performed by decrementing the address counter 10, then
N ₂ = N ₃ -N _in (10)
t ₂ = t ₁ + (N ₃ -N _in -1) T _o (11)
Since the pulses DEC SA decrementing the counter 10 addresses are also fed to the input of incrementing the counter 18 of the vertex, then after completing the exhaustive search, the latter contains information about the duration τ _{to the} vertices of the signal (code N _в ) and the equality
τ _in = N _in ˙T _o (12) and the remaining contents of the address counter 10 equal to N ₂ determines the duration of the leading edge τ _pf signal
τ _pf = (N ₂ -1) ˙T _o (13)
For the correct and stable implementation of the reverse search process discussed above at the beginning of the formation of pulse sequences DEC SA, CT RAM and Strobe BSZ, that is, after registering the moment of completion of the peak t ₃ , BU 8 provides;
the absence of failures due to bounce at the output of the second comparison unit 13 at the time of registration of the end of the peak;
a reliable record in RAM 11 of the last count made by the ADC 9;
the first gating of the third block 16 comparison only after the first decrementation of the counter 10 addresses.

 In the embodiment of FIG. 2 embodiment BU 8 these requirements are met as follows.

The voltage drop that occurs at the output of the second comparison unit 13 at time t ₃ (Fig. 5i) and enters the input 4 of the control unit 8, enters the input of its third input trigger 29. The latter, performing an anti-bounce function, “snaps” the signal Q at its output high level, fed to the first input of the 3xI 33 logic circuit, which, together with the RS flip-flop 34, ensures the correct start of the formation of these three sequences of pulses DEC SA, CT RAM and strobe BSZ as follows. Each pulse of the INK CA (Fig. 5f) generated at the output B1 of the ROM 26 of the BU 8 during sampling, the RS flip-flop 34 is set to the state “0”, and the subsequent pulse of the RAM from the output B3 of the ROM 26 (Fig. 5g) to state "1". The output signal of the RS flip-flop 34 and the signal of the RAM RAM are supplied to the second and third inputs of the 3xI 33 circuit, at the output of which, connected to the input A3 of the ROM 26, the difference from the state “0” to “1” appears regardless of the moment the second comparison unit 13 is triggered , only after the end of the next pulse of the RAM RAM. This ensures reliable fixation in RAM 11 of the last sample taken at the top of the signal. The ROM chip 26 is programmed in such a way that after the appearance of a high level voltage at its input A3, firstly, the pulses of the INK CA and the RAM RAM are stopped, therefore both the third input trigger 29 and the RS trigger 34 remain in the state “1” at the outputs and at the input A3 of the ROM 26 remains a high level signal. Secondly, the formation of pulses begins DEC SA, THAT RAM and strobe BSZ as follows:
DEC SA pulses of duration T _and / 2 = T _o / 4 at the output 2 of the control unit 8 are generated at the leading edge of the pulses r _o (Fig. 5 l);
pulses of read-only memory at the output 4 of the control unit 8 of duration T _and = T _o / 2 are generated from the middle of the pulses r _o (Fig. 5m);
pulses BSZ strobe at the output 5 of BU 8 with duration T _and / 2 = T _o / 4 are generated at the trailing edge of pulses r _o (Fig. 5n).

Thus, in each period T _o starting from the leading edge of the pulse r _o , these pulses are generated in the order required for joint operation of the RAM 11, the DAC 15, and the comparison unit 16. In this case, before the decrementation of counter 10 of the address, the reliable recording of the last count in RAM 11 is provided, and the mutual position of the pulses of the RAM, RAM, DEC RAM, and BSB strobe eliminates the possibility of the first gating of the third comparison block 16 before the decrement of the counter 10 of the address, and this eliminates the possibility of false triggering of the comparison unit 16, i.e., the false determination of the moment t ₂ during the time interval T _o after recording the moment t _3.
So, at the 2nd stage of signal processing, the durations are measured
trailing edge of the signal τ _sf (code N _sf at the outputs of the bits of the counter 19 of the _falling edge);
the vertices of the signal τ _in (code N _in at the outputs of the bits of the counter 18 vertices);
the leading edge of the signal τ _pf (code N ₂ at the outputs of the bits of the counter 10 addresses).

 The end of the 2nd stage is determined by BU 8 upon the occurrence of the last of two events: the end of the trailing edge of the signal (the second voltage drop at the output of the first comparison unit 6) or the end of the reverse search of discrete samples (pulses at the output of the third comparison unit 16). In this case, the control unit 8 starts to generate at its output 7 pulses of the RG WG of writing permission to the registers (Fig. 5p) received at the inputs of the ZP of recording permission of the register 20 of the leading edge, register 21 of the peak, register 22 of the falling edge. At the same time, the control unit 8, at its output 8, generates an interrupt request pulse for the PRAM PR (Fig. 5c), which is received at the input of the interrupt request for computing unit 23. Since the data inputs of the above registers are connected to the corresponding outputs of the address counter 10, vertex counter 18, and counter 19 of the trailing edge, at the very first pulse of the RG WG, the contents of these counters are recorded in the corresponding registers.

 At the 3rd stage of signal processing, the processing unit 23 carries out the processing of the RRP signal in accordance with the sequence diagram of the computer, which is part of the computing unit 23, and is embedded in the program. An example of an interrupt processing program algorithm is shown in FIG. 6. Having received the signal ZPR PR, the computing unit 23 from its first address output B1 sends read pulses TH to the input TH of the read permission register 20 of the leading edge and reads information from it about the duration of the leading edge of the signal. Similarly, by generating pulse read pulses of CTs at the outputs B2 and B3 of the computing unit 23, the computer reads information about the duration of the vertex and the trailing edge of the signal, respectively, from the vertex register 21 and the trailing edge register 22. The received information is entered into your own computer RAM. Then, at the address output B4, the computing unit 23 generates a reset pulse, which is fed to the reset inputs R of the peak detector 12, address counters 10, peaks 18, and trailing edge 19, as well as control unit 8. As a result, these counters are reset to zero, and the peak detector output signal is reset. 12 (Fig. 5h) and, therefore, the return to the initial state of the second block 13 comparison (Fig. 5P). In addition, there is a transition to the initial state of the control unit 8 (reset of all four input triggers 27-30, Fig. 2). BU 8 stops generating pulses of the ZP RG and ZPR PR, and the device as a whole is ready to receive a signal from another particle.

.In the example of constructive execution of the computing unit 23 shown in FIG. 3, a standard EC 1841 type computer was used, equipped with a decoder on DD1-DD4 microcircuits. The address lines A2-A15 of the computer address bus and the logic elements DD1-DD4 are connected in such a way that a signal is realized at the information input D of the first half of the decoder DD4 (chip K555 ID4)
A2∧A3∧.A14∧A15, and a signal is realized at the information input E of the second half of the decoder DD4

.

 When a read enable pulse appears on the reading line of the main bus of the EC 1841 mainframe, it goes to the enable input V1 of the first half of the decoder DD4 and, depending on the combination of signals on the address lines of the computer A0 and A1 connected to the inputs A and B of the decoder DD4, the latter gives a pulse at one of its outputs D0, D1 or D2, connected respectively to the outputs B1, B2 and B3 of the computing unit 23. Moreover, in accordance with FIG. 3, the signal at output B1 corresponds to code 77774, at output B2 77775, at output B3, code 77776 on the computer address bus. When a pulse appears on the recording line of the main bus of the computer, this pulse is fed to the V2 resolution input of the second half of the DD4 decoder and, at the same time, with a combination of 77777 on the computer address bus, i.e., combination 11 on its lines A0 and A1, at the output of the DD4 decoder EO , that is, at the address output B4 of the computing unit 23, a “Reset” signal appears.

 After issuing "Reset" and putting the entire device in a state of readiness to process the signal from the next computer particle of the computing unit 23, it calculates the particle size, information about the duration of the leading and trailing edges and signal peaks of which are located in the computer RAM, according to the program that implements the formula (2 )

 The method is implemented in the laboratory SZPI at the department "Devices and methods of quality control and laser technology" on the installation made in accordance with Fig. 1.

 The method is implemented as follows.

0,5·10^-4м 50 мкм.An ILNP-108 semiconductor laser was used as a radiation source. As the transmitting and receiving forming systems, the BIOLAM R14 microscope collector and its optical system, including the 40X lens, AU-26 binocular nozzle, modified for simultaneous visual observation with photometric measurements using the nozzle with a photomultiplier tube, were used respectively. Before the PMT, a diaphragm 3.0 mm wide was introduced. Since the total increase in the receiving optical system is 60, the width of the measurement zone
l

0.5 · 10 ^-4 m 50 μm.

A mechanized microscope stage with a drive from an electric motor DPR-32-HI-07 was used as a scanning unit. An object (medical) glass with a smear of a suspension containing particles applied to it is installed on a stage. The radiation receiver is based on a FEU-144 and a preamplifier on two operational amplifiers (op amps) of the KR544UD2A type with a compensation circuit for the constant component (background) on a chip of the K544UD2A type. The signal from the output of the pre-amplifier is fed to the electronic node in accordance with the description of the device. The first, second, and third comparison blocks are made on K554CAZ type microcircuits, and the gating outputs in the first two cases are supplied with a constant level of OM allowing their operation. The reference voltage source is made in the form of a highly stable resistive voltage divider connected to a stabilized voltage source with a ripple value of 0.1 mV. Since the noise voltage at the output of the pre-amplifier (radiation receiver) was about 20 mV, and the noise of the other nodes is much less, all three reference voltages were chosen the same for 20 mV. The control unit is made in accordance with FIG. 2 using the indicated microcircuits. The frequency of the master oscillator of the control unit was chosen equal to 2 MHz. Accordingly, the pulse repetition period of the INK SA, ZP RAM, DEC SA, THB RAM, INK NWF, BSB strobe is 2 × 10 ^-6 s. As an ADC, an integral ADC of sequential approximation of the K1108PV1 type was used. The address counter is made in a known manner on three chips of the type K555IE7. Similarly, a vertex counter and a trailing edge counter are made, only with unused decrementing outputs. RAM volume of 1Kx12 is made on three chips of the type K541RU2. The peak detector is assembled on two op-amps of type K544UD2A according to a typical circuit. Adders are implemented on the K544UD2A type op-amp according to the usual principles. The DAC is implemented on a chip of type K1108PA1A, and its inputs of the two high-order bits are not used (since the 10-bit ADC is used, the 12-bit DAC is used as a 10-bit). The leading edge, vertex, and trailing edge registers are each made on two chips of the KR580IR82 type, with OE inputs used as write enable inputs, and STB microcircuits as read enable inputs.

 An EC 1841 microcomputer with an address decoder made in accordance with FIG. 3.

 This device was used to study the size composition of various powders. In particular, a spore powder of a lycopodium (Licopodium) plunger having medical use was investigated. Based on the results of determining the size of 350 particles, a histogram was plotted as shown in FIG. nine.

Claims (2)

1. The method of determining particle sizes, which consists in directing the radiation beam to the region containing the particles, forming a measurement zone in the region using the radiation beam that is larger than the maximum particle size, converting the radiation into an electrical signal and registering pulsed signals arising from the intersection of the measurement zone by the particles, the duration of the leading edge and the peak of the pulse signal from each particle is measured, characterized in that, in order to increase the accuracy, the back duration is measured about the front of the signal from each particle, and the particle size is determined by the formula

where a is the projection of the particle size on the scanning direction;
l the length of the measurement zone in the scanning direction;
τ _{pf the} duration of the leading edge of the signal;
τ _{sf the} duration of the trailing edge of the signal;
τ _{in the} duration of the signal peak.  2. A device for determining particle sizes, containing a radiation source, a transmitting forming system, a scanning unit, a receiving forming system, a radiation receiver, an analog-code converter in the form of a comparison unit with a given level of discrimination and a reference voltage source, and a computing unit, and one input of the unit comparison is connected to the output of the radiation receiver, and the other to one of the outputs of the reference voltage source, characterized in that, in order to improve accuracy, the analog-to-code converter is made in the form tax-to-digital converter, random access memory, reverse counter, peak detector, second comparison unit, third gated comparison unit, first and second adders, digital-to-analog converter, control unit, trailing edge counter, vertex register, trailing edge register , the output of the first comparison unit is connected to the signal registration input of the control unit, the output of the radiation receiver is connected to the input of the peak detector, the output of which is connected to the the input of the second comparison unit, the second input of which is connected to the output of the first adder and whose output is connected to the registration input of the end of the top of the control unit, one input of the first adder is connected to the output of the radiation receiver, and the other to the second output of the reference voltage source, the output of the radiation receiver is also connected with the input of an analog-to-digital converter, the code outputs of which are connected to the corresponding data inputs of the random access memory, the address inputs of which are connected to the corresponding by the outputs of the bits of the address counter, and the data outputs with the corresponding inputs of the digital-to-analog converter, the output of the latter is connected to one of the inputs of the second adder, the other input of which is connected to the third output of the reference voltage source, and the output to the input of the third comparison unit, the other input of which is connected to the output peak detector, and the output with the input of the registration of the end of the leading edge of the control unit, the trigger input of the analog-to-digital converter and the increment input of the address counter are connected to one m from the outputs of the control unit, the input of decrementing the address counter and the input of incrementing the counter of the vertex are connected to the second output of the control unit, the inputs of writing permission and read permission of the random access memory are connected respectively to the third and fourth outputs of the control unit, the gating input of the third comparison unit and the input of incrementing the counter the trailing edge are connected respectively to the fifth and sixth outputs of the control unit, the outputs of the bits of the address counter are also connected to the corresponding and inputs of the leading edge register, the outputs of the bits of the counter of the vertices are connected to the corresponding inputs of the data of the registers of the vertex, the outputs of the bits of the counter of the leading edge are connected to the corresponding inputs of the data of the register of the leading edge, the recording permission inputs of these registers are connected to each other and to the seventh output of the control unit, and the corresponding data outputs are interconnected and with the corresponding data inputs of the computing unit, the read permission input of each of the registers is connected to one of the addresses of the outputs of the computing unit, its fourth address output is connected to the reset inputs of the counters, address, vertex and trailing edge, the peak detector and the control unit, and the interrupt request input of the computing unit is connected to the eighth output of the control unit.

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