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KR940000989B1 - Method of manufacturing polycrystalline silicon ultra thin field effect transistor - Google Patents

Method of manufacturing polycrystalline silicon ultra thin field effect transistor Download PDF

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KR940000989B1
KR940000989B1 KR1019900021815A KR900021815A KR940000989B1 KR 940000989 B1 KR940000989 B1 KR 940000989B1 KR 1019900021815 A KR1019900021815 A KR 1019900021815A KR 900021815 A KR900021815 A KR 900021815A KR 940000989 B1 KR940000989 B1 KR 940000989B1
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silicon
field effect
temperature
effect transistor
thickness
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KR920013752A (en
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남기수
이경수
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한국전기통신공사
이해욱
재단법인 한국전자통신연구소
경상현
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

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  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

내용 없음.No content.

Description

다결정 실리콘 초박막 전계효과 트랜지스터의 제조방법Method of manufacturing polycrystalline silicon ultra thin field effect transistor

제1도는 본 발명의 비정질 실리콘의 활성층 제조과정을 나타낸 단면도.1 is a cross-sectional view showing the manufacturing process of the active layer of amorphous silicon of the present invention.

제2도는 본 발명의 다결정 실리콘 초박막 전계효과 트랜지스터의 게이트 절연막 제조과정을 나타낸 단면도.2 is a cross-sectional view illustrating a process of manufacturing a gate insulating film of a polycrystalline silicon ultra-thin field effect transistor of the present invention.

제3도는 본 발명의 단면도 게이트 전극을 형성하는 과정을 나타낸 단면도.3 is a cross-sectional view showing a process of forming a cross-sectional gate electrode of the present invention.

제4도는 본 발명의 다결정 실리콘 초박막 전계효과 트랜지스터의 제조과정을 나타낸 단면도.4 is a cross-sectional view showing the manufacturing process of the polycrystalline silicon ultra-thin field effect transistor of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 실리콘 웨이퍼 2 : 실리콘 산화막1: silicon wafer 2: silicon oxide film

3 : 다결정 혹은 비정질 실리콘 활성층3: polycrystalline or amorphous silicon active layer

4 : 다결정 실리콘 위에 형성된 실리콘 산화막층4: silicon oxide layer formed on polycrystalline silicon

5 : 탄탈륨 산화막층(tantalum-oxide)5: tantalum oxide layer

6 : 게이트 전극으로서의 다결정 실리콘층6: polycrystalline silicon layer as gate electrode

7 : As-(혹은 BF2)이온주입7: As - (or BF2) ion implantation

8 : n+(혹은 p+)소오스 및 드레인 영역 9 : 금속(AI/1% Si)전극8: n + (or p + ) source and drain region 9: metal (AI / 1% Si) electrode

10 : 저온실리콘 산화막10: low temperature silicon oxide film

본 발명은 실리콘 산화막과 탄탈륨 산화막을 적층제조방법에 있어 특히 이중막을 게이트 절연막으로 사용한 다결정 실리콘 초박막형 전계효과 트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a polycrystalline silicon ultra-thin field effect transistor using a double film as a gate insulating film, in particular, in a method for laminating a silicon oxide film and a tantalum oxide film.

종래의 다결정 실리콘 박막형 전계효과 트랜지스터는 액정 디스플레이(display), 평판 텔레비젼 판넬 및 static random access memory(SRAM)의 기본소자로 응용된다.Conventional polycrystalline silicon thin film field effect transistors have been applied as basic elements of liquid crystal displays, flat panel television panels, and static random access memory (SRAM).

또한 다결정 실리콘 박막형 전계효과 트랜지스터의 동작 원리는 metal-oxide-semiconductor(MOS) 전계효과 트랜지스터 원리와 같고 다결정 실리콘 박막형 전계효과 트랜지스터에 대한 주요연구는 다결정 실리콘막의 성장방법, 다결정 실리콘막의 수십 nm이하로의 초박막화, 고신뢰성 게이트 절연막 형성과 수소처리방법등이 있다. 다결정 실리콘 박막형 전계효과 트랜지스터의 게이트 절연막으로 실리콘 산화막 또는 실리콘 질화막을 사용하지만, 다결정 실리콘 박막형 전계효과 트랜지스터의 구동전류가 감소되는 문제점을 가지게 된다.In addition, the operation principle of the polycrystalline silicon thin film field effect transistor is the same as that of the metal-oxide-semiconductor (MOS) field effect transistor, and the main researches on the polycrystalline silicon thin film field effect transistor are the growth method of the polycrystalline silicon film and the tens of nm or less of the polycrystalline silicon film. Ultra thin film formation, high reliability gate insulating film formation and hydrogen treatment method. Although a silicon oxide film or a silicon nitride film is used as the gate insulating film of the polycrystalline silicon thin film field effect transistor, the driving current of the polycrystalline silicon thin film type field effect transistor is reduced.

이에따라 본 발명은 전계효과 트랜지스터 구동전류를 증가시키고, 서브 드레시 홀드(sub-threshold)스토퍼 다결정 실리콘 박막형 전계효과 트랜지스터를 제조하도록 함을 그 목적으로 한다. 이를 위하여 본 발명은 다결정 실리콘 박막형 전계효과 트랜지스터의 제조방법은 다음과 같다.Accordingly, an object of the present invention is to increase a field effect transistor driving current and to manufacture a sub-threshold stopper polycrystalline silicon thin film type field effect transistor. To this end, the present invention is a method of manufacturing a polycrystalline silicon thin film type field effect transistor is as follows.

제1도는 비정질 실리콘의 활성층 제조방법에 관한 것으로, 실리콘 웨이퍼(1)위에 저압화학 증착법과 열전기로를 이용하여 500nm 정도 두께의 실리콘 산화막(2)을 형성하고 실리콘 산화막(2)위에 저압화학증착법을 이용하여 550-625℃정도 온도에서 10∼200nm정도의 두께로 다결정 또는 비정질 실리콘 박막을 형성한 후 사진 식각 작업을 통하여 다결정 또는 비정질 실리콘의 활성층 영역(3)을 형성한 과정을 나타낸 것이다.FIG. 1 relates to a method of manufacturing an active layer of amorphous silicon. A silicon oxide film 2 having a thickness of about 500 nm is formed on a silicon wafer 1 using a low pressure chemical vapor deposition method and a thermoelectric furnace, and a low pressure chemical vapor deposition method is applied on the silicon oxide film 2. The process of forming a polycrystalline or amorphous silicon thin film having a thickness of about 10 to 200 nm at a temperature of about 550-625 ° C. and then forming an active layer region 3 of polycrystalline or amorphous silicon through photolithography is performed.

제2도는 다결정 실리콘 초박막 전계효과 트래지스터의 게이트 절연막 제조방법을 나타낸 것으로 다결정(혹은 비정질)실리콘의 활성층(3)에 급속열처리법과 열전기 로에 의한 열산화 방법을 이용하여 10nm이하의 얇은 실리콘 열산화막(4)을 성장하고 그 위에 탄탈륨 산화막(5)을 50-200nm의 두께로 증착한후 급속열처리 방법 또는 열전기로를 이용하여 700-1000℃정도 온도에서 산소분위기에서 열처리를 하고, 열처리된 탄탈륨 산화막(5)위에 625℃정도의 온도에서 저압화학 증착법을 이용하여 300-350nm의 두께로 다결정 실리콘(6)을 형성한 과정을 나타낸 것이다.2 shows a method of manufacturing a gate insulating film of a polycrystalline silicon ultra thin film field effect transistor. A thin silicon thermal oxide film of less than 10 nm is formed by using a rapid thermal treatment method and a thermal oxidation method using a thermoelectric furnace on an active layer 3 of polycrystalline (or amorphous) silicon ( 4) After growing and depositing a tantalum oxide film (5) having a thickness of 50-200nm, and heat treatment in an oxygen atmosphere at a temperature of about 700-1000 ℃ using a rapid heat treatment method or a thermoelectric furnace, the heat-treated tantalum oxide film ( 5) shows the process of forming the polycrystalline silicon (6) to a thickness of 300-350nm using a low pressure chemical vapor deposition method at a temperature of about 625 ℃.

제3도는 게이트 전극을 형성하는 과정을 나타낸 것으로, 게이트 전극을 형성하기 위하여 920℃ 온도에서 POCl3을 도핑하고 도핑된 다결정 실리콘을 사진 식각 방법으로 게이트 전극(6)을 정의하고 식각한 후 소오스와 드레인을 형성하기 위하여 M채널(n-channel) MOS 트랜지스터인 경우에는 (버스) As+이온을 5×1015/㎠이상 P채널(p-channel) MOS 트랜지스터인 경우에는 BF2를 5×1015/㎠이상이온 주입한 과정을 나타낸 것이다.FIG. 3 illustrates a process of forming a gate electrode. To form a gate electrode, doping POCl 3 at a temperature of 920 ° C. and defining a gate electrode 6 by photolithography and etching the doped polycrystalline silicon are performed. In order to form a drain, the (bus) As + ion is 5 × 10 15 / cm 2 or more in the case of an M-channel (n-channel) MOS transistor, and the BF 2 is 5 × 10 15 in the case of a p-channel MOS transistor. / ㎠ shows the process of implanting ions.

제4도는 저온화학 증착법을 이용하여 저온산화막(low temperature oxide)(10)을 500nm정도의 두께로 증착한 후, 사진식각법을 이용하여 전극부분을 정의하고, Al/1% Si막을 증착하여 전극(9)을 형성과정을 나타낸 것이다.4 is a low temperature oxide (10) is deposited to a thickness of about 500nm by using a low-temperature chemical vapor deposition method, the electrode portion is defined using a photolithography method, Al / 1% Si film is deposited by electrode (9) shows the formation process.

따라서 본 발명은 실리콘 산화막과 탄탈륨 산화막을 이중막으로 적층시켜 다결정 실리콘 초박막 전계효과 트랜지스터를 제조하면 실리콘 산화막이나 실리콘 질화막을 게이트 절연막으로 사용한 경우보다 구동전류가 증가되고, subthreshold slope 특성이 개선된다.Therefore, in the present invention, when the silicon oxide film and the tantalum oxide film are stacked in a double layer to manufacture a polycrystalline silicon ultra thin field effect transistor, the driving current is increased and the subthreshold slope characteristics are improved compared to when the silicon oxide film or the silicon nitride film is used as the gate insulating film.

Claims (1)

전계효과 트랜지스터 제조방법에 있어서 실리콘 웨이(1) 상면에 실리콘 산화막(2)를 저압화학 증착법이나 열전기로를 이용하여 500nm 정도 두께를 증착하고, 상기 상면에 다결정 또는 비정질 실리콘 박막층(3)을 저압화학증착법을 이용하여 500∼655℃정도의 온도에서 10∼200nm정도의 두께로 증착하고 사진 식각작업을 통하여 다결정 또는 비정질 실리콘의 활성영역(3)을 형성하는 단계와, 실리콘의 활성층(3)에 급속열처리법과 열전기로에의 열산화 방법을 이용하여 10nm이하의 얇은 실리콘 열산화막(4)을 성장하고 그 위에 탄탈륨 산화막(5)을 50-200nm의 두께로 증착하고, 급속열처리 방법 또는 열전기로 이용하여 700∼1000℃정도 온도에서 산소분위기에서 열처리하고 열처리된 위에 625℃정도의 온도에서 저압화학 증착법을 300-350nm의 두께로 이용하여 다결정 실리콘(6)을 형성하는 단계와, 게이트 전극을 형성하기 위하여 920℃ 온도에서 POCl3을 도핑하고 도핑된 다결정 실리콘을 사진식각방법으로 전극(6)를 정의하고 식각한 다음 불순물을 이온주입하고 저온 산화막(low temperature oxide)(10)을 500nm정도의 두께로 도핑하고 열처리한 후 사진식각법을 이용하여 전극부분을 정의하고, Al/1% Si막을 도포하여 전극(9)을 형성하는 단계들로 이루어짐을 특징으로하는 다결정 실리콘 초박막 전계효과 트랜지스터 제조방법.In the field effect transistor manufacturing method, a silicon oxide film 2 is deposited on the silicon wafer 1 by a low pressure chemical vapor deposition method or a thermoelectric furnace, and a thickness of about 500 nm is deposited on the upper surface, and the polycrystalline or amorphous silicon thin film layer 3 is subjected to low pressure chemical vapor deposition. Depositing a thickness of about 10 to 200 nm at a temperature of about 500 to 655 ° C. using a deposition method, and forming an active region 3 of polycrystalline or amorphous silicon through photolithography, and rapidly forming the active layer 3 of silicon. By using a heat treatment method and a thermal oxidation method to a thermoelectric furnace, a thin silicon thermal oxide film 4 of 10 nm or less is grown, and a tantalum oxide film 5 is deposited thereon to a thickness of 50-200 nm, and used as a rapid heat treatment method or a thermoelectric furnace. Heat treatment in an oxygen atmosphere at a temperature of about 700 ~ 1000 ℃, and polycrystalline yarn using low pressure chemical vapor deposition at a temperature of about 625 ℃ and a thickness of 300-350nm. Forming a cone (6), doped with POCl 3 eseo 920 ℃ temperature to form the gate electrode, and a defines the electrode to the doped polysilicon as a photolithography method (6) and etching ions the following impurity implantation and low temperature After doping the oxide film (low temperature oxide) 10 to a thickness of about 500nm and heat treatment, the electrode portion is defined using a photolithography method, and the electrode 9 is formed by applying an Al / 1% Si film. Method for producing a polycrystalline silicon ultra-thin field effect transistor, characterized in that made.
KR1019900021815A 1990-12-26 1990-12-26 Method of manufacturing polycrystalline silicon ultra thin field effect transistor Expired - Fee Related KR940000989B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100624916B1 (en) * 2000-01-31 2006-09-19 주식회사 하이닉스반도체 Gate electrode formation method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100624916B1 (en) * 2000-01-31 2006-09-19 주식회사 하이닉스반도체 Gate electrode formation method

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