KR900006815Y1 - Automatic switching circuit of melody in case of video signal output for vcr - Google Patents
Automatic switching circuit of melody in case of video signal output for vcr Download PDFInfo
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- KR900006815Y1 KR900006815Y1 KR2019870020304U KR870020304U KR900006815Y1 KR 900006815 Y1 KR900006815 Y1 KR 900006815Y1 KR 2019870020304 U KR2019870020304 U KR 2019870020304U KR 870020304 U KR870020304 U KR 870020304U KR 900006815 Y1 KR900006815 Y1 KR 900006815Y1
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- melody
- comparator
- vcr
- adder
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B33/00—Constructional parts, details or accessories not provided for in the other groups of this subclass
- G11B33/10—Indicating arrangements; Warning arrangements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B15/00—Driving, starting or stopping record carriers of filamentary or web form; Driving both such record carriers and heads; Guiding such record carriers or containers therefor; Control thereof; Control of operating function
- G11B15/02—Control of operating function, e.g. switching from recording to reproducing
- G11B15/026—Control of operating function, e.g. switching from recording to reproducing by using processor, e.g. microcomputer
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- Computer Hardware Design (AREA)
- Television Receiver Circuits (AREA)
Abstract
내용 없음.No content.
Description
제1도는 종래의 멜로디 차단회로도.1 is a conventional melody blocking circuit diagram.
제2도는 본 고안에 따른 VCR의 영상출력시 멜로디 자동 차단회로도.2 is a melody automatic cut-off circuit diagram of the video output of the VCR according to the present invention.
제3도는 제2도의 각부 파형도.3 is a waveform diagram of each part of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 동기분리회로 C1-C3: 콘덴서1: Synchronous separation circuit C 1 -C 3 : Condenser
2 : 동기증폭부 R1-R6: 저항2: Synchronous Amplifier R 1- R 6 : Resistance
3 : 가산기 IC1-IC2: 비교기3: Adder IC 1 -IC 2 : Comparator
4 : 적분기 I1: 인버터4: Integrator I 1 : Inverter
5 : 멜로디 IC Q1,Q2: 트랜지스터5: Melody IC Q 1 , Q 2 : Transistor
본 고안은 VCR의 멜로디 차단회로에 관한것으로 특히 테이프의 FF/REW 동작시에 발생되는 멜로디소리를 영상출력시에 자동차단 시키도록한 VCR의 영상출력시 멜로디 자동차단회로에 관한 것이다.The present invention relates to a melody cut-off circuit of a VCR, and more particularly to a melody cut-off circuit of a VCR for outputting a melody sound generated during FF / REW operation of a tape.
일반적으로 VCR은 모니터와 연결되어 보도록되어 있어 VCR의 FF/REW 동작시 멜로디를 발생시키는데, 이는 VCR의 튜너를 통해 TV의 채널방송을 모니터로 시청하거나 VCR의 라인아웃(Line out)에서 영상신호가 출력될시에는 영상신호와 멜로디소리가 혼합되게 된다.In general, the VCR is connected to the monitor to generate the melody during the FF / REW operation of the VCR. This allows the VCR tuner to watch TV channel broadcasts on the monitor or the video signal from the VCR line out. When output, the video signal and the melody sound are mixed.
이러한 경우 종래에는 제1도에서 도시된 멜로디 스위치(SW1)를 오프시켜 스피커(SP)를 통해 출력되는 멜로디 소리를 수동으로 차단시키게 되므로 조작이 불편할뿐만 아니라 매우 번거롭게 되는 문제점이 있었다.In this case, conventionally, the melody switch SW 1 shown in FIG. 1 is turned off to manually block the melody sound output through the speaker SP, and thus the operation is inconvenient and very troublesome.
이에 본 고안은 상기한 문제점을 개선시키기 위해 안출된 것으로써 간단한 멜로디 차단회를 구성시켜 영상신호가 출력될시에는 자동으로 멜로디소리를 차단시키도록 한것으로 이하 그 기술구성을 첨부된 도면에 따라 설명하면 다음과 같다.Accordingly, the present invention is to devise a simple melody blocking session to improve the above problems to automatically cut off the melody sound when the video signal is output. As follows.
제2도는 본 고안에 따른 VCR의 영상출력시 멜로디 자동차단회로를 나타낸것으로 그의 연결구성을 살펴보면, 비데오 출력단(Vout)은 동기분리회로(1)와 동기증폭부(2)에 순차연결되는 동기증폭부(2)의 출력단을 콘덴서(C1)(C2)와 저항(R3)(R4)을 거쳐 비교기(IC1)의 플러스입력단에 접속되고 비교기(IC1)의 마이너스 입력단은 저항(R2)을 거쳐 전원단(Vcc)에 접속되고, 그의 출력단은 인버터(I1)와 콘덴서(C3) 및 다이오드(D1)(D3)와 저항(R6)을 거쳐 가산기(3)의 일단에 접속되며 동시에 다이오우드(D2)와 저항(R5), 콘덴서(C3)의 적분기(4)를 거쳐 비교기(IC2)의 플러스입력단에 접속되고, 상기 비교기(IC2)의 마이너스 입력단은 엄의전압(VA)과 연결되며 그의 출력단은 가산기(3)의 타일단에 접속되어 가산기(3)의 출력단이 에미터가 접지접속된 트랜지스터(Q1)(Q2)의 베이스에 각각 접속되고, 상기 트랜지스터(Q1)(Q2)의 콜렉터는 멜로디IC(5)에 각각 연결되는 구성으로, 상기 회로구성의 동작상태 및 작용효과를 첨부된 도면에 따라 설명하면 다음과 같다.2 shows a melody auto-circuit circuit when outputting a video of a VCR according to the present invention. Looking at the connection configuration thereof, the video output terminal Vout is sequentially connected to the synchronous separation circuit 1 and the synchronous amplifier 2. The output terminal of the negative unit 2 is connected to the positive input terminal of the comparator IC 1 via the capacitor C 1 (C 2 ) and the resistor R 3 (R 4 ), and the negative input terminal of the comparator IC 1 is connected to the resistor ( Is connected to the power supply terminal Vcc via R 2 ), and its output terminal is an adder 3 via an inverter I 1 , a capacitor C 3 , a diode D 1 , D 3 , and a resistor R 6 . At the same time, connected to the positive input terminal of the comparator IC 2 via the integrator 4 of the diode D 2 , the resistor R 5 , and the capacitor C 3 , and the negative of the comparator IC 2 . the input terminal is connected to the voltage (V a) of the moth its output terminal is connected to the other end of the adder 3 is output from the adder (3) the emitter is connected to ground transistor (Q 1) are respectively connected to the base of (Q 2), the transistor (Q 1) (Q 2) collector to configure each connected to Melody IC (5), the operating status, operations and effects of the circuit configuration of the When described according to the accompanying drawings as follows.
제2도에서, 비데오 출력단(VOUT)으로 영상신호가 출력되면 동기분리회로(1)와 동기증폭부(2)를 거쳐 제3도의 (a)와 같은 수평동기신호와 수직동신호가 출력되어 콘데서기(C1)(C2)와 저항(R3)(R4)을 거쳐 제2도의 (b)와 같이 되어 비교기(IC1)의 플러스 입력단으로 인가되고 비교기(IC1)이 마이너스 입력단으로는 저항(R1)(R2)에 의해 분압된 전압이 인가되므로 이전압은 적분파형이 피크값인와 같게 된다.In FIG. 2, when the video signal is output to the video output terminal V OUT , the horizontal synchronizing signal and the vertical synchronizing signal as shown in (a) of FIG. 3 are output through the synchronizing separation circuit 1 and the synchronizing amplifier 2. Conde AD (C 1) (C 2) and a resistor (R 3) (R 4) through a is as in the second degree (b) is applied to the plus input terminal of the comparator (IC 1) a comparator (IC 1) a negative input terminal Divided by the resistor (R 1 ) (R 2 ) This voltage is applied so that the integral waveform has a peak value Becomes the same as
그러므로 상기 비교기(IC1)의 출력단으로는 제3도의 (c)와 같이 하이레벨(VH)과 로우레벨(VC)을 갖는데, 이 출력은 (a) 파형의 1필드 마다 수직동기 부분에서 펄스가 발생된다.Therefore, the output terminal of the comparator IC 1 has a high level (V H ) and a low level (V C ), as shown in (c) of FIG. 3, and the output is (a) in the vertical synchronization portion of each field of the waveform. A pulse is generated.
상기발생 된 펄서는 인버터(I1)를 거쳐 반전되어 (d) 파형과 같이 되며 콘덴서(C3)와 다이오우드(D1)에 의해 로우레벨(V1)은 (e)와같은 O레벨로 되고, 하이레벨(VH)은 2배가 된다(2VH).The generated pulser is inverted through the inverter (I 1 ) and becomes a waveform (d), and the low level (V 1 ) becomes an O level such as (e) by the capacitor (C 3 ) and the diode (D 1 ). , The high level (V H ) is doubled (2V H ).
이 파형은 다이오우드(D3)를 거쳐 가산기(3)의 일측으로 인가되고, 한편 상기 비교기(IC1)의 출력파형은 다이오우드(D2)를 거쳐 (f)와같이 내거티브펄스 성분이 제거되고 포지티브펄스 성분만이 적분기(4)를 거쳐 제3도의 (g) 파형과 같이 비교기(IC2)의 플러스입력단으로 인가된다.The waveform is applied to one side of the adder 3 via the diode D 3 , while the output waveform of the comparator IC 1 is removed through the diode D 2 and the negative pulse component is removed as shown in (f). Only the positive pulse component is applied via the integrator 4 to the positive input terminal of the comparator IC 2 as shown in the waveform (g) of FIG.
이때 비교기(IC2)의 마이너스 입력단으로는 임의전압(VA)이 인가되므로 임의전압(VA)과 (g) 파형이 비교되어 비교기(IC2)의 마이너스 제3도의 (h) 파형이 출력되어 가산기(3)의 타일측으로 인가된다.At this time, since the arbitrary voltage (V A ) is applied to the negative input terminal of the comparator (IC 2 ), the arbitrary voltage (V A ) and the (g) waveform are compared to output the (h) waveform of negative third diagram of the comparator (IC 2 ). Is applied to the tile side of the adder 3.
상기 가산기(3)의 인가된 (e) 파형과 (h) 파형을 가산기(3)에서 가산되어 제3도의 (i)와 같이 하이레벨(VH)을 갖는 파형이 출력되므로 트랜지스터(Q1)(Q2)를 각각 구동시켜 멜로디(5)의 출력멜로디를 차단시킬 수 있게된다.The transistor (Q 1 ) because the (e) and (h) waveforms of the adder 3 are added by the adder 3 to output a waveform having a high level V H as shown in (i) of FIG. 3. By driving (Q 2 ), the output melody of the melody 5 can be blocked.
그러므로 동기신호가 입력되면 그것이 충분히 증폭되어 비교기(IC1)와 인버터(I1) 및 비교기(IC2)를 거쳐 일정한 리벨(VH)이 가산기(3)의 출력단으로 출력되므로 트랜지스터(Q1)(Q2)를 구동시켜 멜로디소리를 차단시키게 된다.Therefore, when the synchronous signal is input, it is sufficiently amplified so that a constant level V H is output to the output terminal of the adder 3 through the comparator IC 1 , the inverter I 1 , and the comparator IC 2 , and thus the transistor Q 1 . (Q 2 ) is driven to block the melody sound.
따라서 본 고안에 따른 VCR의 영상출력시 멜로디 자동차단회로를 이상의 설명에서와 같이 VCR 테이프의 FF/REV 동작시에 반대되는 멜로디소리를 차단시켜 TV 망송국으로부터 수신되는 소리 및 영상이 멜로디소리와 혼합되는 불편을 제거시키며 또한 이를 자동적으로 조절되도록 되어 있어 편리한 효과를 갖게된다.Therefore, in the video output of the VCR according to the present invention, the melody car cut-off circuit blocks the melody sound opposite to the FF / REV operation of the VCR tape as shown in the above description, so that the sound and the image received from the TV network are mixed with the melody sound. It eliminates the inconvenience and is also automatically adjusted to have a convenient effect.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019870020304U KR900006815Y1 (en) | 1987-11-24 | 1987-11-24 | Automatic switching circuit of melody in case of video signal output for vcr |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019870020304U KR900006815Y1 (en) | 1987-11-24 | 1987-11-24 | Automatic switching circuit of melody in case of video signal output for vcr |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR890011668U KR890011668U (en) | 1989-07-13 |
| KR900006815Y1 true KR900006815Y1 (en) | 1990-07-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019870020304U Expired KR900006815Y1 (en) | 1987-11-24 | 1987-11-24 | Automatic switching circuit of melody in case of video signal output for vcr |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR900006815Y1 (en) |
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1987
- 1987-11-24 KR KR2019870020304U patent/KR900006815Y1/en not_active Expired
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| Publication number | Publication date |
|---|---|
| KR890011668U (en) | 1989-07-13 |
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