KR20240019110A - System and method using multilayer optical lattice qubit arrays for quantum computing - Google Patents

Abstract

A quantum computing (QC) system includes a first plurality of logical qubits in a first substantially planar region and a second plurality of logical queues in a second substantially planar region substantially parallel to the first substantially planar region. Contains bits. At least some of the first plurality of logical qubits are configured to interact with each other, and at least some of the second plurality of logical qubits are configured to interact with each other, and the first plurality of logical qubits are configured to interact with each other. It is configured to interact with at least some of the The QC system may include an additional plurality of logical qubits in additional substantially planar regions substantially parallel to the first and second substantially planar regions, wherein at least one of the second plurality of logical qubits Some may be configured to interact with one or more of the additional plurality of logical qubits.

Description

System and method using multilayer optical lattice qubit arrays for quantum computing

This application relates generally to quantum computing (QC), and more particularly to quantum computer architectures employing lattice array structures of one or more dimensions.

The technological history toward scalable quantum computing is becoming more diverse. Demonstrated performance across models of varying merit varies widely depending on the type of physical quantum bit (also called “qubit”) employed by each approach. Approaches based on trapped atomic ions or superconducting qubits have continued to lead the field for over two decades. Recent advances in captured Rydberg atom approaches are increasing their potential for success and importance in this field.

The present invention provides quantum computer architectures employing lattice array structures of one or more dimensions.

Certain implementation examples disclosed herein include one or more to implement and interconnect quantum gates in which two or more logical qubits (e.g., each logical qubit comprising one or more physical qubits) can be simultaneously entangled. Provides a quantum computer architecture employing a three-dimensional lattice array structure. Certain implementations disclosed herein provide quantum microprocessor architecture and gate array design platforms for quantum processing chips similar to field programmable gate arrays (FPGAs) that can advantageously provide a degree of reconfigurability. Certain implementations disclosed herein include quantum processing chips or boards (e.g., application specific integrated circuits (ASICs)) that can be optimized for a particular application and advantageously provide custom design flexibility. Quantum microprocessor architecture and gate array design platforms for electrical and/or optical circuits (integrated optical gratings) are provided.

Certain implementations disclosed herein provide a quantum computing (QC) system comprising a plurality of qubits arranged substantially within a plurality of substantially planar regions (e.g., planes; layers) that are substantially parallel to each other, , at least some of the substantially planar regions include two or more qubits, and one or more qubits of each substantially planar region interact with one or more qubits of at least one adjacent substantially planar region. It is configured to work. For example, the QC system may include a plurality of 2D grid layers (e.g., atomic; photonic), the grid layers being substantially parallel, and the QC system located within a region spanning multiple grid layers. It may include a multi-qubit gate array having the plurality of qubits arranged as a plurality of multi-qubit gates. The multi-qubit gate array is comprised of nitrogen-vacancy or NV centers (e.g., fabricated in diamond or other crystals), arrays of trapped Bose-Einstein condensates (BECs). , and/or configured to selectively process natural (e.g., uncharged) atoms, Rydberg atoms, and/or other qubits, confined within multiple lattice layers, and/or others. It can include grids that are In certain such examples, these substantially parallel grid layers may be substantially arranged within a plurality of substantially planar regions (e.g., planes; levels), and at least one of the qubits of at least one substantially planar region may be substantially parallel. Some are configured to interact (e.g., become quantum mechanically entangled) with at least some of the qubits of at least one other (e.g., adjacent) substantially planar region.

Particular implementations disclosed herein include lattice configurations having multiple globally connected qubits arranged as arrays of three-dimensional (3D) lattice structures (e.g., to form gates), and supporting multiple qubits simultaneously. Gate operations are made possible by qubits arranged in geometric layouts. The specific implementation examples disclosed herein address a common set of important challenges for building optimally efficient quantum computers. Chief among these challenges is how to implement the maximum number of nearest neighbors, next-nearest neighbors, next-next, etc. to effect multi-qubit quantum gate operations naturally or geometrically from a single gate operation. How to fabricate geometries of qubits in which qubits, such as their nearest neighbors, can be entangled simultaneously (e.g., U.S. Published Provisional Patent Application filed May 7, 2021, each of which is incorporated herein by reference in its entirety) No. 63/186,037; U.S. Published Provisional Patent Application No. 17/090,747, filed November 5, 2020; U.S. Published Provisional Patent Application No. 62/933,148, filed November 8, 2019).

In certain implementations, a quantum computing (QC) system may include a first plurality of logical qubits within a first substantially planar region and a second plurality of logical qubits within a second substantially planar region substantially parallel to the first substantially planar region. It includes a plurality of logical qubits. At least some of the first plurality of logical qubits are configured to interact with each other, and at least some of the second plurality of logical qubits are configured to interact with each other, and the first plurality of logical qubits are configured to interact with each other. configured to interact with at least some of the bits. In certain implementations, the QC system includes an additional plurality of logical qubits in additional substantially planar regions substantially parallel to the first and second substantially planar regions, wherein the second plurality of logical qubits at least some of which are configured to interact with one or more of the additional plurality of logical qubits.

In certain implementations, a quantum computing (QC) system includes a plurality of confinement regions configured to contain logical qubits that form quantum gates within a multi-qubit lattice array having two or more dimensions. The quantum gates are configured to perform quantum logic operations that naturally involve three or more logical qubits without relying on connections of 1- and 2-qubit gates.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate one or more implementations described herein and set forth these implementations together with the detailed description of the invention.
1 schematically illustrates a perspective view of an example quantum computing (QC) system including substantially planar regions in accordance with certain implementation examples described herein.
FIG. 2A schematically illustrates a perspective view of an example system including 36 logical qubits within three substantially planar regions substantially parallel to each other in accordance with certain implementations described herein.
FIG. 2B schematically illustrates a perspective view of another example system including 60 logical qubits within three substantially planar regions substantially parallel to each other in accordance with certain implementations described herein.
3A illustrates a plurality of logic arrays arranged within three substantially planar regions substantially parallel to each other (e.g., compatible with the example systems of FIGS. 2A and 2B) in accordance with certain implementations described herein. A perspective view of qubits is schematically illustrated.
3B and 3C each schematically illustrate a perspective view of a plurality of logical qubits arranged within five substantially planar regions substantially parallel to each other in accordance with specific implementation examples described herein.
4A and 4B each show top views (e.g., along the z-axis) of an example system having a set of planar regions each containing a corresponding plurality of logical qubits according to specific implementations described herein. (following) and a perspective view are schematically illustrated.
5A and 5B each show top views (e.g., z- along axis) and perspective views are schematically illustrated.
Figure 5C schematically illustrates a perspective view similar to the case of Figure 5B according to specific implementation examples described herein.
6A and 6B are top views (e.g., z- along axis) and perspective views are schematically illustrated.
Figure 6C schematically illustrates a perspective view similar to the case of Figure 6B according to specific implementation examples described herein.
6D and 6E each show top views (e.g., z- along axis) and perspective views are schematically illustrated.
Figure 6F schematically illustrates a perspective view similar to the case of Figure 6E according to specific implementation examples described herein.
7A-7E illustrate an example multi-qubit gate cell (e.g., a target within the center) formed between multiple 2D planar optical trap regions and having multiple addressing laser beams, according to certain implementations described herein. A perspective view of a C ²⁰ NOT gate cell or C ²⁰ ϕ gate cell) having 21 qubits in a pyrochlore configuration with control qubits and control qubits elsewhere is shown schematically.
8A-8E schematically illustrate various diagrams of trapping laser beams according to specific implementations described herein.
9A-9B schematically illustrate a perspective view of a three-layer 10 x 10 atom trap grid created by alternating arrays of trapping laser beams in accordance with certain implementations described herein.
Figure 9C schematically illustrates a top view of the structure of Figures 9A-9B according to certain implementations described herein.
10A shows a partially assembled QC system comprising a three-layer 10 x 10 atomic grid with three sets of addressing laser beams and two alternating arrays of trapping laser beams in accordance with certain implementations described herein. Schematically illustrate a perspective view.
10B-10D show different views from different directions of two intersecting arrays of addressing laser beams and trapping laser beams of three sets of 10A according to certain implementations described herein.
10E shows another partially assembled QC system comprising a three-layer 10 x 10 atomic grid with four sets of addressing laser beams and two alternating arrays of trapping laser beams in accordance with certain implementations described herein. A perspective view is schematically illustrated.
FIGS. 10F-10H show different views from different directions of the two intersecting arrays of the four sets of addressing and trapping laser beams of FIG. 10E according to certain other implementations described herein.
11A is a schematic illustration of the three-layer 10 x 10 3D atomic lattice of FIGS. 9A-9C and 10A-10D viewed through the first photodetector port 242a according to certain implementations described herein. Illustrate.
FIG. 11B schematically illustrates a side cross-sectional view of the structure of FIG. 11A according to certain implementations described herein.
Figure 12 schematically depicts an example perspective view of an example assembled QC system corresponding to Figures 8E, 9A, 10A and 11A in accordance with certain implementations described herein.
Figure 13 shows a set of tables comparing the total number of qubits that can be simultaneously entangled at given gate fidelities for various multi-qubit lattice arrays according to specific implementation examples described herein.

outline

Specific implementation examples described herein include arrays of three-dimensional (3D) lattice structures (e.g., cells) where simultaneous multi-qubit gate operations are enabled by qubits arranged in geometric layouts. It includes lattice configurations with multiple globally connected qubits arranged as . Certain implementations disclosed herein advantageously increase the number of lattice layers and allow for the limits of current implementations using current square-based photonic lattices for Rydberg atoms (e.g. The number of qubits that can be entangled simultaneously (with possible gate fidelities) and potentially achievable qubit densities in hexagonal multilayer surface-trap geometries for ions. increases.

Specific implementation examples disclosed herein address the challenges of building an optimally efficient quantum computer. One such challenge is that the maximum number of nearest neighbor, next nearest neighbor, next next nearest neighbor, etc. , how to engineer the geometries of qubits that can be simultaneously entangled to provide (geometrically) within a single gate operation. This engineering fabrication challenge involves equal parts of both. One part is how to confine (e.g., capture; fabricate the crystal lattice region) the qubits within optimal entangled geometries. This confinement usually involves fabricating complex intersections of several layers with precise periodic positions of defect sites, electrodes and/or magnetic fields within the crystals. Another part of the engineering fabrication challenge is how to process (e.g., illuminate; excite; manipulate) and read (e.g., detecting or imaging). This addressing can often go beyond the creation of simultaneous entanglement between as many qubits as possible, which can be accomplished with global addressing. Rather, developing the full computational power of numerous entangled qubits may also involve manipulating and reading out the individual qubit states of the desired multi-qubit gate operation, leveraging the ability to process each qubit as needed. . This capability allows the intrinsic computational power of each quantum computing gate to participate entirely as logical qubits in each gate operation, while at the same time increasing the number of entangled qubits exponentially (e.g. , in proportion to 2 to its capabilities), so it can be very important. Additionally, overhead (e.g., error correction qubits; redundant qubits; accessory qubits) must be considered, as the size of quantum computing architectures requires that surface codes require a very large number of qubits. The scales used to correct errors increase dramatically (e.g., the number of digits varies) as the scale increases. Accordingly, the overall advantage of entangling more individually simultaneously addressable (e.g. logical) qubits within the preceding gate cells is to significantly reduce the use of the added overhead of different orders of magnitude accompanying surface code error correction. This can even significantly exceed the initial exponential speedup seen.

Certain implementations disclosed herein include multiple two-dimensional (2D) (e.g., planar) qubit arrays (e.g., layers) substantially parallel to each other, forming arrays of three-dimensional (3D) cells. It can be composed as. The arrays of cells may resemble or be referred to as 3D crystal structures. Captured neutral (e.g. uncharged) atomic qubits or Rydberg atomic qubits in optical lattice structures to illustrate the nature of quantum interactions for which various implementations are exploited (e.g. optimized). (see, e.g., I. Bloch's "Quantum coherence and entanglement with ultracold atoms in optical lattices" (Nature 453, 1016 (2008))), other implementations are described here, but other implementations utilize both structure and function. One or more selective qubit technologies (e.g., qubits trapped in natural crystal lattices; artificially formed crystal structures) within equivalent lattice structures can be used (e.g., within a single gate). maximum number of nearest neighbors, next nearest neighbor, next nearest neighbor, etc. to provide cases previously provided by concatenations of hundreds or thousands of one- and two-qubit quantum gate operations. of qubits can be simultaneously entangled, forming an extension of pyrochlore-like structures).

One exemplary alternative description of atomic vacancy centers in crystals (e.g., nitrogen-vacancy centers, hereinafter simply referred to as “NV centers” in diamonds) is also shown. Recently, progress has been made in terms of full connectivity between up to 10 qubits and multiple entangled states with up to 7 qubits (e.g., “A 10-qubit solid-state spin” by C. E. Bradley et al. register with quantum memory up to one minute"(Phys. Rev. X 9, 031045(2019)). These properties of NV centers, along with their atomic-like properties, enable optimal geometric approaches for simultaneous entanglement and addressing of a maximum number of qubits individually in multilayer optical lattices (e.g., all qubits enabling them to implement one or more examples of qubit technology that can be directly applied to the specific implementations described herein, such as enabling both initialization of qubits, performance of gate operations on them, and reading of their values. Still other implementation examples include other optional qubit technologies, such as captured Bose-Einstein condensate (BEC); neutral molecules; phonons; photons; and others may be used.

Certain implementations of the quantum computing (QC) system described herein advantageously have an optimal number of qubits that are the nearest neighbors, the next nearest neighbors, and the next next nearest neighbors. , and potentially more, providing a multi-layered architecture for simultaneous entanglement. Particular implementation examples include geometries configured to enable optimal combinations of electrical, magnetic and optical addressing, control, detection and readout depending on the needs of fabricating scalable quantum processors. Arrays of globally connected qubits provide more efficient and flexible options for executing quantum algorithms in hardware than designs where entangled gate operations are limited to specific pairs due to the type of qubits employed or their layout. This improved efficiency and flexibility increases with the number of qubits in the array. Adding the capability to perform gate operations involving two or more qubits simultaneously promotes significant efficiency gains compared to designs limited to 1- and 2-qubit gates, allowing tens of gates to operate on a single 4-qubit gate. It can be replaced with a qubit gate. Certain implementations disclosed herein address the problems of one-dimensional and two-dimensional geometric configurations (e.g., limitations on connectivity; the requirement to control each qubit in increasingly dense gate arrays when limited to only two dimensions). It utilizes multiple qubit arrays (e.g., multiple directly connected planar lattices) to advantageously avoid crowding of components. In certain implementations, multidimensional cells of qubits are formed to resemble crystals such as pyrochlores. In certain implementations, multidimensional cells of qubits are configured such that their nearest neighbors, next-nearest neighboring qubits (e.g., within a cell; across cells; across layers), and qubits beyond them perform selected gate operations. Depending on how they are simultaneously entangled, they can be reorganized and formed into various crystal structures. Using many qubits participating per gate can also reduce requirements for circuit depth, error correction, and interference mitigation. Reconfigurable component cells may enable quantum FPGA (QFPGA) and ASIC (QASIC) layouts (e.g., chips).

Specific implementations of the QC system disclosed herein include arrays of three-dimensional (3D) lattice structures (e.g., cells) with simultaneous multi-qubit gate operations enabled by qubits arranged in geometric layouts. It includes multi-layered configurations with multiple fully connected qubits arranged as . For example, multiple planar qubit arrays (e.g., rows and columns; lattice) within layers may be substantially parallel to each other and may resemble, or may be referred to as, crystal structures. Arrays of 3D cells can be formed. In certain implementations, inefficient photonic or other interconnections (e.g., quantum far-field transport (e.g., between nearest-neighboring qubits, next-nearest-neighboring qubits, etc., across multiple substantially planar array regions (e.g., layers; levels; planes) without requiring quantum teleportation. The qubits are placed in multi-qubit lattice containment zones (e.g., parallel neutral atom-trap arrays; NV centers) to directly enable optimal coherent connectivity (e.g., entanglement). ) may be confined (e.g., captured; suspended; restrained) within. These specific implementations can significantly accelerate efficiency gains compared to designs limited to one- and two-qubit gates, while providing a geometrically symmetrical design that provides the ability to perform gate operations involving more than two qubits. Utilize cell structures. Certain other implementations include multiple two-dimensional (2D) qubit grid arrays (e.g., planar grids; grids; rows and columns).

Various implementation examples are described here according to the physics of neutral atom (e.g. uncharged atom, Rydberg atom) qubit approaches, but other qubit approaches (e.g. NV centers; superconducting cue bits; others mentioned herein) may also be used according to the specific implementation examples described herein without loss of generality.

Specific implementations of the QC system described herein include a plurality of multi-qubit three-dimensional (3D) gate cells, each cell containing at least three qubits that can be connected throughout, spanning three dimensions simultaneously, and The multi-qubit cells are configured for gate operations of two or more of the multi-qubit gates. The QC systems of these specific implementations enable direct optimal coherent connectivity or entanglement between nearest-neighboring qubits, next-nearest-neighboring qubits, etc., across multiple array layers, levels or planes. requires a transition to and from photonic qubits, such as parallel neutral atom capture arrays, or other inefficient interconnections (e.g., interconnections that introduce significant losses and/or time delays). and may include multiple substantially parallel qubit containment lattices. The multi-qubit cells can be configured to take advantage of geometric symmetry that allows multiple qubit gates to be naturally affected in a single gate operation without relying on the connection of multiple 1- and 2-qubit gates. Affecting the symmetry of the equilateral coupling distances between multiple qubits within a cell allows more than two entangled qubits to operate simultaneously, which would otherwise involve only 1- and 2-qubit gates. It is possible to perform gate operations that could have been requested.

Other specific implementations disclosed herein include a plurality of 2D array layers (e.g., 2D lattices; planes; grids) substantially parallel to each other, two or more qubits, and at least one neighboring 2D array. A QC system comprising a plurality of qubits substantially arranged within at least a portion of the 2D array layers including one or more qubits of each array layer configured to interact with one or more qubits of the layer. to provide. The QC system may include a plurality of atomic trap layers (e.g., 2D optical grating traps) that are substantially parallel to each other, and the QC system may include a plurality of atomic trap layers located within regions between and/or within the trap layers. It may further include multi-qubit 3D gate arrays including the plurality of qubits arranged as multi-qubit gates. For example, the qubits of the multi-qubit gate array may be atomic qubits containing neutral atoms (e.g., uncharged atoms, Rydberg states), NV centers, or other qubit species. It includes 2D trap arrays configured to be provided. In examples of Rydberg atoms, NV centers and other atomic qubit species, the qubits are confined within lattices (e.g., within potential wells; trapped within atomic vacancy centers), which An optical beam (e.g., a laser) may be generated by gratings and may be substantially arranged within a plurality of substantially parallel trap array layers (e.g., gratings; levels; planes), at least At least one 2D trap array configured to directly interact (e.g., quantum mechanically entangle) with at least some of the qubits of one other (e.g., neighboring) substantially parallel trap array layer. It has at least some of the qubits in a layer.

In each implementation of the QC system described herein, the symmetric or equilateral coupling geometries of multiple qubits per cell allow more complex quantum gates to be performed in a single gate operation, providing improved circuit depth, error correction, and Requirements for interference mitigation can be further reduced. Compatible configuration cells may enable quantum FPGA (QFPGA) and ASIC (QASIC) layouts (e.g., chips) and may be highly reconfigurable.

Certain implementations of the QC system described herein may allow more qubits and/or qubit gates to be utilized for operations than would be provided using one-dimensional (1D) or two-dimensional (2D) layouts. advantageously provides a three-dimensional (3D) layout of qubits and/or qubit gates (e.g., "A scalable quantum computer with ions in an array of microtraps" by J.I. Cirac and P. Zoller, Nature, Vol. 404, p. 579 (2000)); see J. Chiaverini et al., “Quant. Inf. Comp.” (Vol. 5, 419 (2005)). For example, specific implementations described herein provide sufficient spacing to enable electrical connections and optical paths for addressing, manipulating, controlling, reading, and cooling the potential sideband of each qubit, Provides a 3D layout of qubit gates, each containing multiple atomic qubits (e.g., three or more simultaneously entangled neutral atoms, charged atoms, NV center qubits, etc.), providing approach angles. do.

When a particular arrangement or set of qubits can cause any qubit to become directly quantum mechanically entangled with any other qubit in the set, the qubits may be described as “globally connected.” For example, an equal number of qubits connected only in pairs, even if only a small number of qubits containing ions (e.g. charged atoms) connected entirely within a one-dimensional (1D) linear atomic trap. Greater potential processing power can be demonstrated by measurement (see, for example, N.M. Linke et al., “Experimental comparison of two quantum computing architectures” (PNAS, Vol. 114, No. 13 (2017))).

Quantum computing (QC) designs are based on parameters that mostly influence how quickly a quantum computer produces better results than its conventional computer counterpart, which is not based simply on how many qubits are connected together in the same way. This has been proven over the past 20 years. The demonstrated performance of these systems determines qubit fidelity (e.g., how precisely the system can perform gate operations), how the qubits are interconnected, and solutions to difficult problems. This has been explained by how much overhead it takes for the qubits to work together to perform a computation.

One-qubit gates simply involve flipping the qubit itself from “0” to “1” or to a specific quantum superposition of “0” and “1”. Two-qubit gates connect two qubits using superposition, a combination of quantum entanglement, such that what is done to one of the qubits affects the other. In such a two-qubit gate, the target qubit can start in either state “0” or state “1”, with any superposition of “0” and “1” (e.g. “0” and “1”). For example, the function of a quantum-controlled NOT (CNOT) gate is to flip the target qubit if the control qubit is in state “1”, otherwise it will not operate. One- or two-qubit gates can be implemented directly within many other quantum gate-based architectures. For more complex gate operations, implementations where two or more qubits can be immediately entangled will have a significant impact on the overall number of qubits and the overall number of steps performed to effectively influence the operation and the algorithms involved in them. (For example, C. Figgatt et al., “Parallel entangling operations on a universal ion-trap quantum computer” (Nature, Vol. 571 (2019)); Y. Lu et al., “Global entangling gates on arbitrary qubits” ( (see Nature, Vol. 571 (2019)). Measurable reductions in the number of qubits and steps used for transposition can, in some instances, result in a drastic reduction in overhead to implement successful results. One example could be a demonstration of a prototype that could provide solutions to otherwise intractable problems with fewer accessories and without extensive error correction, even at some times.

Certain implementations disclosed herein utilize multiple, fully connected, high fidelity qubits. The advantages of these specific implementations (e.g., how much more efficient certain quantum gate operations can be compared to using combinations of 1- and 2-qubit gates) are that they utilize four fully connected high-fidelity qubits. It can be illustrated by considering an exemplary quantum triply-controlled NOT (C ³ NOT) gate comprising: The C ³ NOT gate is also referred to as a super Toffoli gate. In this example C ³ NOT gate, all three control qubits are in a specified state (e.g., “1, 1, 1”) to flip the fourth target qubit from “1” to “0”. must be in When combined with one or more single-qubit gate operations, these multi-qubit quantum gates can be used to complete a universal set for quantum computing. Multi-controlled NOT gates are largely described in reference sources as involving an extended series of 1- and 2-qubit gate operations (e.g., "Quantum Computing and Quantum Information" by MA Nielsen and IL Chuang, 1st ed. .) (Cambridge Univ. Press, 2000). Extensions to these 1- and 2-qubit gate series greatly increase the physical implementations depending on the type of qubits used and how many qubits can be connected and entangled together. However, a C ³ NOT gate, which is implemented using four fully connected and simultaneously multiply entangled ions, has a small subset of the quantum gate operations utilized within a C ³ NOT gate which is implemented only as 1- and 2-qubit gates with the appropriate physical layout. It may be configured to have a. Methods for implementing simpler C ² NOT Toffoli gates were initially described using trapped ions (e.g., JI Cirac and P. Zoller "Quantum Computations with Cold Trapped Ions" (Phys. Rev. Lett. Vol. 74(20) (1995)), which was later proven (e.g., T. Monz et al., "Realization of the Quantum Toffoli gate with Trapped Ions" (Phys. Rev. Lett. Vol. 102, 040501) (2009)). The 3-qubit C ² NOT implementation produces a net fidelity improvement over the connection of the 1- and 2-qubit gates, even though they have much higher individual fidelities due to gate errors, contributing to A significant reduction in the number of gates and the time required to complete the overall gate operation has already been shown. These three-qubit gates could be implemented within a linear trap without strong requirements for geometric symmetry. In comparison, certain implementation examples described herein utilize the overall 3D symmetries of the designs described herein to provide C ⁿ NOT gates. In this way, the previously mentioned examples of improved efficiency can be greatly increased with the number of controls within each C ⁿ NOT gate through a concomitant reduction in the quantum gates required to implement them. Other multiple control gate operations, including phase rotation, can exhibit similar improvements in efficiency using physical configurations involving two or more simultaneously entangled qubits. These previous improvements can significantly reduce error correction.

If the highest quality qubits exhibit appreciable error rates, these may be small per qubit but can increase with the number of gates used to run the algorithm. When the sum error rate reaches a threshold where error correction is required to perform a much smaller set of quantum operations with a reasonable chance of producing reliable results, the efficiency of the architecture depends on the amount of overhead used for the error correction. It deteriorates proportionally immediately.

For a small-scale quantum computer with hundreds of relatively high-quality qubits intended to perform logic operations, the overhead of the error correction qubits plus the appendix can be expected to increase the number of qubits in the single order of magnitude, with a proportional reduction in efficiency. Or, it may roughly indicate an increase in the heat factor. For larger scale systems, the overhead can increase further by several orders of magnitude. However, in the specific implementations described herein, it benefits from the summation efficiencies of globally connected, high-quality qubits, and employs multi-qubit gate operations (e.g., which are naturally performed utilizing multi-dimensional geometries). ) Quantum computers can utilize significantly fewer steps and a significantly smaller overall number of qubits. As used herein, the expression “native” gate operations indicates that two or more qubits can participate simultaneously due to the geometric layout. Certain native multi-qubit gate implementation examples described herein can advantageously accommodate algorithms without utilizing extensive error correction overhead. Additionally, significant improvements in overall design efficiency can be achieved by multiple orders of magnitude due to reduced overhead for performing basic quantum computing algorithms or subroutines and demonstrating practical utility at increased speeds compared to conventional computing systems. Alternatively, it can be implemented using fewer quantum resources.

To date, most QC systems utilizing atomic qubits have employed one-dimensional (e.g., linear) traps that can be electrically or photonically interconnected (e.g., U.S. Pat. No. 9,858,531; Debnath et al., “Demonstration of a small programmable quantum computer with atomic qubits" (Nature, Vol. 536, p.63 (2016)). Most of these 1D traps allow a linear chain of qubits to be connected entirely within a common potential well or trapping zone. The degree of overall connectivity depends on how many qubits can be chained together before the coupling strength between qubits at or near opposing endpoints of the linear chain becomes too weak to utilize reliable multi-qubit gate operations. Because of the constraints, it may be desirable to create interconnections between multiple linear traps of limited lengths. Optical interconnections can be employed, for example, by switching the qubit state from an atomic qubit to a photon, and then transferring the photon to another linear trap where the quantum state is switched to another atom. One type of protocol used for this process is referred to as “quantum teleportation.” These interconnections introduce time delays and potential inefficiencies in transitions (e.g., from atomic qubit to photon and second atomic). Certain implementations disclosed herein advantageously provide optional configurations to more directly optimize qubit-to-qubit interactions while simultaneously enabling efficiencies using linear or 2D elements with optical interconnects. do. When scaling up to larger numbers of qubits, this particular implementation of optical interconnections between nodes along with their associated penalties (e.g., time delays; ion-to-photon conversion losses) Numbers can be advantageously reduced or avoided.

Rectangular two-dimensional (2D) grid configurations have previously been applied for some trapped ion approaches and superconducting qubit (SCQ) schemes. In these 2D grid approaches, interactions between the qubits largely occur within capture ion grid lanes (e.g., shuttling qubits into and out of lanes through intersections), Traditionally, it has been limited to one- and two-qubit operations that rely on significant redundancy to add fault tolerance to increase the likelihood of success in executing the algorithm up to usable levels. For example, some approaches use global addressing of a collection of qubits, which aligns intersections within a grid to redundantly influence the operation of a single 1- or 2-qubit among many qubits. It is cycled inward and outward and then averaged to reduce errors. In such an approach the overhead grows rapidly with the scale of the logical operations that must be performed by the quantum computer in terms of the number of redundant qubits to effect a single logical operation with sufficient fidelity. In contrast, in certain implementations described herein, entanglement between two or more qubits is simultaneously involved and arranged in two or more dimensions to directly or spontaneously affect multi-qubit gate operations. This is made possible by having qubits.

Other 2D lattice approaches that have been presented and/or employed involve initially applying Rydberg-blockade methods using neutral atoms (e.g., M. Saffman et al., “Quantum information with Rydberg atoms"(Rev. Mod. Phys. 82, 2313(2010)); K. Maller et al., "Rydberg-blockade controlled-not gate and entanglement in a two-dimensional array of neutral-atom qubits"(Phys. Rev .A 92, 022336 (2015)). Although the fidelity of early Rydberg-blocking methods was not competitive for forming quantum gates for computing, these Rydberg-blocking methods were advanced by improved methods of entangling Rydberg atoms (e.g. For example, D. Petrosyan et al., “High-fidelity Rydberg quantum gate via a two-atom dark state” (Phys. Rev. A 96, 042306 (2017)); M. Khazali and K. Molmer, “Fast Multiqubit Gates by Adiabatic Evolution in Interacting Excited-State Manifolds of Rydberg Atoms and Superconducting Circuits" (Phys. Rev. X 10, 021054 (2020)).

To distinguish the specific implementation described here from other approaches whose descriptive representations and visual layouts may appear similar, the overall layout of 2D periodic crystal structures, such as regular geometric lattice traps, has not yet been multiplied. Note that this was done in a useful way for the study of the physics of body interactions that do not implement gate operations between qubits. For example, triangular ion traps (e.g., Penning traps) collect ions to form an extended 2D crystal or triangular lattice that can be used for certain types of quantum simulators. They can be formed on the surface of periodic electrical potential wells that can be located internally. These traps can be used to form energy topologies that mimic those of the quantum system being modeled. Similarly, Kitaev models of tetrahedral hexagons (e.g., A. Kitaev, “Anyons in an exactly solved model and beyond” (Ann. Phys. Vol. 321, 2 (2006)); R. See Schmied et al., “Quantum simulation of the hexagonal Kitaev model with trapped ions” (New J. Phys. 13 115011 (2011)); Hybrid grids; kagome optical gratings (see, e.g., R. Samajdar, “Proc. Natl. Acad. Sci. U.S.A.” (118, e2015785118 (2021))); And while other regular grid structures may resemble them, they differ fundamentally in design complexity and purpose from the specific implementations described here. For example, although these crystal lattice structures are designed for simulations of quantum systems, these structures are generally not intended to perform gate operations. In particular, quantum simulators with 2D hexagonal lattices of ions (e.g., following the Kitaev model above) or neutral atoms (e.g., in an optical Kagome lattice), according to certain implementations described herein, are generally quantum Much simpler qubit control, addressing and readout schemes with fewer lasers than the complexity of these structures and a "full-up" quantum computer capable of performing gate operations (e.g., addressing lasers). instead of global addressing), simpler detection schemes, fewer electrode structures, etc.

Certain implementation examples disclosed herein advantageously enable solutions to rapidly increasing, hardware challenges that may appear challenging or impracticable when designing gate model QC structures that scale up from 2D trapped atomic lattices. You can do it. For example, specific implementations described herein may include optical elements (e.g., lasers; optical ports; fibers; detectors) are integrated into the QC structure and provide corrective field angles.

Specific implementation examples described herein enable simultaneous entanglement between an optimal number of neighboring qubits, enabling direct "writing", and advantageously provide scalable hardware configurations for executing complex quantum algorithms. In certain implementations, multidimensional quantum gate implementations, similar to conventional firmware, such as field programmable gate arrays (FPGAs), can be written directly in the form of multi-qubit gates and can be flexibly reprogrammed.

Certain implementations described herein may advantageously utilize multi-dimensional geometries to allow multiple controlled quantum gate operations to be performed naturally. In certain implementations, the quantum gate operations are executed on a quantum firmware platform in the smallest number of steps (e.g., coupling of 1- and 2-qubit gate operations to effect multiple control NOT operations). (without reclassification).

Certain implementations described herein advantageously enable a quantum firmware platform to be expanded as needed to integrate electrical and optical approaches for full control and readout of each qubit within a circuit model architecture to enable general-purpose quantum computing. Provides an engineered fabrication configuration that can be implemented.

Certain implementations described herein are advantageously configured such that an optimal number of qubits can be simultaneously entangled with their nearest neighbors, next-nearest neighbors, next-nearest neighbors, and beyond. Provides a multi-layer quantum computing structure. These specific implementation examples include electrical channels and optical approaches for addressing, controlling and reading out qubits in scalable quantum processors. For example, arrays of globally connected qubits advantageously allow for quantum processing within hardware rather than other designs where entangled gate operations are limited to specific pairs (e.g. due to the type of qubits employed or their layout). Provides more efficient, flexible options for executing algorithms. This improved efficiency and flexibility can be rapidly increased with the number of qubits within the array.

Certain implementations described herein advantageously can perform gate operations involving two or more qubits simultaneously, thereby providing significant improvements in efficiency compared to previous designs limited to one- and two-qubit gates. Provides improvements (e.g., by replacing dozens of these gates with a single 4-qubit gate). Certain implementations described herein advantageously utilize one-dimensional and two-dimensional qubit geometries (e.g., ions trapped linearly; ions trapped within NV centers in 2D grids, 2D diamond lattices). ; overcome connectivity limitations found within other 1D and 2D qubit lattices). For example, arranging qubits within multiple qubit arrays (e.g., multiple planar and/or linear qubit arrays) with direct connection (e.g., entanglement) between the qubit arrays. This can solve the problems of significant time delays and inefficiencies in the transition from ionic qubits to photonic qubits, and can then be scaled up to tens of atoms in a 1D chain or 2D grid.

Certain implementations described herein advantageously provide multidimensional, entangled geometries that resemble complex 3D crystal structures (e.g., pyrochlores). Additionally, the specific, unobstructed visibility designed into specific implementations advantageously provides optical approaches from multiple angles for individually and uniquely addressing each atomic qubit as well as the ensemble of said qubits. Certain implementations advantageously provide multiple optical approaches for readout of individual atomic qubit states by detectors.

Certain implementations described herein advantageously utilize neutral atomic qubits (e.g., uncharged Rydberg atoms whose outer electrons are raised to a highly excited state) to form multi-qubit lattice arrays. , which serves to demonstrate the applicability of these systems and methods to select qubit types and further illustrate their processing potential. Recent improvements in entangling Rydberg atoms make them more amenable to quantum computing (see, for example, M. Khazali and K. Molmer (2020); D. Petrosyan et al. (2017)). As a result of improved technologies, Rydberg atoms are also potentially well-suited as other exemplary qubits for the systems and methods described herein. Techniques for forming Rydberg qubit gratings have many of the same advantages of trapping ion grid arrays and some special advantages for trapping individual neutral atomic qubits, similar to the process of using electrical potentials to trap ionic qubits. In the process of intersecting coherent light beams (e.g. lasers) and in intersecting optical beams (e.g. in potential wells formed by red sidebands), the generating electromagnetic field interactions with the optical sidebands to form energy potential wells in the light fluxes (e.g., within the spaces (e.g., cells) between them, within the potential wells formed by the blue sidebands). Process may be included. For example, although Rydberg qubits have yet to be demonstrated to have the highest qubit gate fidelities and the longest lifetimes associated with trapped ions, the US patent uses Rydberg atoms as prime examples, ionic qubits. Composed of hexagonal lattice layers to create crystalline geometries (e.g. pyrochlore structures) equivalent to and/or connected to the cases described in Application Publication No. 2021/0142204(A1) It can be. The photonic lattice structures utilized to capture the Rydberg atoms can enable very close qubit spacing and additional array layers, depending on specific implementations described herein.

Specific implementations described herein utilize current square-based photonic gratings for Rydberg atoms to increase the number of grating layers; The hexagonal multilayer surface-trapping geometry described herein for ions and has the potential to increase the number of qubits that can be simultaneously entangled (e.g., with acceptable gate fidelities) beyond the limits of current implementation possibilities. Multilayer grids in geometries potentially equivalent to the cases described in US Patent Publication No. 2021/0142204(A1) (e.g., using primarily charged atomic qubit examples) for implementable qubit densities within The structures utilize Rydberg atoms within qubit arrays to their advantage. Data from recent experiments with trapping neutral Rydberg atoms in small-scale linear and/or square arrays show that 20 orders of magnitude qubits can be used in 2D squares with multi-qubit gate fidelity sufficient for scalable fault tolerance quantum computing. It represents what can be simultaneously entangled within a grid (see, for example, M. Khazali and K. Molmer (2020)).

Integrating multi-axis arrays of coherent photon (e.g., laser) beams into optical trap gratings to optimize the number and fidelity of entangled operations between qubits across a maximum number of cells in multiple directions, the 3D By adjusting the grid cell shapes and spacing, the specific implementations described here are equivalent to the cases of charged atomic qubits (e.g., ions), and in some cases exceed their complexity and processing power. Shiki advantageously provides multidimensional, intertwined geometric structures. For example, certain implementations described herein include Rydberg atoms in photonic multi-qubit grating arrays that advantageously enable minimized inter-qubit spacing (e.g., less than 10 microns in a photon trap grating). Take advantage of them. Specific implementations described herein enable the addition of lattice layers (e.g., up to 3, 4, 5 or more layers) while excitation on ions allows for the overall connection of 12 or more simultaneously entangled qubits. It includes hexagonal multilayer grid arrays equivalent to the cases described in . These example implementations may yield the ability to entangle more qubits simultaneously. As processing power increases exponentially with the number of qubits of substantially equal fidelity that can be entangled simultaneously, we can refer to 12 entangled atomic qubits to 42 qubits for a difference of 30 qubits. Increasing these numbers translates into an increase in computing power of 2 ³⁰ , or a benefit of over 1 billion folds.

Illustrative Implementations

Certain implementations described herein utilize multidimensional configurations of qubits (e.g., cells; nodes) that can resemble 3D crystal structures (e.g., pyrochlores). Certain implementations utilize many qubits per gate and may advantageously reduce (e.g., minimize) circuit depth, error correction, and interference mitigation. Certain implementations utilize compatible configuration cells that can advantageously implement quantum FPGA (QFPGA) and quantum ASIC (QASIC) chips.

Although the physical configurations of certain implementations are described herein as utilizing high fidelity captured atomic qubits (e.g., low error rates), any type of qubit that can be multidimensionally entangled simultaneously with multiple other qubits Qubits (e.g., naturally occurring; artificially formed) may be utilized according to certain implementations described herein. Examples of qubits that are compatible with the specific implementations described herein include, but are not limited to: subatomic particles; neutral atoms; ions; neutral molecules; charged molecules; Bose-Einstein condensates (BECs); electrons; electron holes; excitons; magnetic qubits; nitrogen vacancy (NV) centers (eg, inside diamonds); phonons; photons; quantum dots; Rydberg atoms; spin in silicon; And it includes possible superconducting qubits. In certain implementations, the qubits are suitable to directly (e.g., spontaneously) affect gate operations between two or more qubits in a specified configuration. For example, the physical architecture of certain implementations may advantageously provide complex gate operations such as multi-control NOT or phase rotation directly without resorting to serial connections of 1- and 2-qubit gates. You can.

Captured atomic qubits utilized in specific implementations described herein illustrate the nature of quantum interactions that are optimized. The advantages of an adequate number of captured atoms include, but are not limited to, (i) the fact that they are identical within a given species and thus extensive corrections or adjustments can be advantageously avoided, (ii) their potential (iii) the ability to form qubits with excellent stability and coherence times relative to gate cycle times, and (iii) continuous and proven high fidelity gate operations when compared to competing qubit technologies. In certain implementations described herein, simultaneous multi-qubit gate operations may be enabled by atoms arranged in 3D geometric layouts of multiple identical globally connected qubits. In certain implementations, 3D geometric layouts of globally connected qubits may advantageously integrate more than one qubit type (e.g., as a single species of atom and target for the multiple control qubits). adopt secondary atomic species; employ different atomic species for neighboring cells).

Specific embodiments described herein include, but are not limited to: naturally occurring atoms; neutral atoms; charged atoms; ions; molecules; artificially formed atoms; Rydberg atoms; Nitrogen vacancy (NV) centers in diamond; Bose-Einstein condensates (BECs); electrons; photons; quantum particles; quantum dots; phonons; photons; It includes multi-layer qubit arrays utilizing a variety of qubit technologies, including quantum states that behave as quantum particles. Although the drawings herein illustrate various example multilayer qubit arrays containing uncharged atoms (e.g., neutral atoms; Rydberg states; neutral Rydberg atoms), these example multilayer qubit arrays It will also be appreciated that they are compatible with other qubit technologies.

1 schematically illustrates a perspective view of an example quantum computing (QC) system 100 including logical qubits 110 within substantially planar regions 120 in accordance with certain implementations described herein. The system 100 includes a first plurality of logical qubits 110a within a first substantially planar area 120a, where at least some of the first plurality of logical qubits 110a are adjacent to each other. It is designed to interact. The system 100 further includes a second plurality of logical qubits 110b within a second substantially planar region 120b substantially parallel to the first substantially planar region 120a. At least some of the second plurality of logical qubits 110b are configured to interact with each other and with at least some of the first plurality of logical qubits 110a. Logic qubits 110 of FIG. 1 form multi-qubit gates across multiple 2D planar optical trap layers according to specific implementation examples described herein.

In certain implementations, as schematically illustrated in FIG. 1 , the example system 100 includes a third substantially planar region 120c within a third substantially planar region 120c that is substantially parallel to the second substantially planar region 120b. It further includes a plurality of logical qubits 110c. At least some of the third plurality of logical qubits 110c are configured to interact with each other and with at least some of the second plurality of logical qubits 110b. Another example system 100 that is compatible with certain implementations described herein includes at least one additional substantially parallel to the first, second and third substantially planar areas 120a, b, c. The substantially planar area 120 may include at least one additional plurality of logical qubits 110, wherein the at least one additional plurality of logical qubits 110 interact with each other, and the first, configured to interact with at least some of the second and/or third plurality of logical qubits 110a, b, and c. In certain such implementations, the system 100 includes a plurality of four, five, six, or more logical qubits arranged within four, five, six, or more substantially planar regions 120 that are substantially parallel to each other. 110, wherein the logical qubits 110 of the various planar regions 120 are configured to interact with each other (e.g., intra-plane interactions and inter-plane interactions). .

In certain implementations, the plurality of logical qubits 110 (e.g., the first plurality of logical qubits 110a, the second plurality of logical qubits 110b and/or The third plurality of logical qubits 110c) are naturally occurring atoms; neutral atoms; charged atoms; ions; molecules; artificially formed atoms; Rydberg atoms; Nitrogen vacancy (NV) centers in diamond; Bose-Einstein condensates (BECs); electrons; photons; quantum particles; quantum dots; phonons; transmons; It contains at least one physical qubit selected from the group consisting of quantum states that behave as quantum particles. In certain implementations, a logical qubit among the plurality of logical qubits 110 (e.g., the first, second and/or third plurality of logical qubits 110a, b, c). Fields 110 may be individually addressable.

In certain implementations, at least some of the plurality of logical qubits 110 (e.g., at least some of the first plurality of logical qubits 110a, the second plurality of logical qubits At least some of (110b) and/or at least some of the third plurality of logical qubits (110c) are configured to undergo multi-qubit gate operations in which two or more logical qubits (110) participate simultaneously. configured to interact directly with each other to form at least one three-dimensional (3D) gate cell array (e.g., comprising a plurality of multi-qubit 3D gate cells 130). For example, each logical qubit 110 of the 3D gate cell 130 may be configured to be quantum mechanically entangled with at least one other logical qubit 110 of the 3D gate cell 130.

In certain implementations, each first logical qubit 110a within the first planar region 120a may have a portion (e.g., nearest neighbor and next nearest neighbor) within the first planar region 120a. It may be configured to interact directly with the first logical qubits 110a. Similarly, each second logical qubit 110b within the second planar region 120b has another second portion (e.g., nearest neighbor and next-nearest neighbor) within the second planar region 120b. It may be configured to interact directly with logical qubits 110b, and each third logical qubit 110c within the third planar region 120c is a portion (e.g., a portion) within the third planar region 120c. For example, the nearest neighbor and the next nearest neighbor) may be configured to interact directly with other third logical qubits 110c. Additionally, each first logical qubit 110a within the first planar region 120a has a second logic qubit (e.g., nearest neighbor and next-nearest neighbor) within the second planar region 120b. Can be configured to interact directly with qubits 110b, wherein each second logical qubit 110b within the second planar region 120b is a portion (e.g., a portion) within the third planar region 120c. may be configured to interact directly with third logical qubits 110c (e.g., nearest neighbor and next nearest neighbor), each third logical qubit 110c within the third planar region 120c. may be configured to interact directly with some (eg, nearest neighbor and next nearest neighbor) second logical qubits 110b within the second planar region 120b. Although not shown in FIG. 1 , in certain implementations, at least some of the logical qubits 110 may be within the same planar region 120 and/or even more distant logical qubits within an adjacent planar region 120 110 (e.g., the next-next-closest logical qubits 110; the next-next-next-next-closest logical qubits 110).

2A is a perspective view of an example system 100 including 36 logical qubits 110 within a set of substantially parallel substantially planar regions 120a, b, and c in accordance with certain implementations described herein. is schematically illustrated. 2B illustrates another example system 100 including 60 logical qubits 110 within three substantially planar regions 120a, b, and c that are substantially parallel to each other in accordance with certain implementations described herein. A perspective view is schematically illustrated. The example systems 100 of FIGS. 2A and 2B each include multiple qubit gates (e.g., logical qubits 110 within substantially planar regions 120 where the logical qubits 110 are adjacent). ) A 3D lattice cue comprising 2D planar optical lattice layers forming a 3D hexagonal regular or “pyrochlore” lattice qubit array configuration that is latched or trapped within multiple planar layers with orthogonal connections between them. Contains a bit array.

In certain implementations, the logical qubits 110 shown in FIG. 2A or FIG. 2B are all logical qubits 110 of the example system 100, but in other specific implementations, the logical qubits 110 shown in FIG. 2A or FIG. 2B The logical qubits shown are only a subset of the logical qubits 110 of the example system 100 above. The logical qubits 110 form at least one multi-qubit 3D gate cell 130. For example, each pair of adjacent 3D gate cells 130 has two first logical qubits 110a in the first planar region 120a and two second logical qubits 110a in the second planar region 120b. It shares logical qubits 110b, and two third logical qubits 110c in the third planar area 120c.

Each of the planar regions 120a, b, c in FIG. 2A includes 12 logical qubits 110 arranged in a substantially hexagonal 2D pattern, and each of the planar regions 120a in FIG. 2B , b, c) comprises 20 logical qubits 110 arranged in a substantially hexagonal 2D pattern. The logical qubits 110 of FIGS. 2A and 2B are intraplanar between each logical qubit 110 and its nearest neighbor logical qubits 110 within each planar region 120a, b, and c. ) has a nearest neighbor (nn) distance d ₁ , and in FIGS. 2A and 2B , the plane between each logical qubit 110 and its nearest neighbor logical qubits 110 in different planar regions 120 My nearest neighbor (nn) distance is equal to the interplanar distance d ₂ . In certain implementations, the in-plane distance d ₁ of each of the planar regions 120a, b, c is substantially equal to each other, but in other specific implementations, the planar regions 120a, b, c At least two of the nn distances d ₁ within the plane are different from each other. In certain implementations, the interplanar distance d ₂ between planar regions 120a, b and between planar regions 120b, c is substantially equal to each other, but in other specific implementations, planar regions 120a, The inter-planar distance d ₂ between b) and between the planar areas 120b, c are different.

In certain embodiments, the nn distance d ₁ within the plane and the distance d ₂ between the planes are substantially equal to each other (e.g., less than 15 microns; within the range of 3 microns to 15 microns; 8 microns). in the range of 1 micron to 11 microns), and in other specific embodiments, the nn distance within the plane d ₁ and the distance d ₂ between the planes are different (e.g., within the range of 1 micron to 3 microns), and d ₁ > d ₂ or d ₁ < d ₂ . For example, the 2D hexagonal patterns of qubits 110 in planar regions 120 of the systems 100 of FIGS. 2A and 2B have a distance d ₁ within the plane equal to the distance d ₂ between the planes. can have, the next nearest neighbor (nnnn) distance between the planes is equal to d ₁ √2, the nnn distance within the plane is equal to d ₁ √3, and the next nearest neighbor (nnnn) distance within the plane is is equal to 2d ₁ , the nnnn distance between the planes is equal to 2d ₁ , the next nearest neighbor (nnnnn) distance between the planes is equal to d ₁ √5, and the nnnnn distance within the plane is equal to d ₁ √7. do.

Different configurations of the 2D hexagonal patterns of the qubits 110 within the planar regions 120 may have different lateral offsets between the planar regions 120 (e.g., one Offsets parallel to the planar regions 120 such that the qubits 110 within the planar region 120 are not directly on top of the qubits 110 of the adjacent planar region 120; e.g. For example, see Figures 5A-5C and Figures 6A-6F). As described herein, these configurations can have different values of the intra-plane nn distance d ₁ , the inter-plane distance d ₂ , and various intra- and inter-plane nnn, nnnn and nnnnn distances.

In certain implementations, as shown in Figure 2A, 21 of the logical qubits 110 are connected to a first multi-qubit 3D gate cell 130a (e.g., a C ²⁰ NOT gate cell or a C ²⁰ ϕ gate). cell), and 21 of the logical qubits 110 form a second multi-qubit 3D gate cell 130b (eg, a C ²⁰ NOT gate cell or a C ²⁰ ϕ gate cell). For example, logical qubit 110 (shown in black in FIG. 2A) in the planar region 120b can be the target qubit of the first gate cell 130a, and its 20 control qubits. (shown in dark gray in FIG. 2A), i.e., the nearest-neighbor logical qubits 110 within the six planes, and the nearest-neighbor logical qubits 110 between the two planes (e.g., (one in each of the planar regions 120a, c) and the next nearest neighbor logical qubits 110 between the twelve planes (e.g., six in each of the planar regions 120a, c) and At the same time, they can be quantum mechanically entangled. Similarly, another logical qubit 110 within the planar region 120b (shown in white in FIG. 2A) may be the target qubit of the second gate cell 130b, and the control queue of the 20 Bits 110 (e.g., 14 shown in light gray and 6 shown in dark gray in FIG. 2A since these are also control qubits of the first gate cell 130a) can be simultaneously quantum mechanically entangled. there is. In certain implementations, as shown in FIG. 2B, 21 of the logical qubits 110 may form a third multi-qubit 3D gate cell 130c, and 21 of the logical qubits 110 ) may form the fourth multi-qubit 3D gate cell 130d.

Each C ²⁰ NOT/C ²⁰ ϕ gate cell 130 in FIGS. 2A and 2B may be referred to as a “Pyrochlore cell” due to the similarity of its arrangement to that of pyrochlore crystal structures. As described herein, in certain implementations, more logical qubits 110 are connected to larger multi-qubit gate cells 130 (e.g., C ³⁴ NOT gate cells; C ³⁴ ϕ gate cells; C ⁹⁴ NOT gate cells; C ⁹⁴ ϕ gate cells, etc.) can be simultaneously quantum mechanically entangled with each other. Each of these larger gate cells 130 may be referred to as a “super pyrochlore cell.”

Although some of the entanglements between the various logic qubits 110 in FIGS. 2A and 2B are shown as dashed and solid lines of various weights, the gate cell 130 (e.g., the first gate cell 130a) All logical qubits 110 of can interact directly with each other (e.g., simultaneously quantum mechanically entangled; globally entangled; fully entangled) and with other gate cells 130 (e.g. For example, all logical qubits 110 of the second gate cell 130b may interact directly with each other (e.g., may be quantum mechanically entangled simultaneously). In certain implementations, each logical qubit 110 is divided into its nearest neighbor (nn) logical qubits 110 within a plane, its nearest neighbor (nn) logical qubits 110 between those planes, and the next logical qubits 110 between those planes. It is configured to interact directly with the nearest neighbor (nnn) logical qubits 110 of . In other specific implementations, each logical qubit 110 is divided into the next-nearest-neighbor (nnnn) logical qubits 110 within its plane, the next-nearest-neighbor (nnnn) logical qubits 110 between the planes ( 110), directly interacting with the next-nearest-neighbor (nnnn) logical qubits 110 within the plane and/or with the next-next-nearest-neighbor (nnnnn) logical qubits 110 between the planes. It is further configured to do so. In other specific implementations, each logical qubit 110 is further configured to interact directly with the next-next-next-nearest-neighbor qubits 110 within that plane. Figure 2A shows some example logical qubits 110 with their relationship to the single logical qubit 110 shown in black. By having the logic qubits 110 directly interacting with additional logic qubits 110, the number of logic qubits 110 within the gate cell 130 can be increased, thereby Accordingly, the computing power of the gate cell 130 can be increased.

In certain implementations, each multi-qubit gate cell 130 may be configured as a “native” C ²⁰ NOT gate (e.g., a 20-controlled NOT gate) and/or as a “native” C ²⁰ ϕ gate (e.g., It is formed of 21 entangled qubits 110 (e.g., as shown in FIGS. 2A and 2B) that can be operated as a 20-controlled phase gate. These native C ²⁰ NOT/C ²⁰ ϕ gates can be implemented with significantly fewer gate operations than could be used by them alone. In certain implementations, the native C provided by the example 21-qubit gate cell 130 does not aggregate the errors of many successful operations to implement the result. The net fidelity of ^{a 20} NOT/C ²⁰ ϕ gate is significantly greater than a C ²⁰ NOT/C ²⁰ ϕ gate containing many 2-qubit gates, which can have much higher individual gate fidelities. In these specific implementations, the C ²⁰ NOT/C ²⁰ ϕ gate provided by the example 21-qubit gate cell 130 is a stage of a C ²⁰ NOT/C ²⁰ ϕ gate comprising many 2-qubit gates. The C ²⁰ provided by the exemplary 21-qubit gate cell 130, as can be seen in a comparison of the probabilities of successful gate operation using estimates of both structure and fidelity, using a very small portion of the C 20 NOT/C ²⁰ ϕ gates are faster and less error-prone (i.e., they utilize significantly less error correction in startup).

In certain implementations, the number of logical qubits 110 per gate cell 130 increases the number of substantially planar areas 120 and/or allows the logical qubits 110 to interact with each other. It can be increased by extending the distance that can be reached. For example, Figure 3A shows a plurality of logical qubits 110 arranged within a set of substantially planar regions 120 that are substantially parallel to each other in accordance with certain implementations described herein (e.g., Figures 2A and schematically illustrates a perspective view of a system (compatible with the example system 100 of FIG. 2B). The perspective view of FIG. 3A follows an orientation in which all logical qubits 110 are visible (e.g., where the logical qubits 110 are not obscured by other logical qubits 110). 3A includes lines between some of the logical qubits 110, which lines represent some of the direct intersections between the logical qubits 110 of the gated cell 130. Each logical qubit 110 is divided into the nearest neighbor logical qubits 110 within that plane, the nearest neighbor logical qubits 110 between those planes, and the next nearest neighbor logical qubits 110 between those planes. ), and the gate cell 130 of FIG. 3A is a C ²⁰ NOT gate cell or a C ²⁰ ϕ gate cell (e.g., an exemplary target qubit shown in black and a C 20 ϕ gate cell shown in dark gray). Equipped with the control qubits).

As other examples, each of FIGS. 3B and 3C shows a perspective view of a plurality of logical qubits 110 arranged within five substantially planar regions 120 that are substantially parallel to each other in accordance with certain implementations described herein. Illustrate schematically. The perspective views of FIGS. 3B and 3C follow an orientation in which all logical qubits 110 are visible (e.g., where the logical qubits 110 are not obscured by other logical qubits 110). , comprising lines between some of the logical qubits 110, which lines represent some of the direct interactions between the logical qubits 110 of the gate cell 130. 3B, each logical qubit 110 has its nearest neighbor logical qubits 110 within its plane, its nearest neighbor logical qubits 110 between its planes, and its next nearest neighbor logical queue between its planes. Configured to interact directly with bits 110, gate cell 130 in FIG. 3B is a C ³⁴ NOT gate cell or a C ³⁴ ϕ gate cell (e.g., an example target qubit shown in black and dark (equipped with the control qubits shown in grey). In Figure 3C, each logical qubit 110 has its nearest neighbor logical qubits 110 within its plane, its nearest neighbor logical qubits 110 between its planes, and its next nearest neighbor within its plane. It is configured to interact directly with the qubits 110 and the next-nearest neighboring logical qubits 110 within that plane. Gate cell 130 in FIG. 3C is a C ⁹⁴ NOT gate cell or a C ⁹⁴ ϕ gate cell (e.g., with an example target qubit shown in black and its control qubits shown in dark gray). The exemplary arrangements of FIGS. 3A-3C include “super pyrochlore” cells (e.g., a 21-qubit C ²⁰ NOT/C ²⁰ cell in a three-layer regular hexagonal atomic lattice) according to certain implementations described herein. ϕ gate 130; 35-qubits in a 5-layer regular hexagonal atomic lattice C ³⁴ NOT/C ³⁴ ϕ gate 130; 95-qubits in a 5-layer regular hexagonal atomic lattice C ⁹⁴ NOT/C ⁹⁴ Advantageously increasing the possible simultaneous connections (e.g., entanglement) by using neutral (e.g., Rydberg) atomic traps formed by N-layer optical lattices that are hexagonal cells to form ϕ gates (130). Illustrate the extent to which

4A-4B, 5A-5C, and 6A-6D illustrate different relative displacements between logical qubits 110 in multiple substantially planar regions 120 according to specific implementation examples described herein. Schematically illustrates portions of an example system 110 comprising: 4A and 4B are examples having a set of planar regions 120a, b, and c, each containing a corresponding plurality of logical qubits 110a, b, and c, according to specific implementation examples described herein. A top view (eg, along the z-axis) and a perspective view, respectively, of a portion of the system 100 are schematically illustrated. The logical qubits 110 in each of the planar regions 120 are arranged in a substantially hexagonal 2D pattern, and the planar regions 120 are substantially parallel to each other. In the hexagonal regular grid array of FIGS. 4A and 4B, the 3D configurations include orthogonal connections between qubits in adjacent planar regions 120. 4A and 4B, the logical qubits 110 (of a substantially planar region 120) are connected to the planar region 120 from the logical qubits 110 of a neighboring substantially planar region 120. It is not substantially disposed along a substantially parallel direction. For example, as shown in FIG. 4A, the logical qubits 110a of the uppermost planar area 120a are formed by the logical qubits 110b and c by the logical qubits 110a. The corresponding logical qubits 110b, c within the other two planar regions 120b, c are obscured so that the logical qubits 110a are visible from above (e.g., along the z-axis). is aligned with This exemplary system 100 of FIGS. 4A and 4B is similar to that of FIG. 2A 2B (e.g., the exemplary 21-qubit C ²⁰ NOT/C ²⁰ ϕ gates 130 are substantially the same as each other in the same plane). It has a distance d ₁ and a distance d ₂ between the planes, and each logical qubit 110 has nearest neighbor logical qubits 110 within the plane and nearest neighbor logical qubits 110 between the planes. and configured to interact directly with the next-nearest neighboring logical qubits 110 between the planes.

5A and 5B show another diagram having a set of planar regions 120a, b, and c, each containing a corresponding plurality of logical qubits 110a, b, and c, according to specific implementation examples described herein. A top view (e.g., along the z-axis) and a perspective view, respectively, of a portion of the example system 110 are schematically illustrated. The logical qubits 110 in each of the planar regions 120 are arranged in a substantially hexagonal 2D pattern, and the planar regions 120 are substantially parallel to each other. In the optional hexagonal grating array of FIGS. 5A-5C, the 3D configurations include non-orthogonal connections between qubits in adjacent planar regions 120, and this optional configuration provides for the optical grating. Expands the engineering trade-off of optimal approach angle choices. 5A and 5B, qubits 110 of substantially planar regions 120 are substantially parallel to the planar regions 120 from logical qubits 110 of adjacent substantially planar regions 120. They are positioned (e.g. offset) along one direction.

For example, as shown in FIGS. 5A and 5B, the logical qubits _110a move in a direction along the y _- axis (e.g., the x The logical qubits 110c are displaced relative to the logical qubits 110b (orthogonal to the -axis and the z-axis; shown by the dashed double arrows in Figure 5a), but the logical qubits 110c are The logical qubits 110 (110a, b) of the planar regions 120a, b are visible from above (e.g., along the z-axis) while being obscured by 110a). It is aligned with field 110c. Figure 5c schematically illustrates a perspective view similar to the case of Figure 5b, where nn distance d ₁ within the plane and a nearest neighbor cue between the planes such that the distance d ₂ between the planes is substantially equal to d ₁ √3/2. The distances between the bits are substantially equal to each other, and each logical qubit 110 is one of its nearest-neighbor logical qubits 110 within its plane, and a nearest-neighbor logical queue between its planes, according to specific implementation examples described herein. Bits 110, next-nearest-neighbor logical qubits 110 within the plane, next-nearest-neighbor logical qubits 110 between the planes, and next-nearest-neighbor logical qubits between the planes. It is configured to interact directly with bits 110. As shown in Figure 5C, the exemplary 23-qubit C ²² NOT/C ²² ϕ gates 130 have a target qubit (black) and 22 control qubits (dark gray).

FIGS. 6A and 6B are further illustrated with a set of planar regions 120a, b, and c, each containing a corresponding plurality of logical qubits 110a, b, and c, according to specific implementation examples described herein. Schematically illustrate a top view (e.g., along the z-axis) and a perspective view of a portion of another example system 110. The logical qubits 110 in each of the planar regions 120 are arranged in a substantially hexagonal 2D pattern, and the planar regions 120 are substantially parallel to each other. 6A and 6B, logical qubits 110 of a substantially planar region 120 are substantially parallel to the planar regions 120 from logical qubits 110 of an adjacent substantially planar region 120. Displaced along one direction. For example, as shown in FIGS. 6A and 6B, the logical qubits 110a are oriented along the x-axis (e.g., the y-axis and z) with a displacement magnitude of δ ₂ = d ₁ 2 - orthogonal to the axis (shown by dashed double arrows in Figure 6a) with respect to the logical qubits 110b, but the logical qubits 110c are shifted by the logical qubits 110a. By blurring, the logical qubits 110a, b of the planar regions 120a, b are aligned with the logical qubits 110c such that they are visible from above (e.g., along the z-axis). do. Figure 6c schematically illustrates a perspective view similar to the case of Figure 6b, where nn distance d ₁ within the plane and a nearest neighbor cue between the planes such that the distance d ₂ between the planes is substantially equal to d ₁ √3/2. The distances between the bits are substantially equal to each other, and each logical qubit 110 is one of its nearest-neighbor logical qubits 110 within its plane, and a nearest-neighbor logical queue between its planes, according to specific implementation examples described herein. Bits 110, next-nearest-neighbor logical qubits 110 within the plane, next-nearest-neighbor logical qubits 110 between the planes, and next-nearest-neighbor logical qubits 110 between the planes. interacts directly with fields 110. As shown in Figure 6C, the exemplary 25-qubit C ²⁴ NOT/C ²⁴ ϕ gate 130 has a target qubit (black) and 24 control qubits (dark gray).

6D and 6E each have a set of planar regions 120a, b, and c, each containing a corresponding plurality of logical qubits 110a, b, and c, according to specific implementation examples described herein. Schematically illustrates a top view (e.g., along the z-axis) and a perspective view of a portion of another example system 110. The logical qubits 110 within each of the planar regions 120 are aligned in a substantially hexagonal 2D pattern, with the planar regions 120 being substantially parallel to each other. 6D and 6E, logical qubits 110 of the substantially planar region 120 are substantially planar regions 120 from logical qubits 110 of the adjacent substantially planar region 120. is moved along a parallel direction. For example, as shown in FIGS. 6D and 6E, the logical qubits 110a are moved relative to the logical qubits 110b with a displacement magnitude δ ₃ substantially equal to d ₁ , and the magnitude δ It has a first component along these axes with ₁ = d ₁ √3/2 and a second component along the x-axis with magnitude δ ₂ = d _1/2 . The logical qubits 110a are aligned with the logical qubits 110b, c such that the logical qubits 110b, c are obscured by the logical qubits 110a in FIG. 6D.

FIG. 6F schematically illustrates a perspective view similar to the case of FIG. 6E according to certain implementations described herein, where nn distance within the plane d ₁ and the distance between the nearest neighboring qubits between the planes are The distance (e.g., separation) between the planes is substantially equal to each other such that d ₂ = d ₁ √ 3/2, and each logical qubit 110 is connected to the nearest neighboring logical qubits 110 in that plane, the next-nearest neighbor logical qubits 110 between the planes, the next-nearest neighbor logical qubits within the plane, the next-nearest neighbor logical qubits 110 between the planes, and the next-next between the planes. It is configured to interact directly with the nearest neighboring logical qubits 110. As shown in FIG. 6F, the exemplary 21-qubit C ²⁰ NOT/C ²⁰ ϕ gate 130 has a target qubit (shown in black) and 20 control qubits. In these and all previous examples, all logical qubits 110a, b, c are visible, individually addressable, and there are individually detectable angles.

5A-5C and 6A-6F schematically show example displacements with example directions and magnitudes between logical qubits 110 of the planar regions 120. Other specific implementations may have displacements in different directions (e.g., having a magnitude along both the x- and y-axes) and/or of different magnitudes (e.g., 1/2 cell width; 1/3 cell width). Other specific implementations have different inter-plane distances d ₂ . For example, the separation between planar regions 120 may be reduced depending on the angle from vertical between the nearest logical qubits 110 across the neighboring planar regions 120 (e.g. , d ₁ /2; 2· d ₁ /3; 3· d ₁ /4; 0.85· d ₂ equal to d ₁ ). 5A-5C and 6A-6F schematically illustrate example systems 100 with 2D, substantially hexagonal patterns, although other 2D patterns are compatible with the specific implementations described herein. It can be.

In certain implementations, the first plurality of logical qubits 110a are individually addressable and arranged in a substantially planar first optical grating, and the second plurality of logical qubits 110b are: arranged in a substantially planar second optical grating that is individually addressable and substantially parallel to the first optical grating, wherein the third plurality of logical qubits (110c) are individually addressable and arranged in a second optical grating that is substantially parallel to the first optical grating. and is arranged in a substantially planar third optical grating region substantially parallel to . In certain implementations, the system 100 includes at least one additional plurality of logical qubits 110 within at least one additional substantially planar region 120 substantially parallel to the third substantially planar region 120c. wherein the at least one additional plurality of logical qubits 110 is configured to interact with each other and/or with at least a portion of the third plurality of logical qubits 110c, where The at least one additional plurality of logical qubits 110 are individually accessible. For example, the number of substantially parallel optical gratings of the plurality of qubits may further include a fourth optical grating, a fifth optical grating, a sixth optical grating, a seventh optical grating, etc. The plurality of confinement regions may further include at least one additional confinement region arranged in at least one additional optical grating substantially parallel to the third optical grating, wherein the at least one additional optical grating is in the at least one additional optical grating. Contains an additional plurality of logical qubits.

For example, Figures 7A-7E illustrate certain implementation examples described herein. An exemplary multi-qubit gate cell 130 formed between multiple 2D planar optical trap regions and having a plurality of addressing laser beams 210 (e.g., a target qubit in the center and a control cue elsewhere). Schematically illustrates various diagrams of a C ²⁰ NOT gate cell or C ²⁰ ϕ gate cell) with 21 qubits 110 in a pyrochlore configuration with bits. FIG. 7A shows atomic qubits in a multilayer lattice structure of the multi-qubit gate cell 130. The lines between the qubits 110 in Figure 7A represent only a portion of the entanglement between the qubits 110, and lines representing other entanglements between the qubits 110 are omitted for clarity. FIG. 7B shows such a multi-qubit gate cell 130 with only a portion of the addressing laser beams 210 (e.g., emitted from optical ports 212) configured to individually illuminate atoms, Arrays of trapping laser beams 220 that create optical potential wells containing atoms are omitted for clarity. As shown in FIGS. 7C and 7D, each of the addressing laser beams 210 illuminates a single atom of the multi-qubit gate cell 130. A limitation of 2D drawings is that one instance of them can show a single laser beam intersecting more than one atom. However, the laser beams 210 are arranged in alternating rows and are illustrated as transparent. As a result, atoms between or behind multiple laser beams 210 can in fact make one atom appear within multiple laser beams when each atom is crossed by at most one addressing laser beam, or by one laser beam. The unprocessed beams can be seen "through" in such a way that the light beam can be made to appear intersected by multiple atoms. Specific implementation examples described herein allow more qubits 110 to participate in a single native gate operation. It is configured to entangle a maximum number of qubits simultaneously. Because the potential processing power of each gate cell increases exponentially with the number of qubits 110 simultaneously participating in each gate operation, the processing power of the specific implementation examples described herein also increases overall. Dynamic reconfigurability of the placement of the gate structures and specific implementations is also greatly improved.

8A-8E schematically illustrate various views of trapping laser beams 220 according to specific implementations described herein. These example implementations of FIGS. 8A-8D illustrate the 3D optics of potential wells formed within or between intersecting trapping optical beams 220 (e.g., trapping laser beams emitted from optical ports 222). Utilizes neutral (e.g., uncharged) Rydberg atoms trapped within lattices (see, e.g., I. Bloch, “Nature Physics 1”, 23 (2005)). Specific implementation examples described herein , the atoms are co-aligned and trapped within regions of minimal potential energy (e.g., null) formed within the lattice spaces between intersecting optical beams (e.g., see FIGS. 8A and 8B). , in certain other embodiments, atoms may be trapped within intersecting optical beams (e.g., see Figures 8C and 8D). Such trapping within intersecting trapping optical beams 220 is described in S.E. Anderson et al., “Phys. Rev. Lett. 107" (263001 (2011)); and T.M. Graham et al., "Phys. Rev. Lett. 123" (230501 (2019)).

8A-8E employ grid spacings in the range of 8 microns to 11 microns (eg, less than 12 microns) between nearest neighbor qubits 110. |101S>; In instances where the Rydberg transitions of |109S>cesium (Cs) are utilized (e.g., cooled to 77K, 300K, or some other temperature), a typical grid cell size of 8 microns is based on reference data curves. Thus, it is within the range of optimal values for specific multi-controlled quantum gate operations. These specific implementation examples may provide both the design possibilities and design advantages of the specific implementation examples described herein.

In certain implementations, atomic qubits arranged in alternating columns have parallax offsets between adjacent planes (e.g., 1/2 cell offset spacing along x or y, 1/3 along x or y). cell offset spacing, 1/4 x 1/4 cell offset spacing along and may enable tilted hexagonal prism configurations visible from certain drawings. For example, the intersecting trapping laser beams 220 may be positioned relative to a reference plane (e.g., horizontal; x-y plane) such that 3D intersections of the intersecting trapping laser beams 220 may be close to orthogonal. An exemplary quantum computing system (e.g., a first array of trapping laser beams 220 arranged along the x-axis at +18.5 degrees toward the z-axis, y=0, toward the y-axis, z=0) The length , horizontal dimensions) can form complex angles with respect to a coordinate system that can be defined as The potential wells formed between the trapping laser beams 220 can be substantially symmetrical in plane (e.g., have cross-sections that are square or diamond shaped) when viewed at certain angles, which can be substantially Uniform potential wells (e.g., saddle-shaped wells; saddle points) can be created. For example, in FIGS. 8B and 8D, the first and second arrays of trapping laser beams 220 may appear rectangular or trapezoidal from certain perspectives. However, the intersections of the first and second arrays of trapping laser beams, shown horizontally in FIGS. 8B and 8D, appear approximately orthogonal when viewed obliquely from certain angles of approach from the lower left in FIGS. 8B and 8D. The trapping laser beams 220 that appear inclined to the upper right may also be inclined downward within the 3D structure. In certain embodiments, the atomic confinement structure may form regular hexagonal prisms across planes (e.g., as shown in FIGS. 1A, 1B, and 1D), and in other specific embodiments, , the atom-to-atom geometry can appear tilted or tilted to form oblique hexagonal prismatic configurations. In certain implementations, the optical beam intersections may appear non-orthogonal at various perspectives and angles, but the angled 3D lattice structure of certain implementations allows for optimal addressing and readout (e.g., detection) of qubits. They are designed to allow for maximum spatial separation between atoms when observed from these angles.

9A-9B schematically illustrate a perspective view of a three-layer 10 x 10 atomic trap grid created by alternating arrays of trapping laser beams 220 in accordance with certain implementations described herein. Figure 9C schematically illustrates a top view of the structure of Figures 9A-9B. Also shown are three intertwined arrays of addressing laser beams 210 in accordance with specific implementations described herein.

FIG. 10A shows a three-layer 10 A perspective view of a partially assembled QC system 100 comprising a 10-atom lattice is schematically shown. In addition, Figure 10a shows optical ports 214a, b, c through which the addressing laser beams 210a, b, c extend, and optical fiber ports emitting the trapping laser beams 220a, b. 222a, b), a magnetic field source 230 configured to generate a magnetic field as part of an optical trap configuration (electrodes 234 configured to generate an electric field as part of the optical trap configuration are shown in FIG. 10A) , and first and second photodetectors 240a, b (e.g., a CCD detector array) configured to receive and detect fluorescence from the qubits via corresponding photodetector ports 242a, b. This is shown. 10B-10D illustrate different sets of two intersecting arrays of the three sets of addressing laser beams 210a, b, c and trapping laser beams 220a, b of FIG. 10A according to certain implementations described herein. Shows different views from directions.

10A-10D schematically illustrate an exemplary QC system 100 with three sets of addressing laser beams 210a, b, c; however, in certain other implementations the QC system 100 may have four or more sets of addressing laser beams 210a, b, c. It may include many sets of addressing laser beams 210. For example, Figure 10E has four sets of addressing laser beams 210a, b, c, d and two alternating arrays of trapping laser beams 220a, b according to certain implementations described herein. schematically illustrates another partially assembled QC system 100 comprising a three-layer 10 x 10 atomic lattice. 10F-10H illustrate two intersecting sets of addressing laser beams 210a, b, c, d and trapping laser beams 220a, b of FIG. 10E according to other specific implementations described herein. Different views are shown from different orientations of the arrays.

As described herein, all directions lying within the x-y plane are defined at an altitude of 0 degrees (eg, horizontal), and the direction orthogonal (eg, perpendicular) to x and y is defined as z. Additionally, the direction along y is defined as an azimuth of 0 degrees (eg, rotation about z), and the direction of 0 degrees azimuth and 0 degrees altitude is expressed as (0°, 0°). For example, in certain implementations described herein, the laser arrays may be oriented to intersect in FIGS. 10A-10C (e.g., trapping laser beams 220a at (0°, 0°), Trapping laser beams 220b at (90°, +20°)), the rows of lasers 220a form a 2D grid in which the intersection points of the trapping laser beams 220a, 220b lie in a plane inclined at +20 from the x-y plane. It may be arranged at a cross-sectional inclination (e.g., elevation) of +20 degrees to form In these specific implementations, the trapping cells formed by the substantially orthogonally intersecting lasers may be substantially square in shape (addressing laser beams 210a at (293.5°, +53.5°) , addressing laser beams 210b at (246.5°, +53.5°) and addressing laser beams 210c at (71.5°, +58°)). In certain other implementations described herein, the intersections of the trapping laser beams allow multiple addressing laser angles to allow for individually addressing each qubit within each qubit in the 3D lattice, while maintaining a more planar cue. Bit grid arrays can be advantageously arranged at different angles to form trapping cells that are diamond-shaped or rhombus-shaped to enable addition. For example, in another implementation that is simple to explain, trapping laser beams 220a may be aligned at (30°, 0°) and trapping laser beams 220b may be aligned at (0°, 60°), (120°). Addressing lasers at (°, 60°), (240°, 60°) can be arranged at (90°, +20°). Certain combinations of these angles, as shown in Figure 10b, provide visual clarity; Two compact arrays of trapping laser beams 220 (e.g., clusters; Note that this is chosen for easy differentiation of banks. Other examples include complex lattice lasers forming substantially orthogonal intersections of grating lasers within a 3D structure, while similarly optimizing the possibilities for visibility for addressing and detecting individual qubits according to other specific implementations described herein. Optional combinations of angles can be utilized.

11A is a schematic illustration of the three-layer 10 x 10 3D atomic lattice of FIGS. 9A-9C and 10A-10D viewed through the first photodetector port 242a in accordance with certain implementations described herein. Example: From this perspective, each atom in the multi-dimensional multi-qubit lattice arrays can be processed by a single dedicated optical addressing beam such that the state of each atom can be individually detected and distinguished by the first photodetector 240a. ) can be viewed separately. Figure 11b schematically illustrates a side cross-sectional view of the structure of Figure 11a. 11A shows three layers of 10 x 10 3D atomic lattices, but other atomic lattices are also shown so that each atom in the lattice can be treated and viewed separately and individually from optimal approach angles above and below the lattice structure (e.g. may be configured to be detected by the first photo detector 242a. For example, computer aided design (CAD) and analysis can be used to identify other such configurations for different atomic lattices. These specific implementations allow more qubits to participate in the operation of a single native gate simultaneously among their nearest neighbors, next-nearest neighbors, next-nearest neighbors, etc. Enables the maximum number of qubits. 11A also shows electrode regions 234, a magnetic field (e.g., B-field) source (e.g., B-field) for reading and addressing and manipulating qubits that affect gate operations in accordance with certain implementations described herein. 230), the relative positions of the detector array 240 (e.g., CCD camera, etc.) and optical beam ports 242a, 214a, b, and c are schematically illustrated.

FIG. 12 shows a three-layer 10 Schematically illustrates a perspective view of an exemplary assembled QC system of FIG. 10A comprising a 10-atom lattice. 12 also shows a view through the first photodetector port 242a (e.g., as shown in FIG. 11A) and two intersecting arrays of trapping laser beams 210a, b, c. The drawings (e.g., as shown in FIGS. 8E and 9A) schematically illustrate.

13 is a set comparing the overall number of qubits that can be simultaneously entangled at specified gate fidelities for various multi-qubit lattice layers according to specified gate fidelity for various multi-qubit lattice layers according to specific implementation examples described herein. The tables are shown.

The present invention has been described with several non-limiting implementation examples. It is understood that the above-described implementation examples are not mutually exclusive, and that elements described in connection with one implementation example may be combined with other implementation examples, rearranged, or eliminated in any appropriate manner to implement the desired design objectives. It must be understood. No single feature or group of features is essential or required for each implementation.

For the purpose of summarizing the invention, certain aspects, advantages and novel features of the invention are described herein. However, it should be understood that not all of these advantages may be implemented in any particular implementation. Accordingly, the invention may be implemented or practiced in such a way that one or more advantages thereof are not necessarily achieved as other advantages may be taught or suggested herein.

As used herein, reference to “one implementation,” “some implementations,” or “an implementation” means that a particular element, feature, structure or characteristic described in connection with the implementation is included in at least one implementation. means included. The use of phrases such as “in one implementation” in various paragraphs of this specification do not necessarily all refer to the same implementation. Conditional expressions used here, such as “may,” “could,” “could,” “could,” “for example,” and similar expressions, among other expressions, Unless usage is specifically stated otherwise, or is specifically explained differently, it is generally intended that particular implementation examples be practiced including certain features, elements and/or steps, although other implementation examples may not be included. Additionally, expressions such as “one”, “one”, or “one” used in this specification and the appended patent claims mean “one or more” or “at least one,” unless otherwise stated in the text. It will have to be interpreted.

Expressions of degree, such as "approximately," "about," "substantially," and "substantially," are used herein to still perform the desired function or achieve the desired result. Indicates a nearby value, quantity, or characteristic. For example, the expressions “approximately,” “about,” “substantially,” and “substantially” mean within ±10%, within ±5%, within ±2%, within ±1%, or within ±0.1% of the stated amount. It can refer to the amount within. As another example, the expressions “generally parallel” and “substantially parallel” refer to a value, quantity, or characteristic that deviates from exact parallel by ±10 degrees, ±5 degrees, ±2 degrees, ±1 degree, or ±0.1 degrees. The terms "generally orthogonal" and "substantially orthogonal" refer to a value, quantity, or characteristic that deviates by ±10 degrees, ±5 degrees, ±2 degrees, ±1 degree, or ±0.1 degrees from exact vertical. do. Additionally, ranges disclosed herein encompass any and all overlapping, subranges, and combinations thereof. Expressions such as “up to,” “at least,” “greater than,” “less than,” “between,” and similar words also include the numerals they appear in. As used herein, the expressions “one,” “one,” and “one” include plural expressions unless clearly stated otherwise in the text. Additionally, as used in the description herein, the expression “within” includes “within” and “on” unless clearly stated otherwise in the text.

As used herein, expressions such as “comprise,” “including,” “comprise,” “comprising,” “have,” “having,” or any other variations thereof are non-limiting expressions. It is intended to be inclusive and not exclusive. For example, a process, method, item, or apparatus that includes listed elements is not necessarily limited to only those elements, but may also include other elements explicitly listed or unique to such process, method, item, or apparatus. It can be included. Additionally, unless specifically stated to the contrary in the text, the expression “or” means an inclusive “or” and a non-exclusive “or.” For example, a condition A or B is that A is true (or exists) and B is false (or does not exist), A is false (or does not exist) and B is true (or exists), or A and B are both true (or exist). As used herein, reference to “at least one” in a listing of items refers to any combination of those items, including single members. By way of example, “at least one of A, B, or C” is intended to encompass A, B, C, A and B, A and C, B and C, and A, B, and C. Conjunctive expressions such as "at least one of It must be understood as being Accordingly, this conjunctive expression is generally not intended to include requiring that at least one of X, at least one of Y, and at least one of Z are each present in particular implementations.

Accordingly, although only certain implementation examples are specifically described herein, it will be clearly understood that numerous changes may be made to the above-described implementation examples without departing from the spirit and scope of the invention. Additionally, abbreviations are used solely to improve the readability of the specification and claims. These abbreviations are not intended to reduce the generality of the terms used, and should be understood as not limiting the scope of the patent claims, even with respect to the implementation examples described herein.

Claims (24)

In a quantum computing (QC) system,
comprising a first plurality of logical qubits in a first substantially planar area, wherein at least some of the first plurality of logical qubits are configured to interact with each other;
comprising a second plurality of logical qubits in a second substantially planar region substantially parallel to the first substantially planar region, wherein at least some of the second plurality of logical qubits interact with each other; A system configured to interact with at least some of the first plurality of logical qubits. 2. The method of claim 1, wherein at least some of the first plurality of logical qubits and at least some of the second plurality of logical qubits undergo multi-qubit gate operations in which two or more logical qubits participate simultaneously. A system wherein the system is configured to interact directly with each other to form at least one three-dimensional (3D) gate cell array. 2. The method of claim 1, further comprising a third plurality of logical qubits in a third substantially planar region substantially parallel to the second substantially planar region, wherein at least one of the third plurality of logical qubits and some of which are configured to interact with each other and with at least some of the second plurality of logical qubits. 4. The system of claim 3, wherein the logical qubits of the first, second, and third plurality of logical qubits are individually addressable. 4. The method of claim 3, further comprising at least one additional plurality of logical qubits within at least one additional substantially planar region substantially parallel to the third substantially planar region, wherein the at least one additional plurality of logical qubits interact with each other and/or with at least some of the third plurality of logical qubits, wherein the at least one additional plurality of logical qubits is individually addressable. 2. The method of claim 1, wherein a first confinement region is arranged in a substantially planar first optical grating and a second confinement region is arranged in a substantially planar second optical grating substantially parallel to the first optical grating. further comprising a plurality of optical beams defining a plurality of confinement regions having regions, wherein the first plurality of logical qubits are within the first optical grating and the second plurality of logical qubits are within the first optical grating. 2 A system characterized by being within an optical grating. 2. The method of claim 1, wherein the plurality of confinement regions further comprises third confinement regions arranged in a substantially planar third optical grating substantially parallel to the second optical grating, wherein the third plurality of logical queues The system of claim 1 , wherein the bits are within the third optical grating. 8. The method of claim 7, wherein the plurality of confinement regions further comprises at least one additional confinement region arranged in at least one additional optical grating substantially parallel to the third optical grating, wherein the at least one additional optical grating is A system comprising at least one additional plurality of logical qubits. 8. The method of claim 7, wherein the logical qubits of the first, second, and third plurality of logical qubits are configured as a plurality of multi-qubit 3D gate cells, and one of the plurality of multi-qubit 3D gate cells A system wherein each logical qubit of a multi-qubit 3D gate cell is configured to be quantum mechanically entangled with at least one other logical qubit of the multi-qubit 3D gate cell. 8. The method of claim 7, wherein the confinement regions of each of the first optical grating, the second optical grating, and the third optical grating are two-dimensional substantially symmetrical square-shaped patterns, diamond-shaped patterns, or diamond-shaped patterns. A system characterized by being arranged in a pattern. 2. The system of claim 1, wherein at least some of the first plurality of logical qubits are fully entangled with at least some of the second plurality of logical qubits. 2. The method of claim 1, wherein at least some of the first plurality of logical qubits and/or at least some of the second plurality of logical qubits are one of the first plurality of logical qubits and the second plurality of logical qubits. A system characterized in that the system is globally entangled with the nearest neighbor logical qubits and the next nearest neighbor logical qubits of the plurality of logical qubits. 13. The method of claim 12, wherein at least some of the first plurality of logical qubits and/or at least some of the second plurality of logical qubits are one of the first plurality of logical qubits and the second plurality of logical qubits. A system characterized in that it is completely entangled with the next-next-nearest-neighbor logical qubits of a plurality of logical qubits. 2. The method of claim 1, wherein at least some of the first plurality of logical qubits and/or at least some of the second plurality of logical qubits comprise naturally occurring atoms; neutral atoms; charged atoms; ions; molecules; artificially formed atoms; Rydberg atoms; Nitrogen vacancy (NV) centers in diamond; Bose-Einstein condensates; electrons; photons; quantum particles; quantum dots; phonons; transmons; A system comprising at least one physical qubit selected from the group consisting of quantum states that behave as quantum particles. A quantum computing (QC) system comprising a plurality of confinement regions configured to contain logical qubits forming quantum gates within a multi-qubit lattice array comprising two or more dimensions, wherein the quantum gates are 1- and 2- A system characterized in that it is configured to perform quantum logic operations that naturally involve three or more logical qubits without relying on connections of qubit gates. 16. The system of claim 15, wherein at least some of the quantum logic operations utilize two or more control qubits that naturally act on one or more target qubits. 17. The method of claim 16, wherein the quantum logic operations include: single-controlled multiple NOT gates; Fanout gate; multi-control NOT gate; Toffoli gate; Super Toffoli Gate; A system selected from the group consisting of multi-controlled phase gates. 16. The system of claim 15, further comprising electrical and optical elements configured to perform multi-qubit logic operations. 16. The method of claim 15, wherein electrical traces, optical beam configurations, detectors, and stray light management are configured to enable low noise addressing and readout of individual qubits within the qubit lattice array. ) system characterized in that it further includes elements. 16. The system of claim 15, wherein the multi-qubit grating array comprises multiple substantially parallel planar qubit grating arrays. 21. The method of claim 20, wherein the multiple substantially parallel planar qubit grating arrays comprise at least a first planar qubit grating array and a second planar qubit grating array, and a qubit in the first planar qubit grating array. and the qubits in the second planar qubit lattice array are offset from the qubits in the second planar qubit lattice array along a direction substantially parallel to the first planar qubit lattice array. 22. The method of claim 21, wherein the qubits are aligned with qubits in the first planar qubit lattice array, are aligned with qubits in the second array, or have an offset between the first and second planar qubit lattice arrays. and at least one additional planar qubit grating array having qubits of substantially equal size and offset along a direction substantially parallel to the second planar qubit grating array. 22. The method of claim 21, wherein each of the logical qubits is optically individually addressed, such that an offset between the first and second planar qubit lattice arrays naturally affects multi-qubit gate operations, A system characterized in that it enables a plurality of observation angles from which the states of the logical qubits are individually detected. 22. The method of claim 21, wherein the offset between the first and second planar qubit lattice arrays allows simultaneous entanglement of more qubits within a given volume and at a given interaction distance in square and cubic lattice configurations. A system characterized by enabling.