KR20230103813A - Semiconductor chip and semiconductor package comprising the same - Google Patents

Abstract

The present disclosure relates to a semiconductor chip including a front end of line (FEOL) layer and a first back end of line (BEOL) layer disposed on the FEOL layer; and a printed circuit board including a wiring layer and a second beol layer disposed on the wiring layer; The semiconductor chip is mounted on the printed circuit board so that the first and second beol layers face each other and are connected to each other, and the second beol layer includes a wire for power transmission. will be.

Description

Semiconductor chip and semiconductor package including the same {SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE COMPRISING THE SAME}

The present disclosure relates to a semiconductor package in which a semiconductor chip is mounted on a printed circuit board such as a package substrate and/or an interposer substrate, and a semiconductor chip included therein.

Recently, the demand for high-performance semiconductors is increasing. Due to such high-speed and high-performance semiconductor chips, the number of layers of semiconductor chips or the density of circuits is increasing, and as a result, manufacturing costs are significantly increasing. In addition, yield problems are also occurring. For example, according to the manufacture of high-performance semiconductors, the number of layers of back end of line (BEOL) of semiconductor chips or the density of circuits may increase, which may greatly increase manufacturing costs and also increase manufacturing costs. Defects may occur during production, which may cause cost problems due to yield reduction.

One of the various objects of the present disclosure is to provide a semiconductor package capable of reducing process costs and a semiconductor package including the same.

Another object of the present disclosure is to provide a semiconductor chip and a semiconductor package including the same, which can solve a cost problem caused by a decrease in yield.

One of the various solutions proposed through the present disclosure is to form a part of the beol layer of a semiconductor chip including power transmission wiring on a printed circuit board such as a package substrate and/or an interposer substrate.

For example, a semiconductor package according to an example may include a semiconductor chip including a front end of line (FEOL) layer and a first back end of line (BEOL) layer disposed on the FEOL layer; and a printed circuit board including a wiring layer and a second beol layer disposed on the wiring layer; The semiconductor chip may be mounted on the printed circuit board such that the first and second beol layers are connected to each other, and the second beol layer may include a wire for power transmission.

For example, a semiconductor package according to an example may include a semiconductor chip including a first beol layer; an interposer substrate including a second beol layer; and a package substrate including a wiring layer; The semiconductor chip is mounted on the interposer substrate, the interposer substrate is mounted on the package substrate, the first and second beol layers are connected to each other, and the second beol layer is a power It may also include a wire for transmission.

For example, a semiconductor according to an example may include a POLE layer including a plurality of circuit parts each including a plurality of transistor elements; and a veil layer disposed on the veil layer and including a wiring portion electrically connected to the plurality of circuit portions; The wiring part may not include a power transmission trace pattern interconnecting at least two of the plurality of circuit parts.

For example, a semiconductor package according to an example is disposed on a pickle layer including a first circuit part including a plurality of first transistor elements and a second circuit part including a plurality of second transistor elements, and the pickol layer, and the a semiconductor chip including a first beol layer including a first wiring part electrically connected to the first and second circuit parts; and a second beol layer including a second wiring part electrically connected to the first wiring part; wherein the semiconductor chip is mounted on the printed circuit board, and the first wiring part does not include a power transmission trace pattern interconnecting the first and second circuit parts in the first beol layer; The second wiring part may include a power transmission trace pattern interconnecting the first and second circuit parts in the second beol layer.

As one of the various effects of the present disclosure, a semiconductor chip capable of reducing process cost and a semiconductor package including the same may be provided.

As another effect among several effects of the present disclosure, a semiconductor chip and a semiconductor package including the same can be provided, which can improve a cost problem caused by a decrease in yield.

1 is a block diagram schematically illustrating an example of an electronic device system.
2 is a perspective view schematically showing an example of an electronic device.
3 is a cross-sectional view schematically illustrating an example of a semiconductor package.
4 is a schematic cross-sectional view of another example of a semiconductor package.
5 is a schematic cross-sectional view of another example of a semiconductor package.
6 is a cross-sectional view schematically illustrating wiring for power transmission in a semiconductor package after a portion of a beol layer of a semiconductor chip is applied to a printed circuit board.
7A is a cross-sectional view schematically showing a plurality of metal layers of a beol layer of a semiconductor chip before a portion of the beol layer of the semiconductor chip is applied to a printed circuit board.
7B and 7C are plan views schematically illustrating layers M1 and M2 among the plurality of metal layers of FIG. 7A, respectively.
8A is a cross-sectional view schematically illustrating a plurality of metal layers of a beol layer of a semiconductor chip after a portion of the beol layer of the semiconductor chip is applied to a printed circuit board.
8B and 8C are plan views schematically illustrating layers M1 and M2 among the plurality of metal layers of FIG. 8A, respectively.
9A and 9B are cross-sectional views schematically illustrating an internal structure of a semiconductor chip before and after applying a portion of the beol layer of the semiconductor chip to a printed circuit board, respectively.
9C is a cross-sectional view schematically illustrating a modified example of the semiconductor chip of FIG. 9B.
10 is a cross-sectional view schematically illustrating an example of a package substrate.
11 is a schematic cross-sectional view of another example of a package substrate.
12 is a schematic cross-sectional view of an example of an interposer substrate.
13 is a schematic cross-sectional view of another example of an interposer substrate.
14 is a cross-sectional view schematically illustrating another example of an interposer substrate.
15 is a cross-sectional view schematically illustrating another example of an interposer substrate.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. The shapes and sizes of elements in the drawings may be exaggerated or reduced for clearer description.

Electronics

1 is a block diagram schematically illustrating an example of an electronic device system.

Referring to the drawing, the electronic device 1000 accommodates the main board 1010. A chip-related component 1020, a network-related component 1030, and other components 1040 are physically and/or electrically connected to the main board 1010. These are combined with other electronic components to be described later to form various signal lines 1090 .

The chip-related component 1020 includes memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Logic chips such as central processors (eg, CPU), graphics processors (eg, GPUs), digital signal processors, cryptographic processors, microprocessors, microcontrollers, application processors, analog-to-digital converters, application-specific ICs (ASICs); etc. are included, but are not limited thereto, and other types of chip-related electronic components may be included as well. In addition, it goes without saying that these chip-related components 1020 may be combined with each other. The chip-related component 1020 may be in the form of a package including the aforementioned chip or electronic component.

As the network related parts 1030, Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, LTE (long term evolution), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G, and any other wireless and wired protocols designated thereafter, including, but not limited to, many other wireless or wired protocols. Any of the standards or protocols may be included. In addition, it goes without saying that the network-related components 1030 and the chip-related components 1020 may be combined with each other.

The other parts 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low Temperature Co-Firing Ceramics), EMI (Electro Magnetic Interference) filters, MLCC (Multi-Layer Ceramic Condenser), and the like. . However, it is not limited thereto, and in addition to this, passive elements in the form of chip components used for various other purposes may be included. In addition, it goes without saying that the other component 1040 may be combined with the chip-related component 1020 and/or the network-related component 1030.

Depending on the type of electronic device 1000 , the electronic device 1000 may include other electronic components that may or may not be physically and/or electrically connected to the main board 1010 . Examples of other electronic components include a camera module 1050, an antenna module 1060, a display 1070, and a battery 1080. However, it is not limited thereto, and audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage devices (eg, hard disk drives), CDs (compact disks), DVDs (digital versatile disks), etc. may be In addition to this, it goes without saying that other electronic components used for various purposes may be included depending on the type of the electronic device 1000 .

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer ( computer, monitor, tablet, laptop, netbook, television, video game, smart watch, automotive, and the like. However, it is not limited thereto, and may be any other electronic device that processes data in addition to these.

2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawing, the electronic device may be, for example, a smart phone 1100. A motherboard 1110 is accommodated inside the smart phone 1100, and various parts 1120 are physically and/or electrically connected to the motherboard 1110. In addition, other components that may or may not be physically and/or electrically connected to the motherboard 1110, such as the camera module 1130 and/or the speaker 1140, are accommodated therein. Some of the components 1120 may be the aforementioned chip-related components, for example, the semiconductor package 1121, but is not limited thereto. The semiconductor package 1121 may have a form in which a semiconductor chip or the like is surface mounted on a printed circuit board such as a package substrate and/or an interposer substrate. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above, of course.

semiconductor package

3 is a cross-sectional view schematically illustrating an example of a semiconductor package.

Referring to the drawing, a semiconductor package 500A according to an example includes a semiconductor chip 300 including a peol layer 310 and a first beol layer 320 disposed on the peol layer 310, and a wiring layer 110A. and a printed circuit board 100A including a second beol layer 120A disposed on the wiring layer 110A. The semiconductor chip 300 is mounted on the printed circuit board 100A such that the first and second beol layers 320 and 120A are connected to each other. The second beol layer 120A includes wires for power transmission. The printed circuit board 100A may be a package board, but is not limited thereto.

On the other hand, demand for high-performance semiconductors is increasing recently. Due to such high-speed and high-performance semiconductor chips, the number of layers of semiconductor chips or the density of circuits is increasing, and as a result, manufacturing costs are significantly increasing. In addition, yield problems are also occurring. For example, according to the manufacture of high-performance semiconductors, the number of BEOL layers of a semiconductor chip or the circuit density may increase, which may greatly increase manufacturing costs, and also cause defects during manufacturing to decrease yield. Cost issues may arise.

On the other hand, in the semiconductor package 500A according to an example, a part of the existing beol layer of the semiconductor chip 300, more specifically, a metal layer including power transmission wiring having a relatively large wiring pitch is provided on the printed circuit board 100A. form In this case, the number of layers of the printed circuit board 100A may be increased, but the number of layers of the existing beol layer of the semiconductor chip 300, which is relatively difficult and expensive to process, may be reduced, and thus the process cost is reduced when viewed as a whole package. can be drastically reduced. In addition, it is more advantageous in terms of cost when the printed circuit board 100A is discarded due to a defect in the power transmission wiring than in the case where the semiconductor chip 300 is discarded due to a defect in the power transmission wiring. Cost issues can also be improved.

The semiconductor chip 300 may include an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. At this time, the integrated circuit is, for example, a central processor (eg, CPU), a graphics processor (eg, GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an application processor (eg, an AP), an analog-to-digital converter, and a logic chip such as an application-specific IC (ASIC). Alternatively, it may be a memory chip such as a volatile memory (eg, DRAM), a non-volatile memory (eg, ROM), a flash memory, or a high bandwidth memory (HBM). Alternatively, it may be another type of chip such as a Power Management IC (PMIC).

The peol layer 310 may include a semiconductor substrate, a transistor element formed on the semiconductor substrate, and a metal contact region formed on the transistor element. Here, the peol layer may include a middle end of line (MEOL) layer. For example, the metal contact region may include a contact hole and a plug connecting the metal layer and the p and n junction diffusion layer on the silicon substrate or connecting the metal layer and the polysilicon electrode.

The first beol layer 320 may include a plurality of insulating layers and a plurality of metal layers. In this case, the plurality of insulating layers may include an inorganic insulating material. Also, the plurality of metal layers may include a metal material. The plurality of metal layers may mainly include signal transmission wiring, and may further include some power transmission wiring and/or ground transmission wiring, if necessary. Here, mainly including the signal transmission wiring may mean that the total area occupied by the signal transmission wiring on a plane is larger than the total area occupied by the power transmission wiring and/or the ground transmission wiring. In the case of a plurality of layers, the area of each layer on a plane can be combined and compared, and the determination can be made by excluding vias overlapping the traces of each layer. Each wiring may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern. The first beol layer 320 may be formed on a semiconductor substrate, for example, a silicon substrate, and thus may be formed at a higher density.

The wiring layer 110A may include a plurality of insulating layers and a plurality of metal layers. In this case, the plurality of insulating layers may include an organic insulating material. Also, the plurality of metal layers may include a metal material. Also, the plurality of metal layers may include wires for transmitting various wires in the wiring layer 110A, for example, wires for power transmission, wires for signal transmission, and/or wires for ground transmission. Each wiring may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern or the like. A plurality of insulating layers and a plurality of wiring layers may be alternately stacked. The wiring layer 110A may be formed on a first organic substrate, and thus may be formed more easily at a lower cost.

The second beol layer 120A may include one or more insulating layers and one or more metal layers. At this time, one or more insulating layers may include an organic insulating material. In addition, one or more metal layers may include a metal material. The one or more metal layers may mainly include wires for power transmission, and may further include some wires for signal transmission and/or wires for ground transmission, if necessary. Here, the wiring for power transmission may be a wiring for transmitting power to the semiconductor chip 300 . In addition, mainly including the power transmission wiring may mean that the total area occupied by the power transmission wiring on a plane is larger than the total area occupied by the signal transmission wiring and/or the ground transmission wiring. In the case of a plurality of layers, the area of each layer on a plane can be combined and compared, and the determination can be made by excluding vias overlapping the trace patterns of each layer. Each wiring may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern or the like. The second beol layer 120A may be formed on an organic substrate, and thus may be easily formed at a low cost.

The first beol layer 320 may be disposed adjacent to the bottom side of the semiconductor chip 300 . The second beol layer 120A may be disposed adjacent to the top side of the printed circuit board 100A. In this way, the first and second beol layers 320 and 120A may be disposed adjacent to each other and connected to each other, and thus side effects due to separation of the existing beol layers of the semiconductor chip 300 may be minimized.

The wiring pitch of the second beol layer 120A may be greater than that of the first beol layer 320 . The second beol layer 120A has a relatively large pitch and mainly includes wires for power transmission formed in a larger size, and is formed on the printed circuit board 100A, so the pitch may be relatively larger. On the other hand, the first beol layer 320 has a relatively small pitch and mainly includes wirings for signal transmission formed in a smaller size, and is formed on the semiconductor chip 300, so the pitch may be relatively smaller. . Meanwhile, the pitch may be measured using a scanning microscope or the like, and may roughly mean an average value. For example, it may be an average value of the largest number and the smallest value.

The semiconductor package 500A according to an example includes a plurality of connection conductors 330 disposed between the printed circuit board 100A and the semiconductor chip 300 to connect them to each other, and/or the semiconductor chip of the printed circuit board 100A ( 300) may further include a plurality of electrical connection conductors 130 disposed on the opposite side of the mounted side and connected to the printed circuit board 100A.

The plurality of connection conductors 330 may provide an electrical connection path between the printed circuit board 100A and the semiconductor chip 300 . The plurality of electrical connection conductors 130 may provide electrical connection paths when the semiconductor package 500A is mounted on another substrate, such as a main board. Each of the plurality of connection conductors 330 may be a solder bump, but is not limited thereto. Each of the plurality of electrical connection conductors 130 may be solder balls, but is not limited thereto.

4 is a schematic cross-sectional view of another example of a semiconductor package.

Referring to the drawings, a semiconductor package 500B according to another example includes a semiconductor chip 300 including a peol layer 310 and a first beol layer 320 disposed on the peol layer 310, a first wiring layer ( 210A) and an interposer substrate 200A including a second beol layer 220A disposed on the first wiring layer 210A, and a package substrate 100B including a second wiring layer 110B. The semiconductor chip 300 is mounted on the interposer substrate 200A such that the first and second beol layers 320 and 220A are connected to each other. The interposer substrate 200A is mounted on the package substrate 100B such that the first and second wiring layers 210A and 110B are connected to each other. The interposer substrate 200A is an organic interposer in which wiring is formed on an insulating layer containing an organic insulating material, for example, a coreless type substrate, or an inorganic interposer in which wiring is formed on an insulating layer containing an inorganic insulating material; For example, it may be a silicon interposer, but is not limited thereto.

In the semiconductor package 500B according to another example, a portion of the existing beol layers of the semiconductor chip 300, more specifically, a metal layer including power transmission wiring having a relatively large wiring pitch is formed on the interposer substrate 200A. do. In this case, the number of layers of the interposer substrate 200A may be increased, but the number of layers of the existing beol layer of the semiconductor chip 300, which is relatively difficult and expensive to process, may be reduced, and thus the process cost is reduced when viewed as a whole package. can be drastically reduced. In addition, it is more advantageous in terms of cost when the interposer substrate 200A is discarded due to a defect in the power transmission wiring than in the case where the semiconductor chip 300 is discarded due to a defect in the power transmission wiring. Cost issues can also be improved.

The first wiring layer 210A may include a plurality of insulating layers and a plurality of metal layers. In this case, the plurality of insulating layers may include an organic insulating material or an inorganic insulating material. Also, the plurality of metal layers may include a metal material. Also, the plurality of metal layers may include wires for transmitting various wires in the first wiring layer 210A, for example, wires for power transmission, wires for signal transmission, and/or wires for ground transmission. Each wiring may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern or the like. A plurality of insulating layers and a plurality of wiring layers may be alternately stacked.

The second beol layer 220A may include one or more insulating layers and one or more metal layers. At this time, one or more insulating layers may include an organic insulating material or an inorganic insulating material. In addition, one or more metal layers may include a metal material. The one or more metal layers may mainly include wires for power transmission, and may further include some wires for signal transmission and/or wires for ground transmission, if necessary. Here, the wiring for power transmission may be a wiring for transmitting power to the semiconductor chip 300 . In addition, mainly including the power transmission wiring may mean that the total area occupied by the power transmission wiring on a plane is larger than the total area occupied by the signal transmission wiring and/or the ground transmission wiring. In the case of a plurality of layers, the area of each layer on a plane can be combined and compared, and the determination can be made by excluding vias overlapping the trace patterns of each layer. Each wiring may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern or the like.

The first beol layer 320 may be disposed adjacent to the bottom side of the semiconductor chip 300 . The second beol layer 220A may be disposed adjacent to the top side of the interposer substrate 200A. As such, the first and second beol layers 320 and 220A may be disposed adjacent to each other and connected to each other, and thus side effects caused by separation of the existing beol layers of the semiconductor chip 300 may be minimized.

The wiring pitch of the second beol layer 220A may be greater than that of the first beol layer 320 . The second beol layer 220A has a relatively large pitch and mainly includes wirings for power transmission formed in a larger size, and is formed on the interposer substrate 200A, so the pitch may be relatively larger. On the other hand, the first beol layer 320 has a relatively small pitch and mainly includes wirings for signal transmission formed in a smaller size, and is formed on the semiconductor chip 300, so the pitch may be relatively smaller. . Meanwhile, the pitch may be measured using a scanning microscope or the like, and may roughly mean an average value. For example, it may be an average value of the largest number and the smallest value.

The semiconductor package 500B according to another example includes a plurality of connection conductors 330 disposed between a semiconductor chip 300 and an interposer substrate 200A to connect them to each other, the interposer substrate 200A, and the package substrate 100B. A plurality of first electrical connection conductors 230 disposed between the plurality of first electrical connection conductors 230 and/or the interposer substrate 200A of the package substrate 100B are disposed on the opposite side of the package substrate 100B to connect the package substrate 100B. A plurality of second electrical connection conductors 130 may be further included.

The plurality of connection conductors 330 may provide an electrical connection path between the interposer substrate 200A and the semiconductor chip 300 . The plurality of first electrical connection conductors 230 may provide an electrical connection path between the package substrate 100B and the interposer substrate 200A. The plurality of second electrical connection conductors 130 may provide electrical connection paths when the semiconductor package 500B is mounted on another substrate, such as a main board. Each of the plurality of connection conductors 330 may be a solder bump, but is not limited thereto. Each of the plurality of first and second electrical connection conductors 230 and 130 may be a solder ball, but is not limited thereto.

In addition, other content, for example, content that is not contradictory among the content described in the semiconductor package 500A according to the above-described example may also be applied to the semiconductor package 500B according to the above-described example, and overlapping descriptions thereof omit

5 is a schematic cross-sectional view of another example of a semiconductor package.

Referring to the drawings, a semiconductor package 500C according to another example includes a semiconductor chip 300 including a peol layer 310 and a first beol layer 320 disposed on the peol layer 310, and a second beol layer. It includes an interposer substrate 200B including 220B, and a package substrate 100B including a wiring layer 110B. The semiconductor chip 300 is mounted on the interposer substrate 200B such that the first and second beol layers 320 and 220B are connected to each other. The interposer substrate 200B is mounted on the package substrate 100B so that the second beol layer 220B and the wiring layer 110B are connected to each other. The interposer substrate 200B is an organic interposer in which wiring is formed on an insulating layer containing an organic insulating material, for example, a coreless type substrate, or an inorganic interposer in which wiring is formed on an insulating layer containing an inorganic insulating material, For example, it may be a silicon interposer, but is not limited thereto.

In the semiconductor package 500C according to another example, a portion of the existing beol layers of the semiconductor chip 300, more specifically, a metal layer including power transmission wiring having a relatively large wiring pitch is formed on the interposer substrate 200B. do. In this case, the number of layers of the interposer substrate 200B may be increased, but the number of layers of the existing beol layer of the semiconductor chip 300, which is relatively difficult and costly to process, may be reduced, and therefore, process cost when viewed as a whole package may be reduced. can be drastically reduced. In addition, it is more advantageous in terms of cost when the interposer substrate 200B is discarded due to a defect in the power transmission wiring than in the case where the semiconductor chip 300 is discarded due to a defect in the power transmission wiring. Cost issues can also be improved.

In the semiconductor package 500C according to another example, the interposer substrate 200B includes the second beol layer 220B but does not include an additional wiring layer. Accordingly, the number of layers of the interposer substrate 200B can be minimized. Therefore, the thickness can be reduced, the difficulty of the process can be reduced, and the yield can be improved.

The second beol layer 220B may include one or more insulating layers and one or more metal layers. At this time, one or more insulating layers may include an organic insulating material or an inorganic insulating material. In addition, one or more metal layers may include a metal material. The one or more metal layers may mainly include wires for power transmission, and may further include some wires for signal transmission and/or wires for ground transmission, if necessary. Here, the wiring for power transmission may be a wiring for transmitting power to the semiconductor chip 300 . In addition, mainly including the power transmission wiring may mean that the total area occupied by the power transmission wiring on a plane is larger than the total area occupied by the signal transmission wiring and/or the ground transmission wiring. In the case of a plurality of layers, the area of each layer on a plane can be combined and compared, and the determination can be made by excluding vias overlapping the trace patterns of each layer. Each wiring may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern or the like. One or more insulating layers and one or more metal layers may be alternately laminated with each other.

Other content, for example, content that is not contradictory among the content described in the above-described semiconductor packages 500A and 500B may also be applied to the semiconductor package 500C according to another example described above, and overlapping descriptions thereof is omitted.

6 is a cross-sectional view schematically illustrating wiring for power transmission in a semiconductor package after a portion of a beol layer of a semiconductor chip is applied to a printed circuit board.

Meanwhile, for convenience of description, components other than transistor elements and wires for power transmission are omitted in the drawings, and the omitted components can be understood based on the above-described or later descriptions.

Referring to the drawings, a semiconductor package 5000 includes a printed circuit board 1000 and a semiconductor chip 3000 mounted on the printed circuit board 1000 . The semiconductor chip 3000 includes a peol layer 3100 and a first peol layer 3200 disposed on the peol layer 3100 . The peol layer 3100 includes a first circuit part 3110 including a plurality of first transistor elements 3111, 3112, and 3113 and a second circuit part 3120 including a plurality of second transistor elements 3121, 3122, and 3123. ). The first beol layer 3200 includes a first wiring part 3201 electrically connected to the first and second circuit parts 3110 and 3120 . The second beol layer 1200 includes a second wiring part 1201 electrically connected to the first wiring part 3201 .

The first wiring unit 3201 does not include a trace pattern for power transmission interconnecting the first and second circuit units 3110 and 3120 in the first beol layer 3200 . For example, the first wiring part 3201 is a power transmission wiring that is independently connected to the first and second circuit parts 3110 and 3120 in the first beol layer 3200, specifically vias for power transmission. Can only contain patterns. Each of the first and second circuit units 3110 and 3120 may be a unit circuit having a specific function or a larger unit block circuit. The peol layer 3100 may include more such circuit units, and the first wiring unit 3201 may not include a power transmission trace pattern interconnecting at least two of the plurality of circuit units. This interconnection may be performed in the second beol layer 1200 of the printed circuit board 1000 . Meanwhile, although not shown in the drawing, the first wiring unit 3201 may further include a signal transmission wiring and/or a ground transmission wiring in addition to power transmission wiring, and their trace patterns are the first beol layer 3200 ), but may interconnect the first and second circuit units 3110 and 3120 within, but is not limited thereto.

The first wiring unit 3201 may not include a trace pattern for power transmission that interconnects at least two of the plurality of first transistor elements 3111, 3112, and 3113 in the first beol layer 3200. A trace pattern for power transmission interconnecting at least two of the second transistor elements 3121, 3122, and 3123 may not be included. As such, if necessary, the first wiring unit 3201 may not include a trace pattern for power transmission for interconnection between elements of the smallest unit. Meanwhile, although not shown in the drawing, the first wiring unit 3201 may further include a signal transmission wiring and/or a ground transmission wiring in addition to power transmission wiring, and their trace patterns are the first beol layer 3200 ), at least two of the plurality of first transistor elements 3111, 3112, and 3113 may be interconnected, and/or at least two of the plurality of second transistor elements 3121, 3122, and 3123 may be interconnected, It is not limited to this.

The second wiring unit 1201 includes a trace pattern for power transmission interconnecting the first and second circuit units 3110 and 3120 in the second beol layer 1200 . For example, the second wiring part 1201 is the first and second circuit parts 3110 of the first beol layer 3100 omitted from the first wiring part 3201 of the first beol layer 3200 of the semiconductor chip 3000. , 3120) may include a trace pattern for power transmission for interconnection. The same may be true even when the peol layer 3100 includes a larger number of circuit units. Meanwhile, although not shown in the drawings, the second wiring unit 1201 may further include a signal transmission wiring and/or a ground transmission wiring in addition to the power transmission wiring, and the signal transmission wiring and/or the ground transmission wiring The trace pattern of may not interconnect the first and second circuit units 3110 and 3120 in the second beol layer 1200, but is not limited thereto.

The second wiring unit 1201 may also include a trace pattern for power transmission that interconnects at least two of the plurality of first transistor elements 3111, 3112, and 3113 in the second beol layer 1200, and may include a plurality of A trace pattern for power transmission interconnecting at least two of the second transistor elements 3121, 3122, and 3123 may also be included. As described above, the second wiring unit 1201 may include a trace pattern for power transmission for interconnection between devices of the smallest unit as well as for interconnection between large unit circuit units. Meanwhile, although not shown in the drawing, the plurality of second wiring units 1201 may further include signal transmission wiring and/or ground transmission wiring in addition to power transmission wiring, and their trace patterns are the second beol layer In 1200, at least two of the plurality of first transistor elements 3111, 3112, and 3113 are not interconnected, and/or at least two of the plurality of second transistor elements 3121, 3122, and 3123 are not interconnected. It may not be, but is not limited thereto.

Meanwhile, the printed circuit board 1000 may be a package substrate, an interposer substrate, and the like, and thus, the description of the above-described semiconductor packages 500A, 500B, and 500C may also be applied to the semiconductor package 5000 . For example, the printed circuit board 1000 may further include a separate wiring layer connected to the second wiring part 1202 . In addition, when the printed circuit board 1000 is an interposer board, a printed circuit board such as a separate package board including a wiring part connected to the second wiring part 1202 may be further disposed. In addition, for the specific structure of the printed circuit board 1000, package substrates 100A-1 and 100A-2 and interposer substrates 200A-1, 200A-2, 200B-1 and 200B-2, which will be described later, are applied. can In addition, the structure of the beol layer 1320-2 or the structure of the semiconductor chips 300, 300', and 300", which will be described later, may be applied to the semiconductor chip 3000. Redundant descriptions thereof will be omitted.

7A is a cross-sectional view schematically showing a plurality of metal layers of a beol layer of a semiconductor chip before a portion of the beol layer of the semiconductor chip is applied to a printed circuit board.

7B and 7C are plan views schematically illustrating layers M1 and M2 among the plurality of metal layers of FIG. 7A, respectively.

In the drawings, only some layers may be shown for convenience of illustration, and some vias are shown along with patterns for convenience of description even though they are located under the pattern of the upper metal layer to indicate the connection between the pattern of the upper metal layer and the pattern of the lower metal layer. It can be.

Referring to the drawing, a beol layer 1320-1 of a semiconductor chip includes a plurality of metal layers M1, M2, M3, M4, ... M8, M9, .... The number of metal layers (M1, M2, M3, M4, ... M8, M9, ...) is not particularly limited and may vary depending on the design. The metal layers M1, M2, M3, M4, ... M8, M9, ... may include a trace pattern and a via pattern, and in this case, the trace pattern may include a pad pattern connected to the via pattern. The metal layers M1, M2, M3, M4, ... M8, M9, ... may include a low resistance conductive material such as copper (Cu), aluminum (Al), or tungsten (W).

Among the plurality of metal layers (M1, M2, M3, M4, ... M8, M9, ...), metal layers (M1, M2, M3, M4) adjacent to the Feol layer of the semiconductor chip, for example, the first and second metal layers (M1, M2, M3, M4) The second metal layers M1 and M2 may include power transmission trace patterns P1 and P2 and signal transmission trace patterns P3. In addition, via patterns V_P1 and V_P2 for power transmission connected to trace patterns P1 and P2 for power transmission may be included. Also, although not shown in the drawing, a via pattern for signal transmission connected to the trace pattern P3 for signal transmission may be included.

The trace pattern P1 for first power transmission may include a trace pattern for a positive supply voltage VDD. The via pattern V_P1 for first power transmission may include a via pattern for a positive supply voltage VDD. The second power transmission trace pattern P2 may include a trace pattern for a negative supply voltage VSS. The via pattern V_P2 for second power transmission may include a via pattern for a negative supply voltage VSS. However, the present invention is not limited thereto, and the power transmission trace patterns P1 and P2 and the power transmission via patterns V_P1 and V_P2 may include different types of voltage patterns. The trace pattern and the via pattern for the negative supply voltage (VSS) may be both a voltage pattern and a ground pattern. That is, if necessary, the voltage pattern may include a ground pattern.

Meanwhile, the metal layers M1, M2, M3, and M4 adjacent to the PEOL layer of the semiconductor chip, for example, the first and second metal layers M1 and M2 are layers having a high circuit density, for example, signal transmission. A fine pitch of the dragon trace pattern P3 may be required. In this case, when the power transmission trace patterns P1 and P2 having a relatively large wiring pitch are designed together with the signal transmission trace patterns P3 in the first and second metal layers M1 and M2, as described above, , the process difficulty may be higher. As a result, manufacturing costs may greatly increase, and defects may occur during the manufacturing process, resulting in cost problems due to yield reduction.

8A is a cross-sectional view schematically illustrating a plurality of metal layers of a beol layer of a semiconductor chip after a portion of the beol layer of the semiconductor chip is applied to a printed circuit board.

8B and 8C are plan views schematically illustrating layers M1 and M2 among the plurality of metal layers of FIG. 8A, respectively.

In the drawings, only some layers may be shown for convenience of illustration, and some vias are shown along with patterns for convenience of description even though they are located under the pattern of the upper metal layer to indicate the connection between the pattern of the upper metal layer and the pattern of the lower metal layer. It can be.

Referring to the drawing, the beol layer 1320-2 of the semiconductor chip includes a plurality of metal layers M1, M2, M3, ... M7, .... At this time, a portion of the beol layer 1320-2 of the semiconductor chip is applied to the printed circuit board. ...) can be reduced. For example, among the plurality of metal layers M1, M2, M3, ... M7, ..., metal layers M1, M2, and M3 adjacent to the Feol layer of the semiconductor chip, for example, first and second metal layers M1, M2, M3, ... The metal layers M1 and M2 include the trace pattern P3 for signal transmission, but may not include the aforementioned trace patterns P1 and P2 for power transmission. For example, the aforementioned power transmission trace patterns P1 and P2 may be separately designed as beol layers on a printed circuit board. In this case, the first and second metal layers M1 and M2 may include only power transmission via patterns V_P1 and V_P2 without the aforementioned power transmission trace patterns P1 and P2. The power transmission via patterns V_P1 and V_P2 may be electrically connected to the power transmission wiring of the beol layer designed on the printed circuit board including the power transmission trace patterns P1 and P2 described above. If necessary, some of the power transmission trace patterns (P1, P2) are relatively distant from the metal layers (M1, M2, M3, ... M7, ...) of the semiconductor chip. Further metal layers M7, for example, the seventh metal layer M7 may be designed.

As such, at least a portion of the trace patterns P1 and P2 for power transmission, which were designed on a portion of the beol layer 1320-2 of the semiconductor chip, for example, the lower metal layers M1 and M2, are separately printed on the printed circuit board. In the case of forming the beol layer of the above, the number of layers of the existing beol layer of the semiconductor chip, which is difficult and expensive to process, can be reduced, and the signal transmission trace pattern P3 can be designed with a larger pitch, thereby significantly reducing the process cost. can reduce In addition, cost problems due to a decrease in the yield of semiconductor chips can be improved.

Meanwhile, the description of the above-described beol layer 1320-1 of the semiconductor chip may be applied to the beol layer 1320-2 of the semiconductor chip as long as it does not contradict, and duplicate descriptions thereof will be omitted. In addition, as long as the contents described in the semiconductor packages 500A, 500B, 500C, and 5000 described above and the contents described in the semiconductor chips 300, 300', and 300" to be described later do not contradict each other, the beol layer 1320 of the semiconductor chip -2) can also be applied, and similarly, redundant descriptions of them are omitted.

9A and 9B are cross-sectional views schematically illustrating an internal structure of a semiconductor chip before and after applying a portion of the beol layer of the semiconductor chip to a printed circuit board, respectively.

Meanwhile, in FIGS. 9A and 9B , the internal structure of a partial region of the semiconductor chip is enlarged and schematically illustrated, and other regions can be understood accordingly.

Referring to the drawing, the semiconductor chips 300 and 300" each include beol layers 310 and 310" and beol layers 320 and 320". At this time, a portion of the beol 320" is placed on a printed circuit board. Prior to application, the beol layer 320″ includes more layers of metal layer 324″. Therefore, manufacturing costs may greatly increase, and if a defect occurs during manufacturing, the semiconductor chip 300" should be discarded, which may cause a large cost problem due to a decrease in yield. On the other hand, the When a part is applied to a printed circuit board, the beol layer 320 includes a smaller number of metal layers 324. Therefore, the manufacturing cost can be greatly reduced, and the probability of defects occurring during manufacturing is reduced, so that the semiconductor chip ( 300) can also be improved.

However, it is not limited thereto, and if necessary, the number of layers of the metal layer 324 is similar to or the same as that of the metal layer 324″, but the circuit density of each layer may be wider. For example, each Most of the wiring for power transmission in the layer can be omitted, and it is possible to form more spacious wiring for signal transmission, etc. Even in this case, the manufacturing cost can be greatly reduced, and the probability of occurrence of defects during manufacturing is reduced, so that the semiconductor chip ( 300) can also be improved.

Meanwhile, the peol layers 310 and 310" are formed on the semiconductor substrates 311, 312, 311" and 312" and the lower insulating layers 313 and 313" disposed on the semiconductor substrates 311, 312, 311" and 312". ), the transistor elements 314 and 314" disposed on the semiconductor substrates 311, 312, 311" and 312" and surrounded by the lower insulating layers 313 and 313", the transistor elements 314 and 314" and the lower insulating layer Insulating films 315 and 315" covering the layers 313 and 313", upper insulating layers 316 and 316" disposed on the insulating films 315 and 315", and/or upper insulating layers 316 and 316" ) may include plugs 317 and 317″ penetrating.

The semiconductor substrates 311, 312, 311", and 312" may include a semiconductor material, for example, a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The semiconductor substrates 311, 312, 311", and 312" may be provided as, for example, a bulk wafer, an epitaxial layer, an epitaxial layer, a silicon on insulator (SOI) layer, or a semiconductor on insulator (SeOI) layer. It may be possible, but is not limited thereto.

The transistor elements 314 and 314" may include a gate insulating layer, a gate electrode, a capping layer, a spacer, etc. Source/drain regions may be disposed on both sides of the transistor elements 314 and 314". The transistor elements 314 and 314″ may be located in the cell region and may include, for example, a DRAM memory element, a flash memory element, or a CMOS image sensor (CIS) element, but are not limited thereto, and the Of course, other logic elements, power elements, and the like may also be included.

The plugs 317 and 317" may be electrically connected to the transistor elements 314 and 314" and the metal layers 324 and 324". The plugs 317 and 317" may be made of copper (Cu), tungsten (W), or Combinations of these may be included.

In addition, the beol layers 320 and 320″ include the interlayer insulating layers 321 and 321″, the first interlayer insulating films 322 and 322″ disposed between the interlayer insulating layers 321 and 321″, and the second interlayer insulating film ( 323 and 323"), the metal layers 324 and 324" formed on the interlayer insulating layers 321 and 321", and/or the protective layers 325 and 325" disposed on the interlayer insulating layers 321 and 321" can include

The interlayer insulating layers 321 and 321″ may include, for example, oxide, nitride, or oxynitride, and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride, but are limited thereto. No. Each layer of the interlayer insulating layers 321 and 321″ may include the same material or different materials.

The metal layers 324 and 324" may include, for example, a low-resistance conductive material such as copper (Cu), aluminum (Al), or tungsten (W). Each of the metal layers 324 and 324" The layers may include the same material or different materials. Each of the metal layers 324 and 324" may include a trace pattern, a via pattern, etc. The trace pattern may include a pad pattern connected to the via pattern. Unlike the metal layer 324", the metal layer 324 ) may mainly include wiring for signal transmission. Here, mainly including the signal transmission wiring may mean that the total area occupied by the signal transmission wiring on a plane is larger than the total area occupied by the power transmission wiring and/or the ground transmission wiring. In the case of a plurality of layers, the area of each layer on a plane can be combined and compared, and the determination can be made by excluding the via pattern overlapping the trace pattern of each layer.

The metal layers 324 and 324″ may be surrounded by an anti-diffusion layer. The anti-diffusion layer is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co) , manganese (Mn), tungsten nitride (WN), nickel (Ni), and nickel boron (NiB).

Meanwhile, sealing layers 340 and 340" may be further disposed on the protective layers 325 and 325", and underbumps are formed in via holes penetrating the protective layers 325 and 325" and the sealing layers 340 and 340". Metal layers 351 and 351" and surface treatment layers 352 and 352" may be further disposed. Connection conductors 330 and 330" may be further disposed on the surface treatment layers 352 and 352".

The under bump metal layers 351 and 351" and the surface treatment layers 352 and 352" may improve connection reliability with the connection conductors 330 and 330". The under bump metal layers 351 and 351" may be chromium (Cr) ) layer and a copper (Cu) layer, and the surface treatment layers 352 and 352″ may include a nickel (Ni) layer and a gold (Au) layer, but are not limited thereto.

The connection conductors 330 and 330" may be formed of a low melting point metal, for example, solder such as tin (Sn)-aluminum (Al)-copper (Cu) or tin (Sn)-silver (Ag). For example, the connection conductors 330 and 330" may include solder bumps. However, this is only an example and the material is not particularly limited thereto.

Meanwhile, the structure described above is merely an example of the semiconductor chip 300 or 300", and the internal structure of the semiconductor chip 300 or 300" may be modified differently.

Other content, for example, content that is not contradictory among the content described in the above-described semiconductor packages 500A, 500B, and 500C may also be applied to the semiconductor chips 300 and 300 ", and overlapping descriptions thereof omit

9C is a schematic cross-sectional view of a modified example of the semiconductor chip of FIG. 9B.

Meanwhile, in FIG. 9C, the internal structure of a partial region of the semiconductor chip is enlarged and schematically illustrated, and other regions can be understood in a similar manner.

Referring to the drawings, the semiconductor chip 300' further includes a redistribution layer 370 disposed on the beol layer 320 in the semiconductor chip 300 described above. The redistribution layer 370 includes one or more insulating layers 371 and one or more metal layers 372 . When the redistribution layer 370 is further disposed, when applied to the above-described semiconductor packages 500A, 500B, and 500C, the separated beol layers may be connected to each other through the redistribution layer 370 . By further forming the redistribution layer 370, the circuit scale for connection with the substrate can be further expanded.

The one or more insulating layers 371 may include an inorganic insulating material such as oxide, nitride, or oxynitride, such as silicon oxide, silicon nitride, or silicon oxynitride. However, it is not limited thereto. The one or more insulating layers 371 may include an organic insulating material, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler such as silica. The number of layers of the one or more insulating layers 371 is not particularly limited, and may be one layer or multiple layers. Each layer may have a boundary from each other, and in some cases may be integrated without a boundary from each other.

The one or more metal layers 372 may include, for example, a low-resistance conductive material such as copper (Cu), aluminum (Al), or tungsten (W). The one or more metal layers 372 may include power transmission wiring, signal transmission wiring, ground transmission wiring, and the like. Each of these wirings may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern or the like. The number of layers of the one or more metal layers 372 is not particularly limited, and may be one layer or a plurality of layers. Each layer may have a boundary from each other, and in some cases may be integrated without a boundary from each other.

Other contents, for example, contents that do not contradict among the contents described in the above-described semiconductor packages 500A, 500B, and 500C and the above-described semiconductor chips 300 and 300" may also be applied to the semiconductor chip 300'. It may be possible, and duplicate descriptions thereof will be omitted.

10 is a cross-sectional view schematically illustrating an example of a package substrate.

Referring to the drawing, a package substrate 100A-1 according to an example includes a wiring layer 110A-1 and a beol layer 120A-1 disposed on the wiring layer 110A-1. The wiring layer 110A-1 includes the core insulating layer 111a, the core metal layer 112a formed on the core insulating layer 111a, and the first and second build-up insulating layers (built up on both sides of the core insulating layer 111a). 111b and 111c) and first and second build-up metal layers 112b and 112c respectively formed on the first and second build-up insulating layers 111b and 111c. The beol layer 120A-1 includes an insulating layer 121 and a metal layer 122 formed on the insulating layer 121. If necessary, a first passivation layer 141 disposed on the wiring layer 110A-1 and having a plurality of openings exposing at least a portion of the lowermost first build-up metal layer 112b, respectively, and a beol layer 120A -1) disposed on the second passivation layer 142 having a plurality of openings respectively exposing at least a portion of the uppermost metal layer 122, and/or on the plurality of openings of the first passivation layer 141 A plurality of electrical connection conductors 130 each formed may be further included.

The core insulating layer 111a may function as a central layer of the package substrate 100A- 1 and may impart rigidity. The material of the core insulating layer 111a is not particularly limited. For example, an insulating material may be used. In this case, the insulating material is a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a mixture of these resins with inorganic fillers such as silica, or glass fibers together with inorganic fillers. (Glass Fiber, Glass Cloth, Glass Fabric), etc., resin impregnated in the core material, for example, prepreg, ABF (Ajinomoto Build-up Film), FR-4, BT (Bismaleimide Triazine), etc. can be used. However, it is not limited thereto. The core insulating layer 111a may be introduced through CCL (Copper Clad Laminate) or the like, but is not limited thereto. The core insulating layer 111a may be thicker than each of the first and second build-up insulating layers 111b and 111c.

The first and second build-up insulating layers 111b and 111c may be introduced on both sides of the core insulating layer 111a for build-up. Materials of the first and second build-up insulating layers 111b and 111c are not particularly limited either. For example, an insulating material may be used. At this time, the insulating material is a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a mixture of these resins with an inorganic filler such as silica, or impregnated core material of the inorganic filler. A prepared resin, for example, prepreg, ABF, FR-4, BT, etc. may be used, but is not limited thereto. The first and second build-up insulating layers 111b and 111c may be introduced through RCC (Resin Coated Copper) or the like, but are not limited thereto. The number of layers of the first and second build-up insulating layers 111b and 111c is not particularly limited and may be variously changed according to design. The first and second build-up insulating layers 111b and 111c may have a distinct boundary from each other, or may be integral to each other to the extent that the boundary is ambiguous.

The core metal layer 112a may perform various functions according to the design of the corresponding layer. For example, it may include a wire for ground transmission, a wire for power transmission, a wire for signal transmission, and the like. The signal transmission wiring may include various signals, for example, data signals, excluding ground transmission wiring and power transmission wiring. Each of these wirings may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern or the like. The core metal layer 112a may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. It may include a conductive material, such as, specifically, a metal material. The core metal layer 112a may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). The via pattern of the core metal layer 112a may have a through-via shape, and may have an hourglass shape or a cylindrical shape in cross section, but is not limited thereto.

The first and second build-up metal layers 112b and 112c may perform various functions according to the design of the corresponding layer. For example, it may include a wire for ground transmission, a wire for power transmission, a wire for signal transmission, and the like. The signal transmission wiring may include various signals, for example, data signals, excluding ground transmission wiring and power transmission wiring. Each of these wirings may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern or the like. The first and second build-up metal layers 112b and 112c may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or a conductive material such as an alloy thereof, specifically a metal material. The first and second build-up metal layers 112b and 112c may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper), respectively. The via patterns of the first and second build-up metal layers 112b and 112c may have a downward or upwardly tapered shape in cross section, but are not limited thereto.

The insulating layer 121 may be disposed on the second build-up insulating layer 111c and may have the same build-up as the second build-up insulating layer 111c. The material of the insulating layer 121 is also not particularly limited. For example, an insulating material may be used. At this time, the insulating material is a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a mixture of these resins with an inorganic filler such as silica, or impregnated core material of the inorganic filler. A prepared resin, for example, prepreg, ABF, FR-4, BT, etc. may be used, but is not limited thereto. The insulating layer 121 may also be introduced through RCC or the like, but is not limited thereto. The number of layers of the insulating layer 121 is not particularly limited and may be variously changed according to design. The insulating layers 121 may have distinct boundaries, or may be integral with each other to the extent that the boundaries are ambiguous.

The metal layer 122 may mainly include wires for power transmission. However, if necessary, a part of signal transmission wiring and/or ground transmission wiring may be further included. Here, the wiring for power transmission may be a wiring for transmitting power to the semiconductor chip. In addition, mainly including the power transmission wiring may mean that the total area occupied by the power transmission wiring on a plane is larger than the total area occupied by the signal transmission wiring and/or the ground transmission wiring. In the case of a plurality of layers, the area of each layer on a plane can be combined and compared, and the determination can be made by excluding vias overlapping pads of each layer. Each of these wirings may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern or the like. The metal layer 122 may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, or the like. Of the conductive material, specifically, may include a metal material. The metal layer 122 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). The via pattern of the metal layer 122 may have a downwardly tapered shape in cross section, but is not limited thereto.

The first and second passivation layers 141 and 142 are disposed on the outermost side of both sides of the package substrate 100A- 1 to protect internal components. Materials of the first and second passivation layers 141 and 142 are not particularly limited. For example, an insulating material may be used, and at this time, a solder resist may be used as the insulating material. However, it is not limited thereto, and ABF or the like may be used.

The plurality of electrical connection conductors 130 may physically and/or electrically connect the package substrate 100A-1 to the outside. For example, the package substrate 100A-1 may be a BGA type substrate. The plurality of electrical connection conductors 130 may include a low melting point metal lower than copper (Cu), for example, tin (Sn) or an alloy containing tin (Sn). For example, the plurality of electrical connection conductors 130 may include solder, but this is only one example, and the material is not particularly limited thereto. The plurality of electrical connection conductors 130 may be lands, balls, pins, and the like. The plurality of electrical connection conductors 130 may be multi-layered or single-layered. When formed as a multi-layer, it may include copper pillars and solder, and when formed as a single layer, it may include solder, but again, this is only one example and is not limited thereto.

As such, the package substrate 100A-1 according to one example may be a core-type multi-layer substrate, and in the case of including the beol layer 120A-1, it may be applied to the semiconductor package 500A according to the above-described example, When the veil layer 120A-1 is replaced with the wiring layer 110A-1, it may be applied to the semiconductor package 500B according to another example described above.

Other content, for example, content that does not contradict among the content described in the above-described semiconductor packages 500A, 500B, and 500C may also be applied to the package substrate 100A-1, and redundant description thereof will be omitted. .

11 is a schematic cross-sectional view of another example of a package substrate.

Referring to the drawings, a package substrate 100A-2 according to another example includes a wiring layer 110A-2 and a beol layer 120A-2 disposed on the wiring layer 110A-2. The wiring layer 110A- 2 includes a build-up insulating layer 111 and a build-up metal layer 112 formed on the build-up insulating layer 111 . The beol layer 120A-2 includes an insulating layer 121 and a metal layer 122 formed on the insulating layer 121. If necessary, a first passivation layer 141 disposed on the wiring layer 110A-2 and having a plurality of openings exposing at least a portion of the lowermost build-up metal layer 112, respectively, and a beol layer 120A-2 ) disposed on the second passivation layer 142 having a plurality of openings respectively exposing at least a portion of the metal layer 122 on the uppermost side, and/or formed on the plurality of openings of the first passivation layer 141, respectively. A plurality of electrical connection conductors 130 may be further included.

In this way, the package substrate 100A-2 according to another example may be a coreless type multilayer substrate, and in the case of including the beol layer 120A-2, it may be applied to the semiconductor package 500A according to the above-described example. In the case where the beol layer 120A-2 is replaced with the wiring layer 110A-2, it may be applied to the semiconductor package 500B according to another example described above.

In addition, other content, for example, content that is not contradictory among the above-described semiconductor packages 500A, 500B, and 500C and the above-described package substrate 100A-1 may also be applied to the package substrate 100A-2. , and redundant descriptions thereof are omitted.

12 is a schematic cross-sectional view of an example of an interposer substrate.

Referring to the drawing, the interposer substrate 200A-1 according to the example may be an organic interposer. For example, it may be a coreless type organic multilayer substrate. For example, the interposer substrate 200A-1 according to an example may include a wiring layer 210A-1 and a beol layer 220A-1 disposed on the wiring layer 210A-1. The wiring layer 210A-1 may include a plurality of insulating layers 211a-1 and a plurality of metal layers 212a-1. The beol layer 220A-1 may include one or more insulating layers 221a-1 and one or more metal layers 222a-1. If necessary, the first and second passivation layers 241-1 and 242-1 and a plurality of electrical connection conductors 230 may be further included.

The insulating layers 211a-1 and 221a-1 may include an organic insulating material. Examples of organic insulating materials include thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, or resins in which these resins are mixed with inorganic fillers such as silica, or resins impregnated into the core material of inorganic fillers, such as prepreg and ABF. , FR-4, BT, etc. may be used, but are not limited thereto. The number of layers of the insulating layers 211a-1 and 221a-1 is not particularly limited and may be variously changed according to design. The insulating layers 211a-1 and 221a-1 may be separated from each other or may be integral with each other to the extent that the boundaries are ambiguous.

The metal layer 212a - 1 may include power transmission wiring, signal transmission wiring, ground transmission wiring, and the like. The signal transmission wiring may include various signals, for example, data signals, excluding ground transmission wiring and power transmission wiring. Each of these wirings may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern or the like. The metal layer 212a-1 may be made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or any of these It may include a conductive material such as an alloy, specifically a metal material. The metal layer 212a - 1 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). The via pattern of the metal layer 212a-1 may have a downwardly tapered shape in cross section, but is not limited thereto.

The metal layer 222a-1 may mainly include wires for power transmission. However, if necessary, a part of signal transmission wiring and/or ground transmission wiring may be further included. Here, the wiring for power transmission may be a wiring for transmitting power to the semiconductor chip. In addition, mainly including the power transmission wiring may mean that the total area occupied by the power transmission wiring on a plane is larger than the total area occupied by the signal transmission wiring and/or the ground transmission wiring. In the case of a plurality of layers, the area of each layer on a plane can be combined and compared, and the determination can be made by excluding vias overlapping pads of each layer. Each of these wirings may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern or the like. The metal layer 222a-1 may be made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or any of these It may include a conductive material such as an alloy, specifically a metal material. The metal layer 212a - 1 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). The via pattern of the metal layer 222a-1 may have a downwardly tapered shape in cross section, but is not limited thereto.

The first and second passivation layers 241-1 and 242-1 are disposed on the outermost side of both sides of the interposer substrate 200A-1 to protect internal components. Materials of the first and second passivation layers 241-1 and 242-1 are not particularly limited. For example, an insulating material may be used, and at this time, a solder resist may be used as the insulating material. However, it is not limited thereto, and ABF or the like may be used.

The plurality of electrical connection conductors 230 may physically and/or electrically connect the interposer substrate 200A-1 to the outside. For example, the interposer substrate 200A-1 may be a BGA type substrate. The plurality of electrical connection conductors 230 may include a low melting point metal lower than copper (Cu), for example, tin (Sn) or an alloy containing tin (Sn). For example, the plurality of electrical connection conductors 230 may include solder, but this is only one example, and the material is not particularly limited thereto. The plurality of electrical connection conductors 230 may be lands, balls, pins, and the like. The plurality of electrical connection conductors 230 may be multi-layered or single-layered. When formed as a multi-layer, it may include copper pillars and solder, and when formed as a single layer, it may include solder, but again, this is only one example and is not limited thereto.

Other content, for example, content that is not contradictory among the content described in the above-described semiconductor packages 500A, 500B, and 500C may also be applied to the interposer substrate 200A-1, and redundant description thereof will be omitted. do.

13 is a schematic cross-sectional view of another example of an interposer substrate.

Referring to the drawings, an interposer substrate 200A-2 according to another example may be an inorganic interposer. For example, it may be a silicon interposer. For example, the interposer substrate 200A-2 according to another example may include a wiring layer 210a-2 and a beol layer 210a-2 disposed on the wiring layer 210a-2. The wiring layer 210A-2 may include one or more insulating layers 211a-2 and one or more metal layers 212a-2. The beol layer 220A-2 may include one or more insulating layers 221a-2 and one or more metal layers 222a-2. If necessary, the first and second passivation layers 241-2 and 242-2 and a plurality of electrical connection conductors 230 may be further included.

The insulating layers 211a-2 and 211a-2 may provide a body of the interposer substrate 200A-2. The insulating layers 211a-2 and 211a-2 may include an insulating material, and in this case, the insulating material may include silicon, more specifically, silicon dioxide. In this case, since the interposer substrate 200A-2 can be formed through a semiconductor wafer process, the metal layers 212a-2 and 222a-2 can be easily designed with high density. However, the material is not limited thereto, and other semiconductor materials may be used. The number of layers of the insulating layers 211a-2 and 211a-2 is not particularly limited and may be variously changed according to design. When the insulating layers 211a-2 and 211a-2 are multi-layered, their boundaries may be distinguished from each other and may be uncertain.

The metal layer 212a - 2 may include a signal transmission wire, a power transmission wire, a ground transmission wire, and the like. The signal transmission wiring may include various signals, for example, data signals, excluding ground transmission wiring and power transmission wiring. The metal layer 212a-2 may be made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or any of these It may include a conductive material such as an alloy, specifically a metal material. The metal layer 212a-2 may be formed by a deposition process such as chemical vapor deposition (CVD), but is not limited thereto. The number of layers of the metal layer 212a - 2 is also not particularly limited and may be changed according to design. The metal layer 212a-2 includes a via 213a for electrical connection between layers, and the via 213a may be a Through Silicon Via (TSV), but is not limited thereto.

The metal layer 222a-2 may mainly include wires for power transmission. However, if necessary, a part of signal transmission wiring and/or ground transmission wiring may be further included. Here, the wiring for power transmission may be a wiring for transmitting power to the semiconductor chip 300 . In addition, mainly including the power transmission wiring may mean that the total area occupied by the power transmission wiring on a plane is larger than the total area occupied by the signal transmission wiring and/or the ground transmission wiring. In the case of a plurality of layers, the area of each layer on a plane can be combined and compared, and the determination can be made by excluding vias overlapping the trace patterns of each layer. The metal layer 222a-2 may be made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or any of these It may include a conductive material such as an alloy, specifically a metal material. The metal layer 222a-2 may be formed by a deposition process such as CVD, but is not limited thereto. The number of layers of the metal layer 222a-2 is also not particularly limited and may be changed according to design. The metal layer 222a-2 includes vias 223a for electrical connection between layers, and the vias 223a may be TSVs, but are not limited thereto.

The first and second passivation layers 241-2 and 242-2 are disposed on the outermost side of both sides of the interposer substrate 200A-2 to protect internal components. Materials of the first and second passivation layers 241-2 and 242-2 are not particularly limited. For example, an insulating material may be used. In this case, the insulating material may include an oxide film and/or a nitride film, but is not limited thereto.

Other contents, for example, contents that do not contradict among the above-described semiconductor packages 500A, 500B, and 500C and the above-described interposer substrate 200A-1 are also applied to the interposer substrate 200A-2. It can be applied, and redundant descriptions thereof will be omitted.

14 is a cross-sectional view schematically illustrating another example of an interposer substrate.

Referring to the drawings, in the interposer substrate 200B-1 according to another example, the wiring layer is omitted in the interposer substrate 200A-1 described above, and the beol layer 220B-1 includes a plurality of insulating layers 221b-1. 1) and a plurality of metal layers 222b-1.

The insulating layer 221b-1 may include an organic insulating material. Examples of organic insulating materials include thermosetting resins such as epoxy resins, thermoplastic resins such as polyimide, or resins in which these resins are mixed with inorganic fillers such as silica, or resins impregnated into the core material of inorganic fillers, such as prepreg and ABF. , FR-4, BT, etc. may be used, but are not limited thereto. The number of layers of the insulating layers 211a-1 and 221a-1 is not particularly limited and may be variously changed according to design. The insulating layers 221b-1 may be separated from each other or may be integrated with each other to the extent that the boundaries are ambiguous.

The metal layer 222b-1 may mainly include wires for power transmission. However, if necessary, a part of signal transmission wiring and/or ground transmission wiring may be further included. Here, the wiring for power transmission may be a wiring for transmitting power to the semiconductor chip 300 . In addition, mainly including the power transmission wiring may mean that the total area occupied by the power transmission wiring on a plane is larger than the total area occupied by the signal transmission wiring and/or the ground transmission wiring. In the case of a plurality of layers, the area of each layer on a plane can be combined and compared, and the determination can be made by excluding vias overlapping pads of each layer. Each of these wirings may include a trace pattern, a via pattern, and the like. The trace pattern may include a pad pattern or the like. The metal layer 222b-1 may be made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or any of these It may include a conductive material such as an alloy, specifically a metal material. The metal layer 222b-1 may include an electroless plating layer (or chemical copper) and an electrolytic plating layer (or electrolytic copper). The via pattern of the metal layer 222b-1 may have a downwardly tapered shape in cross section, but is not limited thereto.

Other contents, for example, the contents that are not contradictory among the contents described in the above-described semiconductor packages 500A, 500B, and 500C and the above-described interposer substrates 200A-1 and 200A-2 are interposer substrates ( 200B-1), and redundant description thereof will be omitted.

15 is a cross-sectional view schematically illustrating another example of an interposer substrate.

Referring to the drawings, in the interposer substrate 200B-2 according to another example, the wiring layer is omitted in the interposer substrate 200A-2 described above, and the beol layer 220B-2 includes one or more insulating layers 221b-2. 2) and a silicon interposer including one or more metal layers 222b-2.

The insulating layer 221b-2 may provide a body of the interposer substrate 200B-2. The insulating layer 221b - 2 may include an insulating material, in which case the insulating material may include silicon, more specifically, silicon dioxide. In this case, since the interposer substrate 200B-2 can be formed through a semiconductor wafer process, the metal layer 222b-2 can be easily designed with high density. However, the material is not limited thereto, and other semiconductor materials may be used. The number of layers of the insulating layer 221b-2 is not particularly limited and may be variously changed according to design. When the insulating layer 221b-2 is multi-layered, their boundaries may be distinguished from each other and may be uncertain.

The metal layer 222b-2 may mainly include wires for power transmission. However, if necessary, a part of signal transmission wiring and/or ground transmission wiring may be further included. Here, the wiring for power transmission may be a wiring for transmitting power to the semiconductor chip 300 . In addition, mainly including the power transmission wiring may mean that the total area occupied by the power transmission wiring on a plane is larger than the total area occupied by the signal transmission wiring and/or the ground transmission wiring. In the case of a plurality of layers, the area of each layer on a plane can be combined and compared, and the determination can be made by excluding vias overlapping the trace patterns of each layer. The metal layer 222b-2 may be made of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or any of these It may include a conductive material such as an alloy, specifically a metal material. The metal layer 222b-2 may be formed by a deposition process such as CVD, but is not limited thereto. The number of layers of the metal layer 222b-2 is also not particularly limited and may be changed according to design. The metal layer 222b-2 includes vias 223b for electrical connection between layers, and the vias 223b may be TSVs, but are not limited thereto.

Other contents, for example, contents that do not contradict among the contents described in the above-mentioned semiconductor packages 500A, 500B, and 500C and the above-mentioned interposer substrates 200A-1, 200A-2, and 200B-1 It may also be applied to the interposer substrate 200B-2, and redundant description thereof will be omitted.

In the present disclosure, the meaning of cross-section may mean a cross-sectional shape when an object is vertically cut, or a cross-sectional shape when the object is viewed from a side-view. In addition, the meaning on a plane may be a shape when the object is horizontally cut, or a planar shape when the object is viewed from a top-view or bottom-view.

In the present disclosure, the lower side, the lower side, the lower side, etc. are used to mean directions toward the mounting surface of the semiconductor package including the organic interposer based on the cross-section of the drawing for convenience, and the upper side, upper side, upper surface, etc. are used in the opposite direction. did However, this is to define the direction for convenience of description, and the scope of the claims is not particularly limited by the description of this direction.

In the present disclosure, the meaning of being connected is a concept including not only being directly connected but also being indirectly connected through an adhesive layer or the like. In addition, the meaning of being electrically connected is a concept that includes both physically connected and non-connected cases. In addition, expressions such as first and second are used to distinguish one component from another, and do not limit the order and/or importance of the components. In some cases, without departing from the scope of rights, a first element may be named a second element, and similarly, a second element may be named a first element.

The expression "one example" used in the present disclosure does not mean the same embodiments, and is provided to emphasize and describe different unique characteristics. However, the examples presented above are not excluded from being implemented in combination with features of other examples. For example, even if a matter described in a specific example is not described in another example, it may be understood as a description related to another example, unless there is a description contrary to or contradictory to the matter in the other example.

Terms used in this disclosure are only used to describe an example, and are not intended to limit the disclosure. In this case, singular expressions include plural expressions unless the context clearly indicates otherwise.

1000: electronic devices
1010: motherboard
1020: chip related parts
1030: network related parts
1040: other parts
1050: camera
1060: antenna
1070: display
1080: battery
1090: signal line
1100: smartphone
1110: main board
1120: parts
1121: Part package
1130: camera module
1140: speaker
500A, 500B, 500C: semiconductor package
100A. 100B: printed circuit board (package board)
110A, 110B: wiring layer
120A: beol layer
100A-1, 100A-2: package substrate
110A-1, 110A-2: wiring layer
110A-2, 110A-2: beol layer
111a: core insulation layer
112a: core metal layer
111, 111b, 111c: build-up insulating layer
112, 112b, 112c: build-up metal layer
121: insulating layer
122: metal layer
130: electrical connecting conductor
141, 142: passivation layer
200A, 200B: printed circuit board (interposer board)
210A: wiring layer
220A, 220B: beol layer
200A-1, 200A-2, 200B-1, 200B-2: Interposer substrate
210A-1, 210A-2: wiring layer
220A-1, 220A-2, 220B-1, 220B-2: beol layer
211a-1, 211a-2, 221a-1, 221a-2, 221b-1, 221b-2: insulating layer
212a-1, 212a-2, 222a-1, 222a-2, 222b-1, 222b-2: metal layer
213a, 223a, 213b vias (TSVs)
241-1, 242-1, 241-2, 242-2: passivation layer
230: electrical connecting conductor
300, 300', 300": semiconductor chip
310, 310 ": Pheol layer
311, 312, 311", 312": semiconductor substrate
313, 313 ": lower insulating layer
314, 314": transistor element
315, 315": insulating film
316, 316": upper insulation layer
320, 320": Veol layer
321, 321": interlayer insulating layer
322, 323, 322", 323": interlayer insulating film
324, 324 ": metal layer
325, 325": protective layer
330: connection conductor
340, 340 ": sealing layer
351, 351 ": under bump metal layer
352, 352 ": surface treatment layer
370: redistribution layer
371: insulating layer
372: metal layer
1320-1, 1320-2: beol layer
M1, M2, M3, M4, M7, M8, M9: metal layer
P1: Trace pattern for first power transmission
P2: Trace pattern for second power transmission
P3: Trace pattern for signal transmission
V_P1: Via pattern for first power transmission
V_P2: Via pattern for transmitting the second power
3000: semiconductor chip
3100: Pheol layer
3110: first circuit part
3111, 3112, 3113: first transistor element
3120: second circuit part
3121, 3122, 3123: second transistor element
3200: first beol layer
3201: first wiring
1000: printed circuit board
1200: second beol layer
1201: second wiring

Claims (20)

A semiconductor chip including a Front End Of Line (FEOL) layer and a first Back End Of Line (BEOL) layer disposed on the FEOL layer; and
a printed circuit board including a wiring layer and a second beol layer disposed on the wiring layer; Including,
The semiconductor chip is mounted on the printed circuit board so that the first and second beol layers are connected to each other,
The second beol layer includes a wire for power transmission,
semiconductor package.
According to claim 1,
The power transmission wiring is a wiring for transmitting power to the semiconductor chip,
semiconductor package.
According to claim 1,
The first beol layer is disposed adjacent to the bottom side of the semiconductor chip,
The second beol layer is disposed adjacent to the top side of the printed circuit board,
semiconductor package.
According to claim 1,
The peol layer includes a first circuit part including a plurality of first transistor elements and a second circuit part including a plurality of second transistor elements,
The first and second beol layers include first and second wiring parts electrically connected to the first and second circuit parts, respectively;
The first wiring part does not include a trace pattern for power transmission interconnecting the first and second circuit parts in the first beol layer;
The second wiring part includes a trace pattern for power transmission interconnecting the first and second circuit parts in the second beol layer.
semiconductor package.
According to claim 4,
The first wiring unit includes a power transmission trace pattern interconnecting at least two of the plurality of first transistor elements and a power transmission trace interconnecting at least two of the plurality of second transistor elements in the first beol layer. It does not contain any patterns,
The second wiring unit includes a power transmission trace pattern interconnecting at least two of the plurality of first transistor elements and a power transmission trace interconnecting at least two of the plurality of second transistor elements in the second beol layer. Including patterns,
semiconductor package.
According to claim 1,
The first beol layer includes a plurality of metal layers,
Among the plurality of metal layers, a first metal layer closest to the peol layer includes a trace pattern for signal transmission, but does not include a trace pattern for power transmission.
semiconductor package.
According to claim 6,
The trace pattern for power transmission not included in the first metal layer includes at least one of a trace pattern for a positive supply voltage (VDD) and a trace pattern for a negative supply voltage (VSS).
semiconductor package.
According to claim 6,
The first metal layer includes a power transmission via pattern electrically connected to the power transmission wiring of the second beol layer.
semiconductor package.
According to claim 8,
The via pattern for power transmission included in the first metal layer includes at least one of a via pattern for a positive supply voltage (VDD) and a via pattern for a negative supply voltage (VSS).
semiconductor package.
According to claim 1,
The second beol layer includes one or more insulating layers and one or more metal layers,
The one or more insulating layers include an organic insulating material,
semiconductor package.
According to claim 1,
The semiconductor chip further includes a redistribution layer disposed on the first beol layer,
The first and second beol layers are connected to each other through the redistribution layer,
semiconductor package.
According to claim 1,
a plurality of connection conductors disposed between the printed circuit board and the semiconductor chip and connecting the printed circuit board and the semiconductor chip to each other; and
a plurality of electrical connection conductors disposed on a side opposite to a side of the printed circuit board on which the semiconductor chip is mounted, and connected to the printed circuit board; Including more,
Each of the plurality of connection conductors includes a solder bump,
Each of the plurality of electrical connection conductors includes a solder ball,
semiconductor package.
a semiconductor chip including a first beol layer;
an interposer substrate including a second beol layer; and
A package substrate including a wiring layer; Including,
The semiconductor chip is mounted on the interposer substrate,
The interposer substrate is mounted on the package substrate,
The first and second beol layers are connected to each other,
The second beol layer includes a wire for power transmission,
semiconductor package.
According to claim 13,
The interposer substrate is an organic interposer or an inorganic interposer,
The organic interposer includes a coreless type substrate,
The inorganic interposer includes a silicon interposer,
semiconductor package.
According to claim 13,
a plurality of connection conductors disposed between the semiconductor chip and the interposer substrate and connecting the semiconductor chip and the interposer substrate to each other;
a plurality of first electrical connection conductors disposed between the interposer substrate and the package substrate and connecting the interposer substrate and the package substrate to each other; and
a plurality of second electrical connection conductors disposed on a side opposite to the side of the package substrate on which the interposer substrate is disposed and connected to the package substrate; Including more,
Each of the plurality of connection conductors includes a solder bump,
The plurality of first and second electrical connection conductors each include a solder ball,
semiconductor package.
a peol layer including a plurality of circuit parts each including a plurality of transistor elements; and
a veil layer disposed on the veil layer and including a wiring portion electrically connected to the plurality of circuit portions; Including,
The wiring part does not include a trace pattern for power transmission interconnecting at least two of the plurality of circuit parts.
semiconductor chip.
17. The method of claim 16,
The wiring unit does not include a trace pattern for power transmission that interconnects at least two of the plurality of transistor elements of at least one of the plurality of circuit units.
semiconductor chip.
A pickle layer including a first circuit part including a plurality of first transistor elements and a second circuit part including a plurality of second transistor elements, and disposed on the pickol layer and electrically connected to the first and second circuit parts a semiconductor chip including a first beol layer including a first wiring part; and
a printed circuit board including a second beol layer including a second wiring part electrically connected to the first wiring part; Including,
The semiconductor chip is mounted on the printed circuit board,
The first wiring part does not include a trace pattern for power transmission interconnecting the first and second circuit parts in the first beol layer;
The second wiring part includes a trace pattern for power transmission interconnecting the first and second circuit parts in the second beol layer.
semiconductor package.
According to claim 18,
The first wiring part does not include a trace pattern for power transmission interconnecting at least two of the plurality of first transistor elements in the first beol layer;
The second wiring part also includes a trace pattern for power transmission interconnecting at least two of the plurality of first transistor elements in the second beol layer.
semiconductor package.
According to claim 18,
The first wiring part does not include a trace pattern for power transmission interconnecting at least two of the plurality of second transistor elements in the first beol layer;
The second wiring part also includes a trace pattern for power transmission interconnecting at least two of the plurality of second transistor elements in the second beol layer.
semiconductor package.

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