KR20190013134A - Electroluminescent Display Device - Google Patents

Abstract

The present invention includes an electroluminescence display device in which a plurality of pixels PXL are connected to a data line 14 to which a data voltage Vdata is supplied and a first power supply line 17 to which a high potential power supply voltage EVDD is supplied do. Each pixel PXL disposed in the nth horizontal pixel line Ln is connected to the driving TFT DT connected to the gate electrode, the source electrode, and the drain electrode at the node N2, the first power source line 17 and the node N3, ; A first switch TFT (T1) switched in accordance with the nth scan A signal (G1 (n)); A second switch TFT T2 which is switched in accordance with the n-th scan A signal G1 (n); A third switch TFT (T3) switched in accordance with the nth emission signal EM (n); A light emitting element connected between the third switch TFT (T3) and a low potential power supply voltage; And a storage capacitor Cst connected between the node N1 and the node N2.

Description

[0001] Electroluminescent Display Device [0002]

The present invention relates to an electroluminescent display device.

The electroluminescent display device is classified into an organic light emitting display device or an inorganic light emitting display device according to the type of light emitting device. Among them, the inorganic light emitting display device includes an LED display device.

The organic light emitting display includes an organic light emitting diode (OLED) that emits light by itself, and the LED display includes a self-emitting LED (Light Emitting Diode). The OLED display or the LED display arranges the pixels including the light emitting element in a specific pattern and adjusts the brightness of the pixels according to the gradation of the image data. Each of the pixels includes a driving TFT (Thin Film Transistor) for controlling the driving current flowing to the light emitting element according to the gate-source voltage, and at least one switch TFT for programming the gate-source voltage of the driving TFT, The display gradation (luminance) is adjusted by the amount of light emitted by the light emitting element proportional to the current.

Recently, interest and development of LED display devices using LEDs, which are light emitting devices including an inorganic layer, are increasing. LEDs are able to output even higher brightness grades than OLEDs and are highly reliable for heat, moisture, and oxygen. Also, the LED display device can implement a zero bezel so that the bezel can not be seen. Therefore, when a tiling display is implemented by combining a plurality of LED display devices, there is a great advantage that a boundary between display devices is not visible.

In order to realize a uniform image quality without luminance and color difference between pixels, the driving characteristic of a pixel equal to the threshold voltage (Vth) of the driving TFT must be the same in all the pixels. However, there may be variations in driving characteristics between pixels due to various causes including process variations. In addition, the deterioration progress speed between the pixels may be different according to the driving time of the display device, so that the difference in driving characteristics between the pixels may be large. Therefore, the amount of driving current flowing to the light emitting element changes depending on the driving characteristic deviation between the pixels, thereby causing unevenness in image quality.

In order to improve the image quality and lifetime of a display device, a compensation circuit for compensating a difference in driving characteristics between pixels is applied to an electroluminescence display device. The electroluminescence display device compensates the gate-source voltage of the driving TFT, which may vary depending on the electrical characteristics of the driving TFT, using a compensation circuit located in the pixel, and compensates the data voltage with the compensated voltage.

On the other hand, in driving the compensation circuit applied to the electroluminescence display device, the light emitting element can emit minute light in an unintentional period. Particularly, when the light emitting element emits light while driving the black gradation image, the characteristic of the contrast ratio can be lowered.

In the internal compensation circuit, the driving current of the light emitting element can be influenced by the high potential power supply voltage (hereinafter referred to as " EVDD ") of the pixel. In this case, if the EVDD is different according to the pixel position in the panel due to the voltage drop of the EVDD (IR drop), the driving current applied to the light emitting element is different from the current required in the pixel, and uniform image quality can not be obtained. In order to reduce the voltage drop of the EVDD, it is possible to consider increasing the line width of the EVDD wiring. However, since the pixel area of the high-resolution panel is small, it is difficult to design the reinforcement for increasing the line width.

Currently, electroluminescent display devices are being developed with high resolution, large area and high brightness trend. Therefore, the width of EVDD wiring is inevitably reduced and the EVDD wiring becomes long. Therefore, there is a limit to improve the EVDD voltage drop by the EVDD resistance reduction method have.

In the process of initializing a specific node, a specific voltage may be applied to one electrode of the light emitting node. The light emitting element can emit light in accordance with the potential level of the voltage applied to the light emitting element. In particular, since the threshold voltage at which the light emitting element starts to emit light is lower than that of the OLED, the LED display device may be more vulnerable to the contrast ratio.

Accordingly, it is an object of the present invention to provide an electroluminescent display device capable of real-time compensation of a change in driving characteristics of a pixel regardless of an EVDD voltage drop.

It is another object of the present invention to provide an electroluminescent display device having excellent contrast ratio characteristics in real time while compensating for changes in driving characteristics of a pixel irrespective of an EVDD voltage drop.

An EL display device according to the present invention is connected to a data line 14 to which a data voltage Vdata is supplied and a first power supply line 17 to which a high potential power supply voltage EVDD is supplied And a pixel PXL. The pixel PXL includes a driving TFT DT having a gate electrode, a source electrode, and a drain electrode connected to the node N2, the first power supply line and the node N3, respectively; A first switch TFT (T1) connected between the node N2 and the node N3 and switched in accordance with an n-th scan 1 signal (G1 (n)); A second switch TFT (T2) connected between the data line and a node N1 and switched in accordance with the n-th scan 1 signal (G1 (n)); A third switch TFT (T3) connected between the node N3 and the low potential power supply voltage (EVSS) and switched according to the nth emission signal EM (n); A light emitting element connected between the third switch TFT and the low potential power supply voltage; And a storage capacitor Cst connected between the node N1 and the node N2. Here, in the compensation period (3) for sampling the threshold voltage (Vth) of the driving TFT (DT), the first and second switch TFTs (T1, T2) G1 (n)), and the third switch TFT T3 is turned off according to the nth emission signal EM (n) at the off level.

Since the current applied to the light emitting device is not influenced by the EVDD, the present invention can realize a uniform image quality over the entire screen without a low resistance design of the EVDD wiring, and realize a high resolution and large-screen electroluminescent display device.

In addition, since the current applied to the light emitting device is not influenced by the threshold voltage deviation of each pixel according to the present invention, the brightness and color of the pixels can be uniformly maintained throughout the entire screen.

In addition, the present invention can control the light emitting device not to emit light during the initialization period. In particular, it has an advantage that the contrast ratio can be improved without setting the initialization voltage lower than the low potential voltage.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention.
2 is a view showing an embodiment of a light emitting device included in each pixel of an electroluminescent display device.
3 is a view illustrating a pixel array of an electroluminescent display device according to an embodiment of the present invention.
4 is a diagram showing an equivalent circuit according to an embodiment of the pixel shown in FIG.
5 is a waveform diagram showing a potential change of drive signals input to the pixel of FIG.
6A is an equivalent circuit diagram of a pixel corresponding to the first initialization period of FIG.
FIG. 6B is an equivalent circuit diagram of a pixel corresponding to the second initialization period of FIG. 5; FIG.
6C is an equivalent circuit diagram of a pixel corresponding to the compensation period of FIG.
6D is an equivalent circuit diagram of a pixel corresponding to the sustain period of FIG.
6E is an equivalent circuit diagram of a pixel corresponding to the light emission ready period of FIG.
6F is an equivalent circuit diagram of a pixel corresponding to the light emission period of FIG.
FIG. 7 is a diagram illustrating an equivalent circuit according to an embodiment of the pixel shown in FIG.
8 is a waveform diagram showing a potential change of drive signals input to the pixel of FIG.
FIG. 9A is an equivalent circuit diagram of a pixel corresponding to the first initialization period of FIG. 7; FIG.
FIG. 9B is an equivalent circuit diagram of a pixel corresponding to the second initialization period of FIG. 7; FIG.
9C is an equivalent circuit diagram of a pixel corresponding to the compensation period of FIG.
FIG. 9D is an equivalent circuit diagram of a pixel corresponding to the sustain period of FIG. 7; FIG.
FIG. 9E is an equivalent circuit diagram of a pixel corresponding to the light emission period of FIG. 7; FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. Where the terms "comprises", "having", "done", and the like are used in this specification, other portions may be added unless "only" is used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

Like reference numerals refer to like elements throughout the specification.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or wholly and technically various interlocking and driving are possible and that the embodiments may be practiced independently of each other, It is possible.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings. The component names used in the following description are selected in consideration of easiness of specification, and may be different from the parts names of actual products. Hereinafter, for convenience of explanation, the case where the electroluminescence display device is implemented as a display device including an inorganic luminescent material, for example, an LED display device will be described as an example. The technical idea of the present invention is not limited to the LED display device but can be applied to a display device including an organic light emitting material, for example, an OLED display device.

1 is a block diagram showing an electroluminescent display device according to an embodiment of the present invention. 2 is a view showing an embodiment of a light emitting device included in each pixel of an electroluminescent display device. 3 is a view illustrating a pixel array of an electroluminescent display device according to an embodiment of the present invention.

1 to 3, an electroluminescent display device according to the present invention includes a display panel 10 having pixels PXL, a display panel driving circuit 12 for driving signal lines connected to the pixels PXL, , 13), and a timing controller (11) for controlling the display panel drive circuits (12, 13).

The display panel drive circuits 12 and 13 write the input image data (DATA) to the pixels PXL of the display panel 10. [ The display panel driving circuits 12 and 13 include a source driver 12 for driving the data lines 14 connected to the pixels PXL and a gate driver 15 for driving the gate lines 15 connected to the pixels PXL. And a driver 13.

A plurality of data lines 14 and a plurality of gate lines 15 are intersected with each other in the display panel 10 and the pixels PXL are formed in a manner that the data lines 14 and the gate lines 15 intersect with each other Lt; / RTI > The pixels PXL may include a light emitting element 130 such as the LED shown in FIG.

The light emitting device 130 according to an exemplary embodiment includes a light emitting layer EL, a first electrode E1, and a second electrode E2.

The light emitting layer EL emits light according to the recombination of electrons and holes according to the current flowing between the first electrode E1 and the second electrode E2. The light emitting layer EL according to an example includes a first semiconductor layer 131, an active layer 133, and a second semiconductor layer 135.

The first semiconductor layer 131 provides electrons to the active layer 133. The first semiconductor layer 131 may be made of an n-GaN based semiconductor material, and the n-GaN based semiconductor material may be GaN, AlGaN, InGaN, or AlInGaN. Here, Si, Ge, Se, Te, or C may be used as an impurity used for doping the first semiconductor layer 131.

The active layer 133 is provided on one side of the first semiconductor layer 131. The active layer 133 has a multi quantum well (MQW) structure having a barrier layer having a higher bandgap than that of the well layer and the well layer. The active layer 133 according to an example may have a multiple quantum well structure such as InGaN / GaN.

The second semiconductor layer 135 is provided on the active layer 133 to provide holes in the active layer 133. The second semiconductor layer 135 may be made of a p-GaN semiconductor material, and the p-GaN semiconductor material may be GaN, AlGaN, InGaN, or AlInGaN. As the impurity used for doping the second semiconductor layer 135, Mg, Zn, Be, or the like may be used.

In addition, the first semiconductor layer 131, the active layer 133, and the second semiconductor layer 135 may be sequentially stacked on the semiconductor substrate. Here, the semiconductor substrate includes a semiconductor material such as a sapphire substrate or a silicon substrate. The semiconductor substrate is used as a growth substrate for growing the first semiconductor layer 131, the active layer 133, and the second semiconductor layer 135, and then the first semiconductor layer 131 is removed from the first semiconductor layer 131 Can be separated. Here, the substrate separation process may be a laser lift off or a chemical lift off. The light emitting device 130 from which the substrate is separated is placed on each pixel PXL and connected to the pixel circuit.

The first electrode (E1) is provided on the second semiconductor layer (135). The second electrode E2 may be provided on the other side of the first semiconductor layer 131 so as to be electrically separated from the active layer 133 and the second semiconductor layer 135. [ Each of the first and second electrodes E1 and E2 may be made of a transparent conductive material, and the transparent conductive material may be made of a material such as indium tin oxide (ITO) or indium zinc oxide (IZO) , But is not limited thereto. Each of the first and second electrodes E1 and E2 according to another example includes at least one of a metal material such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, ≪ / RTI >

The light emitting device 130 emits light according to the recombination of electrons and holes according to the current flowing between the first electrode E1 and the second electrode E2. At this time, light emitted from the light emitting device 130 passes through each of the first and second electrodes E1 and E2 and is emitted to the outside to display an image. The first electrode E1 of the light emitting device 130 may be represented by an anode electrode, and the second electrode E2 may be represented by a cathode electrode.

As shown in FIG. 3, the pixel array of the display panel 10 includes a plurality of horizontal pixel lines L 1 to L 4 and horizontally neighboring gate lines L 1 to L 4 on the horizontal pixel lines L 1 to L 4. A plurality of pixels PXL connected in common to the pixels 15a, 15b, 15c are arranged. Here, each of the horizontal pixel lines L1 to L4 is not a physical signal line but a pixel block of one line amount which is implemented by horizontally neighboring pixels PXL. The pixel array includes a first power supply line 17 for supplying a high potential supply voltage EVDD to the pixels PXL and a second power supply line 16 for supplying the initialization voltage Vinit to the pixels PXL . Further, the pixels PXL may be connected to the low potential power supply voltage EVSS.

Each of the gate lines 15 shown in FIG. 3 includes a first gate line 15a to which a first scan signal G1 is supplied, a second gate line 15b to which a second scan signal G2 is supplied, And a third gate line 15c to which the emission signal EM is supplied. The gate line may be further configured to include a fourth gate line to which another emission signal EM2 is supplied.

Each of the pixels PXL may be any one of a red pixel, a green pixel, a blue pixel, and a white pixel for various color implementations. The red pixel, the green pixel, the blue pixel, and the white pixel may constitute one unit pixel. The color implemented in the unit pixel may be determined according to the emission ratio of the red pixel, the green pixel, the blue pixel, and the white pixel. Each of the pixels PXL may be connected to at least one of the plurality of gate lines and one of the data line 14, the first power source line 17, and the second power source line 16.

The source driver 12 converts the input video data DATA received from the timing controller 11 every frame into a data voltage Vdata and supplies the data voltage Vdata to the data lines 14 . The source driver 12 outputs the data voltage Vdata using a digital to analog converter that converts the input image data DATA to a gamma compensation voltage.

The source driver 12 generates the initialization voltage Vinit and supplies it to the second power supply line 16 to generate and supply the high potential supply voltage EVDD to the first power supply line 17. [ To this end, the source driver 12 may further include a power generator (not shown). The power generation section may further generate the low potential power supply voltage EVSS. The power generator may be electrically connected to the source driver via a conductive film or the like after being mounted outside the source driver 12.

The gate driver 13 may be formed directly on the substrate of the display panel 10 together with the pixel array in a gate-driver In Panel (GIP) process, but is not limited thereto. The gate driver 13 may be manufactured in an IC type and then bonded to the display panel 10 through a conductive film.

The timing controller 11 receives digital data (DATA) of an input image from a host system (not shown) and a timing signal synchronized with the digital data (DATA). The timing signal includes a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE. The host system may be any one of a TV (Television) system, a set-top box, a navigation system, a DVD player, a personal computer (PC), and a phone system.

The timing controller 11 multiplies the input frame frequency by i times and controls the operation timing of the display panel driving circuits 12 and 13 at a frame frequency of the input frame frequency x i (i is a positive integer larger than 0) Hz have. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the PAL (Phase-Alternating Line) system.

The timing controller 11 generates a data timing control signal DDC for controlling the operation timing of the source driver 12 based on the timing signals Vsync, Hsync and DE received from the host system, And generates a gate timing control signal GDC for controlling the operation timing.

4 is a diagram showing an equivalent circuit according to an embodiment of the pixel shown in FIG.

Referring to FIG. 4, the pixel PXL of the present invention includes a light emitting device 130, a plurality of thin film transistors (TFTs) T1 through T6, and a storage capacitor Cst. The TFTs T1 to T6 and DT may be implemented as PMOS (P-type metal oxide semiconductor) TFTs, thereby achieving desired response characteristics. However, the technical idea of the present invention is not limited thereto. For example, at least one TFT among the switch TFTs T1 to T6 is implemented as an NMOS type (N-channel metal oxide semiconductor) TFT having an excellent off-current characteristic, The TFTs may be implemented as PMOS type LTPS TFTs with good response characteristics.

Hereinafter, a connection configuration of one pixel PXL arranged on the nth horizontal pixel line will be described in detail.

The light emitting element 130 emits light with an amount of current adjusted in accordance with the gate-source voltage of the driving TFT DT. The anode electrode of the light emitting element 130 is connected to the drain electrode of the fourth switch TFT T4 and the cathode electrode of the light emitting element 130 is connected to the low potential power supply voltage EVSS.

The driving TFT DT is a driving element for adjusting the current flowing in the light emitting element in accordance with the gate-source voltage Vgs. The driving TFT DT includes a gate electrode connected to the node N2, a source electrode connected to the first power supply line 17, and a drain electrode connected to the node N3.

The first switch TFT T1 is connected between the node N2 and the node N3 and is switched according to the n-th scan B signal G2 (n). The gate electrode of the first switch TFT T1 is connected to the nth second gate line 15b (n) to which the nth scan B signal G2 (n) is applied, and the source of the first switch TFT T1 The electrode is connected to the node N3, and the drain electrode of the first switch TFT (T1) is connected to the node N2.

The second switch TFT T2 is connected between the data line 14 and the node N1 and is switched in accordance with the nth scan A signal G1 (n). The gate electrode of the second switch TFT T2 is connected to the nth first gate line 15a (n) to which the nth scan A signal G1 (n) is applied, and the source of the second switch TFT T2 The electrode is connected to the data line 14, and the drain electrode of the second switch TFT T2 is connected to the node N1.

The third switch TFT T3 is connected between the node N3 and the node N4 and is switched in accordance with the nth emission A signal EM1 (n). The gate electrode of the third switch TFT T3 is connected to the nth third gate line 15c (n) to which the nth emission A signal EM1 (n) is applied, and the gate electrode of the third switch TFT T3 The source electrode is connected to the node N3, and the drain electrode of the third switch TFT (T3) is connected to the node N4.

The fourth switch TFT T4 is connected between the node N4 and the light emitting element 130 and is switched in accordance with the nth emission B signal EM2 (n). The gate electrode of the fourth switch TFT T4 is connected to the nth fourth gate line 15d (n) to which the nth emission B signal EM2 (n) is applied, and the gate electrode of the fourth switch TFT T4 is connected to the n- The source electrode is connected to the node N4 and the drain electrode of the fourth switch TFT T3 is connected to the anode electrode of the light emitting element 130. [ On the other hand, the nth fourth gate line 15d (n) to which the nth emission signal B (EM2 (n)) is applied is divided into nm (m is an integer of 1 or more) third gate line 15d Or may be directly connected to the gate driver 13.

The fifth switch TFT T5 is connected between the node N1 and the second power supply line 16 and is switched in accordance with the nth emission A signal EM1 (n). The gate electrode of the fifth switch TFT T5 is connected to the nth third gate line 15c (n) to which the nth emission A signal EM1 (n) is applied, and the gate electrode of the fifth switch TFT T5 is connected to the n- The source electrode is connected to the node N1, and the drain electrode of the fifth switch TFT (T5) is connected to the second power supply line 16.

The sixth switch TFT T6 is connected between the node N4 and the second power supply line 16 and is switched in accordance with the n-th scan B signal G2 (n). The gate electrode of the sixth switch TFT T6 is connected to the nth second gate line 15b (n) to which the nth scan B signal G2 (n) is applied and the source of the sixth switch TFT T6 The electrode is connected to the node N4, and the drain electrode of the sixth switch TFT (T6) is connected to the second power supply line 16.

The storage capacitor Cst is connected between the node N1 and the node N2.

5 is a waveform diagram showing a potential change of drive signals input to the pixel of FIG. 6A to 6F are equivalent circuit diagrams of pixels corresponding to the first initialization period, the second initialization period, the compensation period, the sustain period, the light emission ready period, and the light emission period, respectively, of FIG.

Referring to FIG. 5, each pixel PXL disposed on the nth horizontal pixel line Ln is divided into a first initializing period (1), a second initializing period (2), a compensating period (3) (4), the light emission ready interval (5), and the light emission interval (6).

5 and 6A, in the first initialization period (1), the nth scan A signal G1 (n), the nth scan B signal G2 (n), and the nth emission B signal EM2 (n) is input to the off level (OFF), and the nth emission A signal EM1 (n) is input to the on level (ON).

The third switch TFT T3 and the fifth switch TFT T5 are turned on in response to the nth emission A signal EM1 (n) of the on level (ON) during the first initialization period (1). The initializing voltage Vinit is applied to the node N1 by the turn-on of the fifth switch TFT (T5). At this time, the third switch TFT T3 is turned on for stable operation of the second initialization period (2) after the first initialization period (1). The node N1 of the first initializing period (1) keeps the initializing voltage (Vinit) charged in the light emitting period (6) which is the immediately preceding period.

In response to the off-level n-th scan A signal G1 (n) and the n-th scan B signal G2 (n) during the first initialization period (1) 2 switch TFT (T2), and the sixth switch TFT (T6) are turned off. And the fourth switch TFT T4 is turned off in response to the n-emission B signal EM2 (n) of the OFF level (OFF).

The initialization voltage Vinit is a voltage lower than the high potential supply voltage EVDD and may be set to a voltage higher than the low potential supply voltage EVSS. The gate-source voltage Vgs of the driving TFT DT is smaller than the threshold voltage Vth of the driving TFT DT during the first initializing period (1), so that the driving TFT DT satisfies the turn-on condition. Therefore, during the first initialization period (1), the node N3 receives the high-potential power supply voltage from the driving TFT DT and receives the initialization voltage Vinit from the third switch TFT T3. Therefore, the node N3 can be set to a voltage higher than the initialization voltage (Vinit). However, in Table 1, for convenience of explanation, it is indicated that the potential of the immediately preceding section is maintained. On the other hand, the fourth switch TFT T4 is maintained in the turned off state during the first initialization period (1). Therefore, the light emitting device 130 is previously cut off so as not to emit light by the voltage applied to the node N3 or the node N4 during the first initialization period (1).

The potential of the initialization voltage Vinit may be set to be low so that the light emitting device 130 can not emit light due to the initialization voltage Vinit applied to the anode electrode of the light emitting device 130. [ However, referring to Equation 1, as the potential of the initialization voltage Vinit is lower than the data voltage Vdata, the driving current I of the light emitting device 130 becomes larger, It becomes difficult. However, the compensation circuit according to an embodiment of the present invention can prevent the light emitting device 130 from being turned on by the initialization voltage Vinit. Accordingly, by applying the compensation circuit according to an embodiment of the present invention, the black gradation can be driven more efficiently.

Referring to Table 1, the potential of the node N1 becomes the initializing voltage (Vinit) during the first initialization period (1), and the potential of the node N2, the node N3, and the node N4 becomes the voltage ≪ / RTI >

5 and 6B, the n-th scan A signal G1 (n) and the n-th emission B signal EM2 (n) are input at OFF level in the second initialization period (2) The nth scan B signal G2 (n) and the nth emission A signal EM1 (n) are inputted to the ON level (ON).

In response to the n-th scan B signal G2 (n) and the n-th emission A signal EM1 (n) of the on level (ON) during the second initialization period (2) The third switch TFT T3, the fifth switch TFT T5, and the sixth switch TFT T6 are turned on. A current path from the second power supply line 16 to the node N2 is formed by the turn-on of the first switch TFT (T1), the third switch TFT (T3), and the sixth switch TFT (T6). Thus, the node N2, the node N3, and the node N4 are charged with the initializing voltage Vinit. The node N1 is maintained at the initialization voltage Vinit in the second initialization period (2) following the first initialization period (1) by the fifth switch TFT (T5).

Referring to FIG. 5, the first initialization interval (1) and the second initialization interval (2) are distinguished, but the present invention is not limited thereto. The first initialization period (1) may be omitted. For example, the second initialization period (2) shown in FIG. 5 may be followed by the light emission period (6) of the previous frame.

Referring to FIGS. 5 and 6C, the n-th scan A signal G1 (n) and the n-th scan B signal G2 (n) are input to the on level (ON) The emission A signal EM1 (n) and the nth emission B signal EM2 (n) are inputted at the off level (OFF).

The first switch TFT T1 is turned on in response to the n-th scan B signal G2 (n) of the ON level ON during the compensation period (3). The gate electrode and the drain electrode of the drive TFT DT are short-circuited by the turn-on of the first switch TFT (T1), and the drive TFT DT is diode-connected. The threshold voltage Vth of the driving TFT DT is compensated by the diode connection of the driving TFT DT and the potentials of the nodes N2 and N3 become " EVDD + Vth ".

The second switch TFT T2 is turned on and the data voltage Vdata of the data line 14 is turned on in response to the nth scan A signal G1 (n) of the on level ON during the compensation period (3) And is applied to the node N1.

The third switch TFT T3 and the fourth switch TFT T3 in response to the n-emission A signal EM1 (n) and the nth emission B signal EM2 (n) of the off level (OFF) during the compensation period (3) The switch TFT T4, and the fifth switch TFT T5 are turned off.

Referring to Table 1, during the compensation period (3), the potential of the node N1 becomes the data voltage (Vdata), the potentials of the nodes N2 and N3 become " EVDD + Vth ", and the potential of the node N4 becomes the initialization voltage Vinit ).

Referring to FIG. 5 and FIG. 6D, an nth scan A signal G1 (n), an nth scan B signal G2 (n), an nth emission A signal EM1 (n) ) And the n th emission B signal EM2 (n) are inputted at the off level (OFF).

Therefore, the first to sixth switch TFTs T1 to T6 are turned off during the light emission ready period (4). The node N1 and the node N2 are changed to the floating state during the light emission ready period (4), but are maintained at the potential in the previous stage by the storage capacitor Cst. That is, the potential of the node N1 is maintained at the data voltage (Vdata), and the potential of the node N2 is maintained at " EVDD + Vth ". Other nodes except for node N1 and node N2 may be somewhat discharged from the voltage of the previous stage, but in Table 1, it is indicated that the voltage of the previous stage is maintained for convenience of explanation.

On the other hand, it is preferable to determine the length of the sustain period (4) so that the potential of the node N4 can be discharged to a voltage sufficiently lower than the initialization voltage (Vinit). Thus, it is possible to prevent the light emitting device 130 from emitting light during the consecutive light emitting ready period (5) after the sustain period (4).

5 and 6E, the n-emission B signal EM2 (n) is input to the on level (ON) during the light emission ready period (5), and the nth scan A signal G1 The nth scan B signal G2 (n), and the nth emission A signal EM1 (n) are inputted at the off level (OFF).

The fourth switch TFT T4 is turned on in response to the n-emission B signal EM2 (n) of the on level (ON) during the light emission ready period (5). The light emission ready period (5) is different from the operation period of the fourth switch TFT (T4) in comparison with the previous sustain period (4), and the remaining TFTs maintain the same operation state. The fourth switch TFT T4 is controlled to be turned on prior to the start of the light emitting period ⑥ so that the light emitting device 130 can emit light stably during the light emitting period ⑥.

The light emitting standby period (5) may be omitted, for example, the light emitting period (6) may be continued after the light emitting ready period (5).

5 and 6F, the n-emission A signal EM1 (n) and the n-emission B signal EM2 (n) are input to the ON level (ON) during the light emission period (6) The nth scan 1 signal G1 (n) and the nth scan 2 signal G2 (n) are input to the off level (OFF).

In response to the n-emission A signal EM1 (n) and the nth emission B signal EM2 (n) of the on level (ON) during the light emission period (6) The switch TFT T4, and the fifth switch TFT T5 are turned on. The first switch TFT T1 and the second switch TFT T2 are turned on in response to the off-level nth scan A signal G1 (n) and the nth scan B signal G2 (n) And the sixth switch TFT (T6) are turned off.

During the light emission period (6), the fifth switch TFT (T5) is turned on and the potential of the node N1 falls to the initializing voltage (Vinit).

During the light emission period (6), the node N2 becomes a floating state and is coupled to the node N1 through the storage capacitor Cst. Therefore, " Vdata-Vinit " which is the potential change of the node N1 during the light emission period (6) is reflected to the node N2. As a result, the potential of the node N2 is lowered by "Vdata-Vinit" in comparison with "EVDD + Vth" in the immediately preceding light emission preparation period (⑤) during the light emission period (⑥) &Quot; EVDD + Vth - Vdata + Vinit ". Meanwhile, the potentials of the nodes N3 and N4 during the light emission period (6) are proportional to the data voltage (Vdata) and may be varied depending on the device characteristics of the driving TFT (DT).

Thus, the gate-source voltage Vgs of the driving TFT DT for determining the amount of driving current of the light emitting element 130 is set. At this time, the driving current I as shown in Equation (1) below flows through the light emitting element 130.

[Equation 1]

Here, K is a constant value determined by the mobility of the driving TFT DT, the channel ratio, the parasitic capacitance, and the like, and Vth is the threshold voltage of the driving TFT DT.

The driving current I of the light emitting element 130 is not influenced by not only the threshold voltage Vth of the driving TFT DT but also the high potential power supply voltage EVDD. Since the driving current I of the light emitting device 130 is not influenced by the high potential power supply voltage EVDD, the embodiment of the present invention can be applied to the first power supply line 17 ) Can be made uniform in the luminance and color tone of the entire screen without forming a mesh shape. Further, the embodiment of the present invention can solve the problem of the light leakage without setting the potential of the initialization voltage (Vinit) lower than the low potential power supply voltage (EVSS). Thus, the present invention is very advantageous for realizing a uniform image quality in a high-resolution panel having a small pixel size. Further, the present invention is effective in providing a large-sized panel having improved luminance and image quality.

① ② ③ ④ ⑤ ⑥ N1 Vinit Vinit Vdata Vdata maintain Vinit N2 maintain Vinit EVDD + Vth EVDD + Vth maintain EVDD + Vth-Vdata + Vinit N3 maintain Vinit EVDD + Vth maintain maintain N4 maintain Vinit Vinit maintain maintain

7 is a diagram showing an equivalent circuit according to an embodiment of the pixel shown in FIG.

Referring to FIG. 7, the pixel PXL of the present invention includes a light emitting device 130, a plurality of TFTs (Thin Film Transistors) T1, T2, T3, T5, T6, DT, and a storage capacitor Cst . The TFTs T1, T2, T3, T5, T6, and DT can be implemented as a PMOS type TFT, thereby achieving desired response characteristics. However, the technical idea of the present invention is not limited thereto. For example, at least one TFT among the switch TFTs T1, T2, T3, T5, and T6 is implemented as an NMOS type TFT having good off-current characteristics, and the remaining TFTs are implemented as a PMOS type LTPS TFT having good response characteristics It is possible.

Hereinafter, a connection configuration of one pixel PXL arranged on the nth horizontal pixel line will be described in detail.

The light emitting element 130 emits light with an amount of current adjusted in accordance with the gate-source voltage of the driving TFT DT. The anode electrode of the light emitting element 130 is connected to the drain electrode of the third switch TFT T3 and the cathode electrode of the LED is connected to the low potential power supply voltage EVSS.

The driving TFT DT is a driving element for adjusting a current flowing in the light emitting element 130 according to the gate-source voltage Vgs. The driving TFT DT includes a gate electrode connected to the node N2, a source electrode connected to the first power supply line 17, and a drain electrode connected to the node N3.

The first switch TFT T1 is connected between the node N2 and the node N3 and is switched according to the nth scan A signal G1 (n). The gate electrode of the first switch TFT T1 is connected to the nth first gate line 15a (n) to which the nth scan A signal G1 (n) is applied, and the source of the first switch TFT T1 The electrode is connected to the node N3, and the drain electrode of the first switch TFT (T1) is connected to the node N2.

The second switch TFT T2 is connected between the data line 14 and the node N1 and is switched in accordance with the nth scan A signal G1 (n). The gate electrode of the second switch TFT T2 is connected to the nth first gate line 15a (n) to which the nth scan A signal G1 (n) is applied, and the source of the second switch TFT T2 The electrode is connected to the data line 14, and the drain electrode of the second switch TFT T2 is connected to the node N1.

The third switch TFT T3 is connected between the node N3 and the anode electrode of the light emitting element 130 and is switched in accordance with the nth emission signal EM (n). The gate electrode of the third switch TFT T3 is connected to the nth third gate line 15c (n) to which the nth emission signal EM (n) is applied, and the source of the third switch TFT T3 The electrode is connected to the node N3, and the drain electrode of the third switch TFT (T3) is connected to the anode electrode of the light emitting element 130. [

The fourth switch TFT T6 is connected between the node N1 and the second power supply line 16 and is switched in accordance with the nth emission signal EM (n). The gate electrode of the fourth switch TFT T6 is connected to the nth third gate line 15c (n) to which the nth emission signal EM (n) is applied, and the source of the fourth switch TFT T6 The electrode is connected to the node N1, and the drain electrode of the fourth switch TFT (T6) is connected to the second power supply line 16. [

The fifth switch TFT T5 is connected between the node N3 and the second power supply line 16 and is switched in accordance with the n-th scan B signal G2 (n). The gate electrode of the fifth switch TFT T5 is connected to the nth second gate line 15b (n) to which the nth scan B signal G2 (n) is applied and the source of the fifth switch TFT T5 The electrode is connected to the node N3 in common with the source electrode of the third switch TFT T3 and the drain electrode of the fifth switch TFT T5 is connected to the second power supply line 16. [

The storage capacitor Cst is connected between the node N1 and the node N2.

8 is a waveform diagram showing a potential change of drive signals input to the pixel of FIG. 9A to 9E are equivalent circuit diagrams of pixels corresponding to the first initialization period, the second initialization period, the compensation period, the sustain period, and the light emission period of FIG. 8, respectively.

8, each of the pixels PXL disposed on the nth horizontal pixel line Ln is divided into a first initializing period (1), a second initializing period (2), a compensating period (3) (4), and a light emitting section (5).

8 and 9A, the n-th scan A signal G1 (n) is input to the OFF level (OFF) in the first initialization period (1), the n-th scan B signal G2 The nth emission signal EM (n) is input to the ON level (ON).

The third switch TFT T3 and the fourth switch TFT T6 are turned on in response to the nth emission signal EM (n) of the ON level ON during the first initialization period (1). An initializing voltage (Vinit) is applied to the node N1 by the turn-on of the fourth switch TFT (T6). At this time, the third switch TFT T3 is turned on so that the light emitting element 130 emits light after the light emitting period (⑤) of the previous frame. The potential of the node N1 during the first initializing period (1) maintains the initializing voltage (Vinit) charged in the light emitting period (5) of the previous frame by the fourth switch TFT (T6).

During the first initialization period (1), the first switch TFT (T1) and the second switch TFT (T2) are turned off in response to the nth scan A signal G1 (n) at the off level (OFF). Thus, the node N2 is in a floating state and maintains the potential in the immediately preceding state by the storage capacitor Cst.

During the first initialization period (1), the fifth switch TFT T5 is turned on in response to the n-th scan B signal G2 (n) of the on level (ON).

The initialization voltage Vinit may be set to a voltage lower than the high potential supply voltage EVDD and higher than the low potential supply voltage EVSS. During the first initialization period (1)  Since the gate-source voltage Vgs of the driving TFT DT is smaller than the threshold voltage Vth of the driving TFT DT, the driving TFT DT satisfies the turn-on condition. Therefore, during the first initialization period (1), the node N3 receives the high-potential power supply voltage from the driving TFT DT and receives the initialization voltage Vinit from the third switch TFT T3. Therefore, the node N3 can be set to a voltage higher than the initialization voltage (Vinit). However, in Table 2, for convenience of explanation, it is indicated that the potential of the immediately preceding section is maintained.

Referring to Table 2, the potential of the node N1 becomes the initializing voltage (Vinit) during the first initialization period (1), and the potentials of the nodes N2 and N3 maintain the state of the immediately preceding period.

8 and 9B, the n-th scan A signal G1 (n) and the n-th scan B signal G2 (n) are input to the on level (ON) in the second initialization period (2) The n-th emission signal EM (n) is input to the OFF level (OFF).

The first switch TFT T1 and the second switch TFT T2 are turned on in response to the nth scan A signal G1 (n) of the ON level ON during the second initialization period (2). The data voltage (Vdata) is applied to the node N1 by the second switch TFT (T2). The fifth switch TFT T5 is turned on in response to the n-th scan B signal G2 (n) at the on level (ON). Thus, a current path is formed from the second power supply line 16 to the node N2. Thus, the node N2 is charged with the initializing voltage Vinit.

The third switch TFT T3 and the fourth switch TFT T4 are turned off in response to the nth emission signal EM (n) of the off level (OFF) during the second initialization period (2). The third switch TFT T3 controls the initialization voltage Vinit of the node N3 not to be applied to the anode electrode of the light emitting element 130. In this case, That is, the third switch TFT T3 controls the light emitting element 130 having a low light emitting threshold voltage to emit light due to the initialization voltage Vinit.

Referring to Table 2, during the second initialization period (2), the potential of the node N1 becomes the data voltage (Vdata), and the potentials of the nodes N2 and N3 become the initialization voltage (Vinit).

On the other hand, the first initialization period (1) may be omitted. For example, immediately after the light emission period (5) shown in FIG. 8 (e), the second initialization period (2) shown in FIG.

8 and 9C, the nth scan A signal G1 (n) is input to the ON level (ON) in the compensation period (3), the nth scan B signal G2 (n) The emission signal EM (n) is input to the off level (OFF).

The first switch TFT T1 and the second switch TFT T2 are turned on in response to the nth scan A signal G1 (n) of the ON level ON during the compensation period (3). The gate electrode and the drain electrode of the driving TFT DT are short-circuited by the first switch TFT T1, and the driving TFT DT is diode-connected. The threshold voltage Vth of the driving TFT DT is compensated by the diode connection of the driving TFT DT and the potentials of the nodes N2 and N3 become " EVDD + Vth ". Further, the second switch TFT T2 is turned on in response to the n-th scan A signal G1 (n) at the on level (ON). Accordingly, the potential of the node N1 keeps the data voltage (Vdata) after the second initialization period (2).

The third switch TFT T3 and the fourth switch TFT T3 in response to the n-th scan B signal G2 (n) and the nth emission signal EM (n) of the off level (OFF) during the compensation period (3) The second switching TFT T6, and the fifth switching TFT T5 are turned off.

Referring to Table 2, during the compensation period (3), the potential of the node N1 becomes the data voltage (Vdata), and the potentials of the nodes N2 and N3 become " EVDD + Vth ". Then, the voltage stored in the storage capacitor Cst during the compensation period (3) becomes " EVDD + Vth - Vdata ". The threshold voltage Vth of the PMOS type TFT may be a negative voltage.

8 and 9D, the nth scan A signal G1 (n), the nth scan B signal G2 (n), and the nth emission signal EM (n (n) ) Is input as the OFF level (OFF).

The first to fifth switch TFTs T1, T2, T3, T6, and T5 are turned off in the light emission ready period (4). During the light emission ready period (4), the node N1 and the node N2 are changed to the floating state, but are maintained at the voltage of the immediately preceding state by the storage capacitor Cst. That is, the potential of the node N1 is maintained at the data voltage (Vdata), and the potential of the node N2 is maintained at " EVDD + Vth ". The potential of the node N3 can be gradually discharged, but for convenience of explanation, it is assumed that the potential in the immediately preceding section is maintained.

8 and 9E, the nth emission signal EM (n) is input to the ON level (ON) during the light emission period (5), and the nth scan 1 signal G1 (n) And the scan 2 signal G2 (n) is input to the off level (OFF).

During the light emission period (5), the third switch TFT (T3) and the fourth switch TFT (T6) are turned on in response to the nth emission signal EM (n) at the on level (ON). The first switch TFT T1 and the second switch TFT T2 are turned on in response to the off-level nth scan A signal G1 (n) and the nth scan B signal G2 (n) And the fifth switch TFT (T5) are turned off.

During the light emission period (5), the initializing voltage (Vinit) is applied to the node N1 by the fourth switch TFT (T6). Therefore, the potential of the node N1, which is held at the data voltage Vdata by the storage capacitor Cst, is lowered to the initializing voltage Vinit.

During the light emission period (5), since the node N2 is in the floating state, the potential of the node N2 is coupled to the node N1 through the storage capacitor Cst. Therefore, "Vdata-Vinit" which is the potential change of the node N1 during the light emission period (5) is reflected to the node N2. As a result, the potential of the node N2 is lowered by "Vdata-Vinit" from "EVDD + Vth" of the previous light emission preparation period (4) during the light emission period (⑤). That is, the potential of the node N2 during the light emission period (5) becomes "EVDD + Vth - Vdata + Vinit". Meanwhile, the potential of the node N3 during the light emission period (5) is proportional to the data voltage (Vdata) and may vary depending on the device characteristics of the driving TFT (DT).

Thus, the gate-source voltage Vgs of the driving TFT DT for determining the amount of driving current of the light emitting element 130 is set. At this time, the driving current I shown in the following Equation 2 flows through the light emitting device 130.

&Quot; (2) "

Here, K is a constant value determined by the mobility of the driving TFT DT, the channel ratio, the parasitic capacitance, and the like, and Vth is the threshold voltage of the driving TFT DT.

The driving current I of the light emitting element 130 is not affected by not only the threshold voltage Vth of the driving TFT DT but also the high potential power supply voltage EVDD. Since the driving current I of the light emitting device 130 is not influenced by the high potential power supply voltage EVDD, the embodiment of the present invention can be applied to the first power supply line 17 ) Can be made uniform in the luminance and color tone of the entire screen without forming a mesh shape. Further, the embodiment of the present invention can solve the problem of the light leakage without setting the potential of the initialization voltage (Vinit) lower than the low potential power supply voltage (EVSS). Thus, the present invention is very advantageous for realizing a uniform image quality in a high-resolution panel having a small pixel size. Further, the present invention is effective in providing a large-sized panel having improved luminance and image quality.

① ② ③ ④ ⑤ N1 Vinit Vdata Vdata Vdata Vinit N2 maintain Vinit EVDD + Vth EVDD + Vth EVDD + Vth-Vdata + Vinit N3 maintain Vinit EVDD + Vth EVDD + Vth

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Source driver 13: Gate driver
130: Light emitting element

Claims (21)

A pixel connected to a data line 14 to which a data voltage Vdata is supplied and a first power supply line 17 to which a high potential power supply voltage EVDD is supplied,
The pixel includes:
A driver TFT (DT) having a gate electrode, a source electrode, and a drain electrode connected to the node N2, the first power supply line and the node N3, respectively;
A first switch TFT (T1) connected between the node N2 and the node N3 and switched in accordance with an n-th scan 1 signal (G1 (n));
A second switch TFT (T2) connected between the data line and a node N1 and switched in accordance with the n-th scan 1 signal (G1 (n));
A third switch TFT (T3) connected between the node N3 and the low potential power supply voltage (EVSS) and switched according to the nth emission signal EM (n);
A light emitting element connected between the third switch TFT (T3) and the low potential power supply voltage (EVSS); And
And a storage capacitor connected between the node N1 and the node N2,
The first and second switch TFTs T1 and T2 are turned on in response to the n-th scan 1 signal G1 (n) at the on level in the compensation period (3) for sampling the threshold voltage of the drive TFT DT. , And the third switch TFT (T3) is turned off according to the nth emission signal (EM (n)) of off level. The method according to claim 1,
The pixel is further connected to a second power supply line 16 to which an initialization voltage Vinit is supplied,
The pixel includes a fifth switch TFT (T5) connected between the node N3 and the second power supply line (16) and switched in accordance with the n-th scan 2 signal (G2 (n)); And
Further comprising a fourth switch TFT (T6) connected between the node N1 and the second power supply line (16) and switched in accordance with the nth emission signal (EM (n)). The method according to claim 1,
And the third switch TFT (T3) is turned off such that the light emitting element does not emit light while the initialization voltage (Vinit) is applied to the node N2 and the node N3. 3. The method of claim 2,
In the compensation period (3)
And the third and fourth switch TFTs T3 and T6 are turned off according to the nth emission signal EM (n) at the off level. 3. The method of claim 2,
In the first initialization period (1) for initializing the node N1 prior to the compensation period (3)
And the fifth switch TFT (T5) is turned off according to the n-th scan 1 signal (G1 (n)) of the off level, and the fifth switch TFT And the third and fourth switch TFTs T3 and T6 are turned on according to the scan 2 signal G2 (n), and the third and fourth switch TFTs T3 and T6 are turned on according to the nth emission signal EM (n) Emitting display device. 6. The method of claim 5,
Wherein the light emitting element emits light according to a gate-source voltage of the driving TFT in the first initialization period (1). 3. The method of claim 2,
In the second initialization period (2) for initializing the node N2 prior to the compensation period (3)
The first and second switch TFTs T1 and T2 are turned on according to the n-th scan 1 signal G1 (n) at the on level, and the fifth switch TFT T5 is turned on according to the n-th scan 1 signal G1 And the third and fourth switch TFTs T3 and T6 are turned on according to the scan 2 signal G2 (n), and the third and fourth switch TFTs T3 and T6 are turned off according to the nth emission signal EM (n) Emitting display device. 3. The method of claim 2,
In the sustain period (4) for holding the gate voltage of the driving TFT following the compensation period (3)
And the fifth switch TFT (T5) is turned off according to the n-th scan 1 signal (G1 (n)) of the off level, and the fifth switch TFT And the third and fourth switch TFTs T3 and T6 are turned off according to the scan 2 signal G2 (n), and the third and fourth switch TFTs T3 and T6 are turned off according to the nth emission signal EM (n) Emitting display device. 3. The method of claim 2,
In the light emission period (5) for causing the light emitting element to emit light following the compensation period (3)
And the fifth switch TFT (T5) is turned off according to the n-th scan 1 signal (G1 (n)) of the off level, and the fifth switch TFT And the third and fourth switch TFTs T3 and T6 are turned off according to the scan 2 signal G2 (n), and the third and fourth switch TFTs T3 and T6 are turned off according to the nth emission signal EM (n) Emitting display device. 10. The method of claim 9,
The current flowing in the light emitting element in the light emitting period (5)
And is independent of a change in threshold voltage of the driving TFT (DT) and a change in the high-potential power supply voltage (EVDD). 10. The method of claim 9,
The current flowing in the light emitting element in the light emitting period (5)
(Vdata) and the initialization voltage (Vinit). An electroluminescent display device comprising a pixel circuit including an initialization period, a compensation period, and a light emitting period, and a light emitting element connected to the pixel circuit,
The pixel circuit includes:
A first power supply line 17 to which a high potential power supply voltage is supplied;
A data line 14 to which a data voltage is supplied;
A second power supply line (16) to which an initialization voltage is supplied;
A storage capacitor connected between nodes N1 and N2;
A driver TFT (DT) connected between the first power supply line and a node N3 for controlling a current of the node N3 according to a voltage of the node N2;
First and fifth switch TFTs (T1, T5) connected between the second power supply line (16) and the node N2 and configured to apply the initialization voltage to the node N2 during the initialization period preceding the compensation period;
And a third switch TFT (T3) connected between the node N3 and the light emitting element, for controlling the operation of the light emitting element during the initialization period,
The light emitting element is connected between the third switch TFT (T3) and the low potential power supply voltage,
And the fifth switch TFT (T5) is connected between the second power supply line (16) and the node N3. 13. The method of claim 12,
A fourth switching TFT (T6) connected between the second power supply line (16) and the node (N1) for charging the node (N1) with an initialization voltage during the initialization period preceding the compensation period; And
And a second switching TFT (T2) connected between the data line (14) and the node (N1) for charging the node (N1) with a data voltage during the compensation period after the initialization period. 14. The method of claim 13,
The first switch TFT T1 is connected between the node N2 and the node N3 and is switched according to the nth scan 1 signal G1 (n)
The second switch TFT T2 is connected between the data line 14 and the node N1 and is switched according to the n-th scan 1 signal G1 (n)
The third switch TFT T3 is connected between the node N3 and the light emitting element and is switched in accordance with the nth emission signal EM (n)
The fourth switch TFT T6 is connected between the second power supply line 16 and the node N1 and is switched in accordance with the nth emission signal EM (n)
And the fifth switch TFT (T5) is connected between the second power supply line (16) and the node N3 and switched according to the nth scan 2 signal (G2 (n)). 14. The method of claim 13,
During the initialization interval,
The first and second switch TFTs T1 and T2 are turned off according to the nth scan 1 signal G1 (n) at the turn-off level,
The third and fourth switch TFTs T3 and T6 are turned on according to the nth emission signal EM (n) at the turn-on level,
And the fifth switch TFT (T5) is turned on according to the n-th scan 2 signal (G2 (n)) at the turn-on level. 14. The method of claim 13,
During the initialization interval,
The third switch TFT T3 is turned off according to the nth emission signal EM (n) at the turn-off level,
And the fifth switch TFT (T5) is turned on according to the n-th scan 2 signal (G2 (n)) at the turn-on level. 17. The method of claim 16,
During the initialization interval,
The first and second switch TFTs T1 and T2 are turned on according to the nth scan 1 signal G1 (n) at the turn-on level,
And the fourth switch TFT (T6) is turned off according to the nth emission signal EM (n) at the turn-off level. 14. The method of claim 13,
Wherein the initialization voltage is higher than the low potential power supply voltage. 14. The method of claim 13,
During the compensation period,
The first and second switch TFTs T1 and T2 are turned on according to the nth scan 1 signal G1 (n) at the turn-on level,
The third and fourth switch TFTs T3 and T6 are turned off according to the nth emission signal EM (n) at the turn-off level,
And the fifth switch TFT (T5) is turned off according to the n-th scan 2 signal (G2 (n)) at the turn-off level. 14. The method of claim 13,
Wherein the pixel circuit further includes a sustain period between the compensation period and the light emitting period,
During the sustain period,
The first to fifth switch TFTs (T1, T2, T3, T6, T5) are all turned off, and the storage capacitor is configured to maintain the voltage in the immediately preceding state. 14. The method of claim 13,
The first and second switch TFTs T1 and T2 are turned off according to the nth scan 1 signal G1 (n) at the turn-off level,
The third and fourth switch TFTs T3 and T6 are turned on according to the nth emission signal EM (n) at the turn-on level,
And the fifth switch TFT (T5) is turned off according to the n-th scan 2 signal (G2 (n)) at the turn-off level.

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