KR20180045769A - Semiconductor memory device and method of fabricating of the same - Google Patents

Abstract

A semiconductor memory device and a manufacturing method thereof are provided. The semiconductor memory device includes a first high concentration doped region doped with a first conductivity type dopant, a second base region doped with a second conductivity type dopant, a first base region doped with the first conductivity type dopant, Terminal memory cell in which a second heavily doped region doped with a dopant of a second conductivity type is sequentially bonded, wherein a length or a doping concentration of the first base region and the second base region is adjusted, And the voltage is controlled.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device including a memory cell whose write voltage is controlled by adjusting a length of a base region and a doping concentration, .

BACKGROUND ART A semiconductor memory device is an element used for storing information, and is an apparatus that enables human memory and recording capabilities to be realized by electronic means. Semiconductor memory devices can operate easily with electricity even at low power and are useful for constructing circuits. Currently, most electronic devices such as computers and smart phones use semiconductor memories.

However, as the fourth industrial revolution such as artificial intelligence (AI) and autonomous vehicle has begun, demand for ultra-high-performance memory has exploded, and the development of semiconductor memory devices has been limited . This deteriorates the overall performance of the electronic device determined by the performance of the semiconductor memory device.

Therefore, there is a demand for techniques for improving the performance of semiconductor memory devices.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device having a controlled write voltage.

Another object of the present invention is to provide a semiconductor memory device with improved integration.

It is another object of the present invention to provide a reduced size semiconductor memory device.

It is another object of the present invention to provide a method of manufacturing a semiconductor memory device in which the manufacturing process is simplified.

It is another object of the present invention to provide a method of manufacturing a semiconductor memory device with improved process yield.

The technical problem to be solved by the present invention is not limited to the above.

According to an aspect of the present invention, there is provided a semiconductor memory device.

According to one embodiment, a semiconductor memory device includes a first high concentration doping region doped with a first conductivity type dopant, a second base region doped with a second conductivity type dopant, a second high concentration doping region doped with the first conductivity type dopant, Terminal memory cell in which a first base region and a second heavily doped region doped with the second conductivity type dopant are sequentially bonded to each other, and the length or doping concentration of the first base region and the second base region is controlled Thereby adjusting the write voltage of the memory cell.

According to an embodiment, the length of the first base region and the second base region may be increased, or the doping concentration may be increased to increase the write voltage of the memory cell.

According to one embodiment, the length of the first base region and the second base region may be reduced, or the doping concentration may be decreased, thereby reducing the write voltage of the memory cell.

According to one embodiment, a semiconductor memory device includes an array in which a plurality of the memory cells are stacked, the array including alternately and repeatedly stacking the memory cells and the insulating layer.

According to one embodiment, the memory cell included in the array includes a first memory cell and a second memory cell on the first memory cell, wherein the first base regions of the first and second memory cells The lengths are different from each other and the lengths of the second base regions of the first and second memory cells are different from each other.

According to one embodiment, the memory cell included in the array includes a first memory cell and a second memory cell on the first memory cell, wherein the first base regions of the first and second memory cells The doping concentrations may be different from each other and the doping densities of the second base regions of the first and second memory cells may be different from each other.

According to one embodiment, a semiconductor memory device includes a plurality of said arrays, a plurality of said arrays arranged laterally spaced apart, and a trench being provided between said plurality of arrays .

According to one embodiment, the plurality of arrays include a first array and a second array adjacent to each other, and the length of the first base region of the memory cells included in the first array is included in the second array The length of the first base region of the memory cell being different from the length of the first base region of the memory cell included in the first array and the length of the second base region of the memory cell included in the first array, The lengths of the regions may include different ones.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device.

According to one embodiment, a method of manufacturing a semiconductor memory device includes the steps of preparing a substrate, alternately and repeatedly laminating a semiconductor layer and an insulating film on the substrate to produce a stacked structure, Etching and defining a plurality of arrays spaced apart from each other by a trench, the semiconductor layer comprising: a first heavily doped region extending in a first direction and doped with a dopant of a first conductivity type; A first base region extending in the first direction and doped with a dopant of the first conductivity type and a second base region extending in the first direction, And a second high concentration doped region doped with a second conductivity type dopant, wherein the first high concentration doped region, the second base region, the first base region, Doped region are arranged in sequence, the trench comprises that extends in a second direction crossing the first direction.

According to one embodiment, a method of fabricating a semiconductor memory device includes a plurality of memory cells in which the arrays defined by etching the stacked structure are stacked so as to be spaced from each other, and the memory cells are sequentially stacked with the first heavily doped Wherein the first base region, the second base region, the first base region, and the second heavily doped region are adjusted in length or doping concentration of the first base region and the second base region, May be controlled.

A semiconductor memory device according to an embodiment of the present invention includes a memory cell in which a first heavily doped region, a second base region, a first base region, and a second heavily doped region are successively joined, The write voltage can be adjusted by adjusting the length of the second base region or the doping concentration. Accordingly, a semiconductor memory device including a memory cell capable of two-terminal operation and having a write voltage controlled according to an application can be provided.

The semiconductor memory device according to an embodiment of the present invention includes a stacked structure in which the memory cells are alternately and repeatedly stacked with a plurality of insulating films. A semiconductor memory device in which the memory cells are stacked apart from each other to improve the degree of integration can be provided.

1 is a view for explaining a memory cell according to an embodiment of the present invention.
2 is a cross-sectional view illustrating an array including memory cells according to an embodiment of the present invention.
3 is a cross-sectional view for explaining a modification of the array including the memory cell according to the embodiment of the present invention.
4A to 4G are views for explaining a method of manufacturing an array including memory cells according to an embodiment of the present invention.
5 is a view for explaining an array manufactured according to an embodiment of the present invention.
6 is a graph illustrating a write voltage measurement according to lengths of first and second base regions of a memory cell according to an embodiment of the present invention.
FIG. 7 is a graph of a write voltage measurement when a memory cell according to an embodiment of the present invention has first and second base regions of different lengths. FIG.
8 is a block diagram briefly showing an example of an electronic system including a semiconductor memory device based on the technical idea of the present invention.
9 is a block diagram briefly showing an example of a memory card including a semiconductor memory device based on the technical idea of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the technical spirit of the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

In this specification, when an element is referred to as being on another element, it may be directly formed on another element, or a third element may be interposed therebetween. Further, in the drawings, the thicknesses of the films and regions are exaggerated for an effective explanation of the technical content.

Also, while the terms first, second, third, etc. in the various embodiments of the present disclosure are used to describe various components, these components should not be limited by these terms. These terms have only been used to distinguish one component from another. Thus, what is referred to as a first component in any one embodiment may be referred to as a second component in another embodiment. Each embodiment described and exemplified herein also includes its complementary embodiment. Also, in this specification, 'and / or' are used to include at least one of the front and rear components.

The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It is also to be understood that the terms such as " comprises "or" having "are intended to specify the presence of stated features, integers, Should not be understood to exclude the presence or addition of one or more other elements, elements, or combinations thereof.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

1 is a view for explaining a memory cell according to an embodiment of the present invention.

1, a memory cell includes a structure in which a first heavily doped region 120, a second base region 130, a first base region 140, and a second heavily doped region 150 are sequentially stacked can do.

The first heavily doped region 120 is doped with a dopant of the first conductivity type at a high concentration. According to one embodiment, the first conductivity type dopant may be a P type dopant, and the first heavily doped region 120 may be a P + region.

The second base region 130 is doped with a dopant of a second conductivity type. According to one embodiment, the second conductivity type dopant may be an N type dopant, and the second base region 130 may be an N base region.

The first base region 140 is doped with the first conductivity type dopant and doped with a lower concentration than the first heavily doped region 120. According to one embodiment, the first conductivity type dopant may be the P type dopant, and the first base region 140 may be a P base region.

The second heavily doped region 150 is heavily doped with the dopant of the second conductivity type and doped at a higher concentration than the second base region 130. According to one embodiment, the dopant of the second conductivity type may be the N type dopant, and the second heavily doped region 150 may be an N + region.

The first base region 140 and the second heavily doped region 150 may be formed of a material selected from the group consisting of Si As shown in FIG.

According to another embodiment, in the memory cell, the first heavily doped region 120, the first base region 140, and the second heavily doped region 150 are formed of Si, (130) may be formed of SiGe or Ge.

According to another embodiment, the memory cell may be formed such that the first heavily doped region 120, the second base region 130, and the second heavily doped region 150 are formed of silicon, Region 140 may be formed of SiGe or Ge.

When a forward voltage is applied to both ends of the memory cell, a junction J ₁ between the first heavily doped region 120 and the second base region 130, a junction J ₁ between the first base region 140 and the second high concentration A forward voltage is applied to the junction J ₃ between the doped regions 150 and a reverse voltage is applied to the junction J ₂ between the second base region 130 and the first base region 140.

When a voltage is applied to the memory cell and a punch-through occurs in the second base region 130 or the first base region 140, the holes and electrons injected into the memory cell drastically increase . When a sufficient number of holes and electrons are accumulated in the memory cell, a junction J ₂ between the second base region 130 and the first base region 140 is changed from a reverse bias state to a forward bias state So that current can flow through the memory cell.

According to one embodiment, the length A of the second base region 130 and the length B of the first base region 140 may be adjusted to control the write voltage of the memory cell. For example, when the length A of the second base region 130 and the length B of the first base region 140 increase, the write voltage of the memory cell may increase. In another example, when the length A of the second base region 130 and the length B of the first base region 140 decrease, the write voltage of the memory cell may decrease.

According to one embodiment, the doping concentration of the second base region 130 and the first base region 140 may be adjusted to control the write voltage of the memory cell.

For example, when the doping concentration of the second base region 130 and the first base region 140 increases, the write voltage of the memory cell may increase. Specifically, when the doping concentration of the second base region 130 and the first base region 140 increases, the width of the depletion region of the second base region 130 and the first base region 140 (x _p1 , x _p2 , x _n1 , x _n2 ) decreases. It may not be easy to cause a punch-through in the junction (J ₂ ) between the second base region 130 and the first base region 140 where the reverse voltage is applied. Accordingly, the write voltage of the memory cell may increase.

In another example, if the doping concentration of the second base region 130 and the first base region 140 decreases, the write voltage of the memory cell may decrease. Specifically, when the doping concentration of the second base region 130 and the first base region 140 decreases, the width of the depletion region of the second base region 130 and the first base region 140 (x _p1 , x _p2 , x _n1 , x _n2 ) increases. Punch-through can be facilitated in the junction (J ₂ ) between the second base region 130 and the first base region 140 where the reverse voltage is applied. Accordingly, the write voltage of the memory cell can be reduced.

The memory cell according to an embodiment of the present invention includes the first base region 140 and the second base region 130 and the length of the first base region 140 and the second base region 130 (A, B) and the doping concentration of the memory cell.

2 is a cross-sectional view illustrating an array including memory cells according to an embodiment of the present invention.

2, the array includes a substrate 110, a plurality of memory cells, and a plurality of insulating films 160, and the memory cells and the insulating film 160 are alternately and repeatedly And may be a stacked structure.

The substrate 110 is provided as a support on which the memory cell and the insulating film 160 are stacked. According to one embodiment, the substrate 110 may be a silicon semiconductor substrate.

The memory cell has a structure in which a first heavily doped region 120, a second base region 130, a first base region 140, and a second heavily doped region 150 are sequentially stacked. And the like. A plurality of the memory cells are stacked on the substrate 110. According to an embodiment, the first base regions 140 and the second base regions 130 included in the plurality of memory cells have a length And the doping concentration may be the same.

A plurality of the insulating films 160 may be stacked on the substrate 110 and may be alternately stacked on the substrate 110 with the memory cells. According to one embodiment, the insulating layer 160 may be silicon oxide, silicon nitride, or silicon oxynitride.

3 is a cross-sectional view for explaining a modification of the array including the memory cell according to the embodiment of the present invention.

3, the array includes a substrate 110, a plurality of memory cells, and a plurality of insulating films 160, on which the memory cells and the insulating film 160 are alternately and repeatedly Or may be a laminated laminated structure.

The substrate 110 may be provided as described above with reference to FIG. 2 as a support on which the memory cell and the insulating film 160 are stacked.

The memory cell has a structure in which a first heavily doped region 120, a second base region 130, a first base region 140, and a second heavily doped region 150 are sequentially stacked. And the like. A plurality of the memory cells are stacked on the substrate 110. According to an embodiment, the first base regions 140 and the second base regions 130 included in the plurality of memory cells have a length And the doping concentration may be different from each other.

For example, the array may include a first memory cell and a second memory cell, wherein the first base region 140 of the first memory cell is formed to extend from the first base region 140 of the second memory cell The length can be long or short. Also, the second base region 130 of the first memory cell may be longer or shorter than the second base region 130 of the second memory cell. Accordingly, the first memory cell and the second memory cell may have different write voltages. In other words, by adjusting the lengths of the first and second base regions 140 and 130 of the memory cells included in one array, the memory cells included in one array are adjusted to have different write voltages Thus, a semiconductor memory device applicable to various applications can be provided.

In another example, the array includes a first memory cell and a second memory cell, wherein the first base region 140 of the first memory cell is connected to the first base region 140 of the second memory cell, The doping concentration may be higher or lower. Also, the second base region 130 of the first memory cell may have a higher or lower doping concentration than the second base region 130 of the second memory cell. In other words, by adjusting the lengths of the first and second base regions 140 and 130 of the memory cells included in one array, the memory cells included in one array are adjusted to have different write voltages Thus, a semiconductor memory device applicable to various applications can be provided.

A plurality of the insulating films 160 may be stacked on the substrate 110 and may be alternately stacked on the substrate 110 with the memory cells. According to one embodiment, the insulating layer 160 may be provided in the same manner as described above with reference to FIG.

FIGS. 4A to 4G are views for explaining a method of manufacturing an array including memory cells according to an embodiment of the present invention, and FIG. 5 is a view for explaining an array manufactured according to an embodiment of the present invention.

Referring to FIG. 4A, a substrate 110 is prepared. A laminated structure in which a plurality of memory cells and a plurality of insulating films are alternately and repeatedly stacked on the substrate 110 may be provided. According to one embodiment, the substrate 110 may be provided as described above in Fig.

Referring to FIG. 4B, a first semiconductor layer is disposed on the substrate 110. The first semiconductor layer includes a first high concentration doped region 120a, a second base region 130a, a first base region 140a, and a second high concentration doped region 150a sequentially grown in a first direction Structure, it can be provided in the same manner as described above in Fig. 1 to Fig.

4B, the first heavily doped region 120a, the second base region 130a, the first base region 140a, and the second heavily doped region 150a are formed in the first direction , And can have a constant width. Referring to FIG. 5, when a trench is generated, the first high concentration doped region 120a, the second base region 130a, the first base region 140a, and the second high concentration The width of the doped region 150a is larger than the width of the first heavily doped region 120a, the second base region 130a, the first base region 140a, (150a). In other words, by controlling the widths of the second base region 130a and the first base region 140a of the first semiconductor layer, the second base region 130a of the semiconductor layer of the memory cell, The length of one base region 140a can be adjusted, and consequently, the write voltage of the memory cell can be adjusted.

Referring to FIG. 4C, a first insulating layer 160a is disposed on the first semiconductor layer. The first insulating layer 160a may be provided in the same manner as described above with reference to FIG.

Referring to FIG. 4D, a second semiconductor layer is disposed on the first insulating layer 160a. The second semiconductor layer may include a first high concentration doped region 120b, a second base region 130b, a first base region 140b, and a second high concentration doped region 150b sequentially extending in a first direction Structure, it can be provided in the same manner as described above in Fig. 1 to Fig.

According to one embodiment, the first base region 140b and the second base region 130b included in the second semiconductor layer are formed in the first base region 140a and the second base region 130b, 2 base region 130a may have the same length or doping concentration.

According to another embodiment, the first base region 140b and the second base region 130b included in the second semiconductor layer are formed in the first base region 140a and the second base region 130b, 2 base region 130a may differ in length or doping concentration.

Referring to FIG. 4E, a second insulating layer 160b is disposed on the second semiconductor layer. The second insulating film 160b may be provided in the same manner as described above with reference to FIG.

Referring to FIG. 4F, a third semiconductor layer is disposed on the second insulating layer 160b. The third semiconductor layer may include a first heavily doped region 120c, a second base region 130c, a first base region 140c, and a second heavily doped region 150c sequentially extending in a first direction Structure, it can be provided in the same manner as described above in Fig. 1 to Fig.

According to an embodiment, the first base region 140c and the second base region 130c included in the third semiconductor layer may include the first base region 140a and the second base region 140b, The first base region 140b and the second base region 130b included in the second base region 130a or the second semiconductor layer may have the same length or doping concentration.

According to another embodiment, the first base region 140c and the second base region 130c included in the third semiconductor layer may include the first base region 140a and the second base region 140b, The first base region 140b and the second base region 130b included in the second base region 130a or the second semiconductor layer may have different lengths or doping densities.

Referring to FIG. 4G, a third insulating layer 160c is disposed on the third semiconductor layer. The third insulating film 160c may be provided in the same manner as described above with reference to FIG.

5, the laminated structure in which the first to third semiconductor layers and the first to third insulating films 160a, 160b, and 160c are alternately stacked on the substrate 110 is etched to form a plurality of A trench can be formed between the arrays.

Specifically, the first heavily doped regions 120a, 120b, and 120c, the second base regions 130a, 130b, and 130c, and the first base regions 140a and 140b And 140c and the second heavily doped regions 150a, 150b, and 150c extend in the first direction, and the trenches extend in a second direction that intersects the first direction.

A semiconductor memory device in which a plurality of the arrays are laterally spaced apart and a trench is provided between a plurality of the arrays can be manufactured by gap-filling the trenches with an insulating material.

In FIG. 4B, the first heavily doped region 120a, the second base region 130a, the first base region 140a, and the second heavily doped region 150a have a constant width in the first direction According to one modification, in the semiconductor layer, the widths of the first heavily doped region 120a and the second heavily doped region 150a are gradually widened, or gradually increased, Can be narrowed. In this case, in the semiconductor layer, the widths of the second base region 130a and the first base region 140a may gradually become narrower or wider, respectively. Accordingly, when the array is manufactured by the method described with reference to Figs. 4C to 4G and Fig. 5, in the arrays adjacent to each other, in the first base region and the second base region of the memory cells located at the same level The widths may be different from each other, so that a semiconductor memory element having a different writing voltage for each array can be manufactured.

6 is a graph illustrating a write voltage measurement according to lengths of first and second base regions of a memory cell according to an embodiment of the present invention.

Referring to FIG. 6, the write voltage changes of the memory cells having different lengths of the first base region and the second base region were measured.

When a voltage was applied to a memory cell having a length of 200 nm in the first base region and the second base region, the write voltage of the memory cell was measured to be 0.77 V. When a voltage was applied to a memory cell having a length of 250 nm in the first base region and the second base region, the write voltage of the memory cell was measured to be 1.85 V. When a voltage was applied to a memory cell having a length of 300 nm in the first base region and a second base region, the write voltage of the memory cell was measured to be 3.40 V.

In this manner, the lengths of the first base region and the second base region can be adjusted to adjust the write voltage of the memory cell.

FIG. 7 is a graph of a write voltage measurement when a memory cell according to an embodiment of the present invention has first and second base regions of different lengths. FIG.

Referring to FIG. 7, when a voltage is applied to a memory cell having a length of 200 nm in the first and second base regions, the write voltage of the memory cell is measured to be 0.66V. When the length of the first base region is reduced to 150 nm and the length of the second base region is 200 nm, which is the same as the memory cell, the write voltage of the memory cell is measured to be 0.36 V, It can be confirmed that the write voltage of the memory cell is decreased with decreasing the length.

In this manner, the lengths of the first base region and the second base region can be adjusted to adjust the write voltage of the memory cell.

The semiconductor memory device according to the embodiments of the present invention described above can be implemented in various types of semiconductor packages. For example, the semiconductor memory device according to the embodiments of the present invention can be used in a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package -Level Processed Stack Package (WSP) or the like. The package on which the semiconductor memory device according to the embodiments of the present invention is mounted may further include a controller and / or a logic element for controlling the same.

8 is a block diagram briefly showing an example of an electronic system including a semiconductor memory device based on the technical idea of the present invention.

8, an electronic system 1100 according to an embodiment of the present invention includes a controller 1110, an input / output device 1120, a memory device 1130, an interface 1140, and a bus 1150, bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via the bus 1150. The bus 1150 corresponds to a path through which data is moved.

The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The memory device 1130 may include at least one of the semiconductor memory devices disclosed in the embodiments of the present invention described above. Further, the storage device 1130 may further include other types of semiconductor memory devices (ex, a DRAM device and / or an SRAM device, etc.).

The interface 1140 may perform functions to transmit data to or receive data from the communication network. The interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver. Although not shown, the electronic system 1100 is an operation memory for improving the operation of the controller 1110, and may further include a high-speed DRAM and / or an esram.

The electronic system 1100 may be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a digital music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

9 is a block diagram briefly showing an example of a memory card including a semiconductor memory device based on the technical idea of the present invention.

Referring to FIG. 9, a memory card 1200 according to an embodiment of the present invention includes a storage device 1210. The memory device 1210 may include at least one of the semiconductor memory devices disclosed in the embodiments of the present invention described above. Further, the storage device 1210 may further include other types of semiconductor memory devices (ex, a DRAM device and / or an SRAM device, etc.). The memory card 1200 may include a memory controller 1220 that controls the exchange of data between the host and the storage device 1210.

The memory controller 1220 may include a processing unit 1222 that controls the overall operation of the memory card. In addition, the memory controller 1220 may include an SRAM 1221, which is used as an operation memory of the processing unit 1222. In addition, the memory controller 1220 may further include a host interface 1223 and a memory interface 1225.

The host interface 1223 may include a data exchange protocol between the memory card 1200 and a host. The memory interface 1225 can connect the memory controller 1220 and the storage device 1210. Further, the memory controller 1220 may further include an error correction block 1224 (Ecc).

The error correction block 1224 can detect and correct errors in data read from the storage device 1210. [ Although not shown, the memory card 1200 may further include a ROM device for storing code data for interfacing with a host. The memory card 1200 may be used as a portable data storage card. Alternatively, the memory card 1200 may be implemented as a solid state disk (SSD) capable of replacing a hard disk of a computer system.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the scope of the present invention is not limited to the disclosed exemplary embodiments. It will also be appreciated that many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention.

110: substrate
120: first high concentration doped region
130: second base region
140: first base region
150: second heavily doped region
160: Insulating film
1100: Electronic system
1110: Controller
1120: Input / output device (I / O)
1130, 1210: Storage device
1140: Interface
1150: bus
1200: Memory card
1220: Memory controller
1221: Slam
1222: Processing unit
1223: Host interface
1224: Error correction block (Ecc)
1225: Memory interface
A: length of the second base region
B: length of the first base region
J ₁ , J ₂ , J ₃ : Junction
x _n1 , x _n2 , x _p1 , x _p2 : width of the depletion region

Claims (10)

A second base region doped with a second conductivity type dopant, a first base region doped with the first conductivity type dopant, and a second base region doped with the first conductivity type dopant, In a two-terminal memory cell in which second high-concentration doped regions doped with a dopant are sequentially bonded,
Wherein a length or a doping concentration of the first base region and the second base region is adjusted to adjust a write voltage of the memory cell.
The method according to claim 1,
Wherein a write voltage of the memory cell is increased when the lengths of the first base region and the second base region are increased or the doping concentration is increased.
The method according to claim 1,
Wherein a write voltage of the memory cell is reduced when the length of the first base region and the second base region is decreased or the doping concentration is reduced.
The method according to claim 1,
Wherein the array comprises an array of a plurality of memory cells stacked, the array comprising alternately and repeatedly stacking the memory cells and an insulating layer.
5. The method of claim 4,
Wherein the memory cell included in the array includes a first memory cell and a second memory cell on the first memory cell,
Wherein lengths of the first base regions of the first and second memory cells are different from each other,
Wherein the lengths of the second base regions of the first and second memory cells are different from each other.
5. The method of claim 4,
Wherein the memory cell included in the array includes a first memory cell and a second memory cell on the first memory cell,
Wherein the doping densities of the first base regions of the first and second memory cells are different from each other,
Wherein the doping concentrations of the second base regions of the first and second memory cells are different from each other.
5. The method of claim 4,
The array is provided in a plurality,
A plurality of said arrays are arranged laterally spaced apart and a trench is provided between said plurality of said arrays.
8. The method of claim 7,
The plurality of arrays include a first array and a second array adjacent to each other,
The length of the first base region of the memory cells included in the first array is different from the length of the first base region of the memory cells included in the second array,
Wherein a length of the second base region of the memory cell included in the first array and a length of the second base region of the memory cell included in the second array are different.
Preparing a substrate;
Depositing a semiconductor layer and an insulating film alternately and repeatedly on the substrate to produce a stacked structure;
Etching the stack to define a plurality of arrays spaced apart from each other by trenches,
Wherein:
A first heavily doped region extending in a first direction and doped with a dopant of a first conductivity type, a second base region extending in the first direction and doped with a dopant of a second conductivity type, A first base region doped with a dopant of a first conductivity type and a second heavily doped region extending in the first direction and doped with a dopant of the second conductivity type,
Wherein the first heavily doped region, the second base region, the first base region, and the second heavily doped region are sequentially arranged,
Wherein the trench extends in a second direction that intersects the first direction.
10. The method of claim 9,
Wherein the array defined by etching the stacked structure includes a plurality of memory cells stacked and isolated from each other,
Wherein the memory cell includes the first heavily doped region, the second base region, the first base region, and the second heavily doped region that are sequentially bonded,
Wherein a length or a doping concentration of the first base region and the second base region is adjusted to adjust the write voltage of the memory cell.

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