KR20180012351A - Vertical Atomic Transistor and Method of the same - Google Patents

Abstract

Disclosed are a vertical atomic transistor having a new diffusion wall layer in a transistor and an operating method thereof. An ion channel layer of a resistance change feature is introduced so that a multi-level cell of the transistor can be realized, wherein the multi-level cell of the transistor can store more information without increasing the number of memory cells. In addition, the ion channel layer is manufactured in a vertical structure to drastically increase an integration degree of the transistor.

Description

Vertical Atomic Transistor and Method of Operation

Field of the Invention The present invention relates to vertical atomic transistors, and more particularly to vertical atomic transistors having memory characteristics using conductive bridges and methods of operation thereof.

Recently, due to the development of digital information communication and household appliances industries, there is an increasing demand for low power and high integration devices. However, it is known that power consumption and high integration of devices based on existing charge control have reached a limit. In order to overcome these limitations, new memory devices using phase change and magnetic field change of organic or inorganic materials have been actively studied. Such an information storage method of memory devices uses a principle of changing a resistance of a material by inducing a change of a material state. For example, the next generation non-volatile memory devices include phase-change RAM (PRAM), magnetic RAM (MRAM), and resistance change RAM (ReRAM).

In the case of a flash memory, which is a typical element of a nonvolatile memory, a high operating voltage is required for programming and erasing data. Therefore, when scale-down is performed with a line width of 45 nm or less, a malfunction may occur due to interference between adjacent cells, and slow operation speed and excessive power consumption are problematic.

Magnetic RAM (MRAM) with nonvolatile memory characteristics, which is proposed as an alternative to solve this problem, requires more research for commercialization due to complicated manufacturing process, multi-layer structure, and small margin of read / write operation . Therefore, development of a next-generation non-volatile memory device that overcomes the disadvantages of these devices and has low power, high integration, and low manufacturing process ratio is an indispensable research field.

In the case of a conventional transistor, it is composed of a 3-terminal of a source electrode, a drain electrode and a gate electrode, and operates the element using the principle of controlling the carrier concentration of silicon. That is, it is an element that can control the magnitude of the resistance between the source electrode and the drain electrode by adjusting the voltage of the gate electrode. These transistors have the feature that the stored logic disappears at the same time when the power is turned off. In order to use the transistor as a computing element, a memory portion for storing the memory must be separately disposed. As a result, data is stored between the memory and the arithmetic device, a bottleneck occurs in the process of loading, and the speed of the transistor is lowered. In addition, since the horizontal channel is used, there is a limitation in improving the integration degree.

Also, as with the flash memory device, attempts have been made to implement a multi-level cell capable of storing more information even for the next generation non-volatile memory devices without increasing the number of memory cells. However, There are very few devices doing this.

The US patent application US13 / 871,040 (filed on March 26, 2013) relates to a conductive bridge resistor memory and describes a method for manufacturing a programmable metallization cell (PMC) for a resistor S / W in a nonvolatile memory . In order to improve the performance of the device by reducing the leakage current by suppressing the electric field value in the cell operation and suppressing the occurrence of defects in the high electric field, a semiconductor layer is provided between the memory layer and the ion supply layer to suppress the leakage current It is a structure that can be. The basic structure is a two-electrode structure, and the leakage current decreases due to the semiconductor layer. However, the increase in resistance of the resistance variable layer including the semiconductor layer lowers the reliability of the nonvolatile memory characteristics in the repeated operation.

US 13/347840 (filed on January 12, 2012), which is a US patent application, is a nonvolatile, resistive memory cell with an active layer, wherein the active material is between the first electrode and the second electrode of the metal or metal silicide, A two-electrode structure made of a structure in which a barrier exists between one electrode and the active material, and is a conductive bridging random access memory (CBRAM). There is a similar aspect in terms of a two-electrode structure in which a conductive bridge is formed by the movement of ions in the active layer to perform a nonvolatile memory function and a dielectric layer is disposed on one side of the active layer to prevent ion diffusion. The position of the dielectric layer is not in contact with the ion source layer.

 Japanese Patent Application No. 2012-42825 (filed on Feb. 29, 2012) relates to a storage device capable of advancing miniaturization while maintaining good thermal insulation of a device. A storage device comprising a first electrode, a storage layer, and a second electrode, in which a heat insulating layer is provided in a sidewall of the storage layer, and a transistor (MOSFET) for controlling the first electrode is provided. In other words, a nonvolatile memory element having a two-electrode structure is controlled by a transistor, which makes it difficult to fabricate an element, and it is difficult to reduce the cost.

Recently, a conductive bridge memory (CBM) device has been studied as one of the components of ReRAM devices. The CBM device has a function of oxidizing metal atoms or metal ions permeated from the metal electrode into the resistance variable layer The metal filament is formed and disappears by the reduction reaction, and the resistance state is changed. Solid oxide materials such as oxides or GeS are mainly used for the resistance variable layer materials that have been used so far. However, oxide-based solid electrolyte materials are very unstable in low-resistance state, high-resistance state, scattering characteristics of SET and RESET voltage, and device control is very difficult. Therefore, it is necessary to propose a new structure that can always be stable in the development of a new material for a resistance variable layer or repeated device control.

A first problem to be solved by the present invention is to form a conductive bridge by introducing a selective diffusion barrier capable of selectively blocking the diffusion of ions according to the voltage of the ion source gate electrode, Which can suppress the occurrence of fatigue of an ion channel layer of a conductive bridge, thereby increasing the reliability of the device, stably maintaining the concentration of ions in the conductive bridge, and greatly increasing the degree of integration in device fabrication.

A second object of the present invention is to provide a method of operating a vertical atomic transistor provided through the achievement of the first object.

A first problem to be solved by the present invention is to provide a semiconductor device having a substrate, a drain electrode formed on the substrate, an ion channel layer formed on the drain electrode and arranged perpendicularly to the plane of the substrate, 1 diffusion barrier layer, an ion source gate electrode formed in contact with an outer surface of the first diffusion barrier layer, a second diffusion barrier layer formed on the ion channel layer, and a source electrode formed on the second diffusion barrier layer. Is an atomic transistor.

And a first oxide layer formed between the ion source gate electrode and the substrate to separate the drain electrode from the ion source gate electrode.

The first oxide layer is CuInS, CuInSe, CuInS, CdInSe, MnInS, MnZnInS, ZnInSe, InS, InSSe, InSe, CdS, ZnCdS, ZnInS, a-Si, SiO 2, Al 2 O 3, crystalline SiO _2, determined castle Al ₂ O _3, CuS, and may have at least one selected from the group consisting of metal oxide.

Wherein the first oxide layer is a vertical atomic transistor formed below the first diffusion barrier layer and in contact with a lower region of the ion channel layer in contact with the first diffusion barrier layer.

And the first oxide layer is a vertical atomic transistor that completely shields the side surface of the drain electrode.

And an upper portion of the first oxide layer is a vertical atomic transistor which is in contact with a side surface of a part of the ion channel layer above the drain electrode.

And a vertical atomic transistor formed on the side of the second diffusion barrier layer above the first oxide layer and further including a second oxide layer for shielding a part of the ion channel layer.

The second oxide layer is CuInS, CuInSe, CuInS, CdInSe, MnInS, MnZnInS, ZnInSe, InS, InSSe, InSe, CdS, ZnCdS, ZnInS, a-Si, SiO 2, Al 2 O 3, crystalline SiO _2, determined castle Al ₂ O _3, CuS, and may have at least one selected from the group consisting of metal oxide.

A surface oxide layer is further formed between the substrate and the drain electrode to achieve electrical insulation between the substrate and the drain electrode, and the surface oxide layer is formed of SiO ₂ , Al ₂ O ₃ , ZrO ₂ , TaO ₂ , TiO ₂ , BaTiO _2, HfO _2, and may have at least one selected from the group consisting of Cu ₂ O.

The drain electrode may have at least one selected from the group consisting of p-doped Si, n-doped Si, WN, AlN, TaN, HfN, TiN, titanium oxynitride, and tungsten oxynitride (WON).

The ion channel layer CuInS, CuInSe, CuInS, CdInSe, MnInS, MnZnInS, ZnInSe, InS, InSSe, InSe, CdS, ZnCdS, ZnInS, a-Si, SiO 2, Al 2 O 3, crystalline SiO _2, crystalline Al ₂ O ₃ , CuS, and a metal oxide.

The first diffusion barrier layer or the second diffusion barrier layer may have at least one selected from the group consisting of WN, AlN, TaN, HfN, GaN, SiN x and Si ₃ N _4.

The ion source gate electrode may have at least one selected from the group consisting of Cu, Ag, Cu alloy, and Ag alloy.

The source electrode may have at least one selected from the group consisting of Cu, Ag, Cu alloy, and Ag alloy.

A second problem to be solved by the present invention is to provide a semiconductor device having an ion channel layer formed in a direction perpendicular to a surface of a substrate, a source electrode and a drain electrode formed on upper and lower portions of the ion channel layer, The method comprising the steps of: applying an overvoltage to the source electrode, moving ions from the source electrode to the ion channel layer by the overvoltage, and separating the ions from the source electrode and the drain electrode Forming a conductive bridge, having a steady current flow between the source electrode and the drain electrode with an overvoltage of the source electrode being a steady voltage, applying a voltage to the ion source gate electrode to remove the steady current flow Thereby forming a conductive bridge in the center of the ion channel layer Removing the conductive bridge by moving the ionic layer on the first diffusion barrier layer and removing the steady current flow between the source electrode and the drain electrode. .

And a second diffusion barrier layer formed on the first diffusion barrier layer by applying a reverse voltage to the ion source gate electrode to form a steady current flow after the steady current flow is removed between the source electrode and the drain electrode Forming a conductive bridge by moving the ion layer to the center of the ion channel layer, and having the steady current flow between the source electrode and the drain electrode.

After removing the conductive bridge by applying a voltage to the ion source gate electrode to remove the steady current flow to move the ions formed at the center of the ion channel layer onto the first diffusion barrier layer, Maintaining the state of the ion layer formed on the first diffusion preventing layer in a state of being blocked and not supplied and maintaining the state in which the steady current flow is blocked between the source electrode and the drain electrode when power is supplied And a method of operating the vertical atomic transistor.

Forming a conductive bridge between the source electrode and the drain electrode by applying a reverse voltage to the ion source gate electrode to move the ions on the first diffusion barrier layer to the center of the ion channel, The step of maintaining the state of the ionic layer forming the conductive bridge in a state in which electric power is cut off and not supplied, and And the steady state current flow occurs between the source electrode and the drain electrode when power is supplied.

Wherein the step of applying a voltage to the ion source gate electrode is an operation method of a vertical atomic transistor that applies the voltage stepwise to adjust the movement amount of the ions in the ion channel layer.

In the present invention, by introducing a diffusion barrier layer between the ion source gate electrode and the ion channel layer, the ion concentration for forming the conductive bridge in the ion channel layer is stably maintained in accordance with the voltage of the gate electrode, It is effective.

Also, since the ion concentration in the channel region is controlled by using the electric field, and the ion migration does not occur in the state where the power supply is interrupted, the nonvolatile memory characteristic of the transistor can be realized.

In addition, even when the power supply is cut off, the memory function of the transistor makes it possible to design a computer capable of processing computation and memory at one time, and it can be applied to a neuromotion computer and next generation computing.

Further, in the conventional memory, since the length of the channel is shortened as the device size is reduced, the operation of the memory becomes impossible. However, since the transistor of the present invention has operating characteristics due to the conductive bridge formed of ions, It is possible to scaling down the transistor up to the atomic unit.

In addition, since the transistor is formed in a vertical structure, the width of the ion channel layer can be shortened, and the integration degree of the device can be remarkably increased.

The technical effects of the present invention are not limited to those mentioned above, and other technical effects not mentioned can be clearly understood by those skilled in the art from the following description.

1 is a cross-sectional view of a vertical atomic transistor having a first diffusion barrier layer, a second diffusion barrier layer, and a vertically structured ion channel layer according to an embodiment of the present invention.
FIG. 2 is a process diagram of a fabrication sequence of a vertical atomic transistor according to an embodiment of the present invention.
3 is a process diagram for fabricating a structure for isolating a drain electrode and an ion source gate electrode on a substrate using a surface oxide layer according to an embodiment of the present invention.
4 is a flowchart illustrating a process of operating a vertical atomic transistor according to a voltage of an ion source gate electrode according to an embodiment of the present invention.
5 is a graph illustrating a change in current value between a source electrode and a drain electrode according to a voltage of an ion source gate electrode according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. Rather, the intention is not to limit the invention to the particular forms disclosed, but rather, the invention includes all modifications, equivalents and substitutions that are consistent with the spirit of the invention as defined by the claims.

It will be appreciated that when an element such as a layer, region or substrate is referred to as being present on another element "on," it may be directly on the other element or there may be an intermediate element in between .

Although the terms first, second, etc. may be used to describe various elements, components, regions, layers and / or regions, such elements, components, regions, layers and / And should not be limited by these terms.

A vertical atomic transistor according to an embodiment of the present invention will be described.

A vertical atomic transistor according to an embodiment of the present invention includes a first diffusion barrier layer 130 between an ion channel layer 160 and an ion source gate electrode 140, Ion movement can be limited. The first diffusion barrier layer 130 may be a metal nitride based or a metal oxynitride based.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view of a vertical atomic transistor having a first diffusion barrier layer 150, a second diffusion barrier layer, and a vertical structure of an ion channel layer 160 according to an embodiment of the present invention.

Referring to FIG. 1, a surface oxide layer 120 is disposed on a substrate 110, and a first oxide layer 130 and a drain electrode 165 are disposed on the surface oxide layer 120. An ion channel layer 160 is formed on the drain electrode. The ion channel layer is vertically disposed on the plane of the substrate 110. The first diffusion barrier layer 150 is disposed on the side of the ion channel layer 160 and the ion source gate electrode 140 is formed on the outer surface of the first diffusion barrier layer 150, A second diffusion barrier layer 175 and a source electrode 170 are formed.

The substrate 110 may be at least one selected from the group consisting of Si, Al ₂ O ₃ , SiC, Si ₃ N ₄ , GaAs, and GaN. In addition, the substrate 110 may be formed on the surface oxide layer 120 formed on the surface of the oxide layer include SiO _2, Al ₂ O _3, which is selected from crystalline SiO ₂ and the crystallinity of the group consisting of Al ₂ O ₃ single And a general metal material may be used as the substrate 110. [

In place of the first oxide layer 130 formed on the substrate 110, the ion channel layer 160 may be replaced with the ion channel layer forming film 220 disclosed in FIG.

The source electrode 170 may be made of Cu ₂ S, CuTeS, Ag, CuTeGe, AgSe, CuTeSi or Ag ₂ S, and a material such as Cu ₂ S, CuTeS or Ag ₂ S may be formed by a chemical vapor deposition Cu, CuTe and Ag materials can be used by sulphidation.

The drain electrode 165 may be at least one selected from the group consisting of p-doped Si, n-doped Si, WN, AlN, TaN, HfN, TiN, titanium oxynitride, and tungsten oxynitride (WON).

The spacing distance between the source electrode 130 and the drain electrode 120 is determined by the height of the ion channel layer 160 and the height of the ion channel layer 160 is in the range of 2 to 30 nm. .

In particular, when the width of the ion channel layer 160 is 1 nm or more, normal operation of the transistor is possible, but it is preferably manufactured in the range of 5 to 100 nm, but is not limited thereto.

The material of the ion channel layer 160 is CuInS, CuInSe, CuInS, CdInSe, MnInS, MnZnInS, ZnInSe, InS, InSSe, InSe, CdS, ZnCdS, ZnInS, a-Si, SiO 2, Al 2 O 3, crystalline SiO ₂ , crystalline Al ₂ O ₃ , CuS, and a metal oxide.

Cu ₂ S, CuTeS, and Ag ₂ S can be used as the ion source gate electrode 160, and Cu, CuTe, and Ag materials can be used by sulfidation using a CVD (chemical vapor deposition) method or the like.

The ion source gate electrode 140 may be at least one selected from the group consisting of Cu, Ag, Cu alloy, and Ag alloy. The material of the ion source gate electrode 140 is a metal that can move metal ions due to an electric field due to a high diffusion coefficient in a solid.

In particular, when an alloy such as AgNi or CuAg is used as the material of the ion source gate electrode 140, over-injection of ions from the ion source gate electrode 140 is prevented in repetitive driving of the transistor, .

The thickness of the ion source gate electrode 140 may be 1 nm or more, preferably 5 nm to 100 nm. However, the present invention is not limited thereto.

A first diffusion barrier layer 150 may be at least one selected from the group consisting of WN, AlN, TaN, HfN, GaN, SiN x and Si ₃ N _4.

Also, the thickness of the first diffusion barrier layer 150 may be selected in the range of 0.4 to 5 nm, but is not limited thereto.

The first diffusion barrier layer 150 is a material having a nitride-based conductive property and suppresses the generation of fatigue in the ion channel layer 160 by the repetitive operation of the vertical atom transistor, thereby improving the stability of the vertical atom transistor . However, if the thickness of the first diffusion barrier layer 150 becomes too thin, the function of the first diffusion barrier layer 150 may be lost.

2 is a detailed process diagram of a fabrication sequence of a vertical atomic transistor according to an embodiment of the present invention.

Referring to FIG. 2, in step S1, a drain electrode 165 is formed on the substrate 110 through a process of depositing and patterning a metal material. The material of the drain electrode is the same as that described in Fig.

In step S2, the ion channel layer forming film 220 is formed on the drain electrode 165. [ The ion channel layer forming film 220 is formed into an ion channel layer 160 in a subsequent step.

Subsequently, in step S3, an etching mask is formed on the ion channel layer forming film 220. The etch mask is a patterned photoresist through a conventional photolithography process. An etching mask is formed in a specific region on the ion channel layer forming film 220. Also, the etch mask may be a hard mask, and SiN _x may be used as the hard mask.

In step S4, the ion channel layer 160 is formed by etching the structure having the etching mask 230 formed thereon. In addition, the residual ion channel layer forming film 220 other than the ion channel layer 160 is removed through etching, and the portion to serve as the first oxide layer 130 remains.

In step S5, the first diffusion barrier layer 150 and the ion source gate electrode 140 are coated on the entire surface of the structure formed in step S4.

Subsequently, in step S6, the first diffusion barrier layer 150 and the ion source gate electrode 140 are patterned through selective etching.

A second oxide layer 260 is formed on the ion source gate electrode 140 in step S7.

Subsequently, in step S8, the mask 230 is removed to expose the ion channel layer 160, and then a second diffusion barrier layer 175 is formed on the ion channel layer 160 through an application of an insulating material and a patterning process.

In step S9, the source electrode 270 is formed on the second diffusion barrier layer 175 through the application and patterning process of metal.

The vertical atomic transistor can be fabricated through steps S1 through S9 of FIG.

3 is a process diagram for fabricating a structure for isolating a drain electrode and an ion source gate electrode using a first oxide layer 130 according to an embodiment of the present invention.

Referring to FIG. 3, a surface oxide layer 120 is formed on the substrate 110 in step S1. Then, the drain electrode 165 is disposed on the surface oxide layer 120 through the application of a metallic material and the patterning process.

In step S2, an ion channel layer 160 and a mask 230 are formed by applying and patterning a material and an etching mask used as the ion channel layer 160 on the drain electrode 165. [

In step S3, the first oxide layer 130 is formed by applying an oxide. Then, the first diffusion barrier layer 150 and the ion source gate electrode 140 are patterned and selectively etched to complete the patterning of the first diffusion barrier layer 150 and the ion source gate electrode 140.

In step S4, an oxide is applied to form a second oxide layer 260 and the ion source gate electrode 140 is exposed.

In step S5, the mask 230 is removed and a second diffusion barrier layer 175 is formed by applying and patterning the material of the second diffusion barrier layer 175. Then, a metal material is applied and patterned to form a source electrode 170. [

The vertical atomic transistor can be fabricated through steps S1 to S5 of FIG.

Production Example 1

A vertical atomic transistor is fabricated by the structure of FIG.

Referring to FIG. 2, a surface oxide layer 120 is disposed on a substrate 110, a first oxide layer 130 and a drain electrode 165 are disposed on the surface oxide layer 120, Ion channel layer 160 is formed.

The first diffusion barrier layer 150 is disposed on the side of the ion channel layer 160 and the ion source gate electrode 140 is formed on the side surface of the first diffusion barrier layer 150. A second diffusion barrier layer 175 and a source electrode 170 are formed on the ion channel layer 160. And a second oxide layer 260 for insulating the source electrode 170 from the ion source gate electrode 140.

A silicon wafer is used as the substrate 110, and the surface oxide layer 120 is formed of silicon dioxide (SiO ₂ ) on the substrate 110.

The material of the drain electrode 165 is TaN with a thickness of 20 nm and the source electrode 170 with AgCu of 20 nm.

In addition, the ion channel layer 160 is formed using CuTeS, the vertical height of the ion channel layer 160 is 30 nm, and on the drain electrode 165 when the ion channel layer 160 is formed, Leaving a 10-nm thick CuTeS layer to serve as the first oxide layer 130.

In addition, the second oxide layer 260 is formed by 20 nm of AlN, the first diffusion barrier layer 150 is formed with WN of 10 nm, the second diffusion barrier layer 175 is formed with 5 nm of WN , And the ion source gate electrode 140 forms AgCu to a thickness of 20 nm.

The electrode layer, the insulating layer, and the resistive layer are typically formed using chemical vapor deposition (CVD) or atomic layer epitaxy (ALE).

Production Example 2

Referring to FIG. 3, a vertical atomic transistor having a first oxide layer 130 formed between a drain electrode 165 and an ion source gate electrode 140 is fabricated.

SiO ₂ is formed to 100 nm on the substrate 110 and then the drain electrode 165 is formed on the substrate 110 to a thickness of 10 nm and the first oxide layer 130 is formed on the substrate 110, To form AlN 20 nm.

In addition, the ion channel layer 160 is formed by forming CuTeS with a height of 30 nm and a diameter of 10 nm, forming the first diffusion barrier layer 150 with a thickness of 10 nm and a width of 10 nm using WN, The barrier layer 150 is formed to surround and surround the outer surface of the ion channel layer 160. The ion source gate electrode 140 is then formed to surround the side of the first diffusion barrier layer 150 and formed using AgCu.

The second oxide layer 130 is formed to have a thickness of 20 nm and the second diffusion barrier layer 175 has a thickness of 10 nm. The source electrode 170 is formed of AgCu in a thickness of 10 nm .

Evaluation example 1

Evaluation using vertical atomic transistors manufactured in Production Example 1 and Production Example 2 shows the following operation characteristics.

FIG. 4 is a flowchart illustrating an operation of a vertical atomic transistor according to a voltage of an ion source gate electrode 140 according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 4, in step S1, an overvoltage is applied to the source electrode 170 in an initial state, so that the ions of the source electrode 170 pass through the second diffusion barrier layer 175. Then, the ions move into the ion channel layer 160 to form the conductive bridge 410.

Then, in step S2, since a conductive bridge of ions is formed, a current can flow from the source electrode 170 to the drain electrode 165, and this state is referred to as a forming state.

The ions in the central portion of the portion of the ion channel layer 160 forming the conductive bridge 410 are applied to the first diffusion barrier layer 150 . The current flowing from the source electrode 170 to the drain electrode 165 is cut off.

In step S4, the voltage of the ion source gate electrode 140 is applied so that the ions on the first diffusion barrier layer 150 side move to the center of the ion channel layer 160 to form the conductive bridge 410. A current flow from the source electrode 170 to the drain electrode 165 is formed.

Evaluation example 2

Evaluation using vertical atomic transistors manufactured in Production Example 1 and Production Example 2 shows the following operation characteristics.

5 is a graph illustrating a change in current value between the source electrode 170 and the drain electrode 165 according to the voltage of the ion source gate electrode 140 according to an embodiment of the present invention.

Referring to FIG. 5, as the voltage of the ion source gate electrode 140 increases, the current increases from the source electrode 170 to the drain electrode 165 in the first direction. As the voltage of the ion source gate electrode 140 decreases, a current is maintained from the source electrode 170 to the drain electrode 165 in the second direction.

When the voltage of the ion source gate electrode 140 is swept in the negative direction, hysteresis is maintained in a state of maintaining a low resistance. When the voltage of the ion source gate electrode 140 is further reduced, And the resistance rises sharply.

When the voltage of the ion source gate electrode 140 is increased in the fourth direction, the current value between the source electrode 170 and the drain electrode 165 is maintained at zero, When the voltage increases from zero again, the current value between the source electrode 170 and the drain electrode 165 increases.

Further, when the voltage is swept to 1 V and the voltage of the ion source gate electrode 140 is reduced along the direction 5 (green line), the initial decrease in the voltage of the ion source gate electrode 140 causes a low resistance state Lt; / RTI > Then, when the voltage of the ion source gate electrode 140 further decreases to reach a certain point, the current value between the source electrode 170 and the drain electrode 165 decreases rapidly, resulting in a high resistance state. The current value between the source electrode 170 and the drain electrode 165 can be varied according to the voltage value of the ion source gate electrode 140. [ The shape of the hysteresis in accordance with the voltage value of the ion source gate electrode 140 is similar.

When the voltage of the ion source gate electrode 140 is increased in the first direction and then the power is turned off, the current flow from the source electrode 170 to the drain electrode 165 is stopped. However, The inner conductive bridge 410 remains. Subsequently, when the power is supplied again, current is transferred from the source electrode 170 to the drain electrode 165 because the already formed conductive bridge is maintained without applying a voltage to the ion source gate electrode 140.

Then, the voltage of the ion source gate electrode 140 is applied to such a degree that the ion can move, in order to reduce the voltage of the ion source gate electrode 140 and return to the fifth direction while the hysteresis of the vertical atom transistor proceeds to 1 . Subsequently, when the voltage of the ion source gate electrode 140 is reduced, it is confirmed that the current movement from the source electrode 170 to the drain electrode 165 becomes zero. This changes the amount of ions forming the conductive bridge of the vertical atom transistor by adjusting the voltage of the ion source gate electrode 140, so that the current movement from the source electrode 170 to the drain electrode 165 decreases and can be zero .

It should be noted that the embodiments of the present invention disclosed in the present specification and drawings are only illustrative of specific examples for the purpose of understanding and are not intended to limit the scope of the present invention. It will be apparent to those skilled in the art that other modifications based on the technical idea of the present invention are possible in addition to the embodiments disclosed herein.

110: substrate 120: surface oxide layer
130: first oxide layer 140: ion source gate electrode
150: first diffusion barrier layer 160: ion channel layer
165: drain electrode 170: source electrode
175: second diffusion barrier layer 220: ion channel layer forming film
230: mask 260: second oxide layer
280: first diffusion barrier layer (inside) 290: ion source gate electrode thin film
410: conductive bridge

Claims (19)

Board;
A drain electrode formed on the substrate;
An ion channel layer formed on the drain electrode and disposed perpendicularly to the plane of the substrate;
A first diffusion barrier layer formed on a side surface of the ion channel layer;
An ion source gate electrode formed in contact with an outer surface of the first diffusion barrier layer;
A second diffusion barrier layer formed on the ion channel layer; And
And a source electrode formed on the second diffusion barrier layer. The method according to claim 1,
Further comprising a first oxide layer formed between the ion source gate electrode and the substrate for spacing between the drain electrode and the ion source gate electrode. 3. The method of claim 2,
The first oxide layer is CuInS, CuInSe, CuInS, CdInSe, MnInS, MnZnInS, ZnInSe, InS, InSSe, InSe, CdS, ZnCdS, ZnInS, a-Si, SiO 2, Al 2 O 3, crystalline SiO _2, determined castle Al ₂ O _3, CuS and vertical atom transistor, characterized in that at least one selected from the group consisting of metal oxide. 3. The method of claim 2,
Wherein the first oxide layer is formed below the first diffusion barrier layer and in contact with a lower region of the ion channel layer in contact with the first diffusion barrier layer. 5. The method of claim 4,
Wherein the first oxide layer completely shields the side surface of the drain electrode. 5. The method of claim 4,
Wherein an upper portion of the first oxide layer is in contact with a side surface of a portion of the ion channel layer above the drain electrode. 3. The method of claim 2,
Further comprising a second oxide layer formed on a side of the second diffusion barrier layer above the first oxide layer and shielding a portion of the ion channel layer. 8. The method of claim 7,
The second oxide layer is CuInS, CuInSe, CuInS, CdInSe, MnInS, MnZnInS, ZnInSe, InS, InSSe, InSe, CdS, ZnCdS, ZnInS, a-Si, SiO 2, Al 2 O 3, crystalline SiO _2, determined castle Al ₂ O _3, CuS and vertical atom transistor, characterized in that at least one selected from the group consisting of metal oxide. The method according to claim 1,
A surface oxide layer is further formed between the substrate and the drain electrode to achieve electrical insulation between the substrate and the drain electrode,
The surface oxide layer is _{SiO 2, Al 2 O 3,} ZrO 2, TaO 2, TiO 2, BaTiO 2, HfO 2 and a vertical transistor that atom is at least one selected from the group consisting of Cu ₂ O. The method according to claim 1,
Wherein the drain electrode is at least one selected from the group consisting of p-doped Si, n-doped Si, WN, AlN, TaN, HfN, TiN, titanium oxynitride, and tungsten oxynitride (WON) transistor. The method according to claim 1,
The ion channel layer CuInS, CuInSe, CuInS, CdInSe, MnInS, MnZnInS, ZnInSe, InS, InSSe, InSe, CdS, ZnCdS, ZnInS, a-Si, SiO 2, Al 2 O 3, crystalline SiO _2, crystalline Al ₂ O ₃ , CuS, and a metal oxide. The method according to claim 1,
The first diffusion barrier layer or the second diffusion barrier layer is a transistor, characterized in that at least one selected from the group consisting of WN, AlN, TaN, HfN, GaN, SiN x and Si ₃ N _4. The method according to claim 1,
Wherein the ion source gate electrode is at least one selected from the group consisting of Cu, Ag, Cu alloy, and Ag alloy. The method according to claim 1,
Wherein the source electrode is at least one selected from the group consisting of Cu, Ag, Cu alloy, and Ag alloy. An operation method of a vertical atom transistor having an ion channel layer formed in a direction perpendicular to a surface of a substrate, a source electrode and a drain electrode formed on upper and lower portions of the ion channel layer, and an ion source gate electrode formed in contact with a side surface of the ion channel layer ,
Applying an overvoltage to the source electrode;
Transferring ions from the source electrode into the ion channel layer by the overvoltage;
The ions forming a conductive bridge between a source electrode and a drain electrode;
A normal current flow between the source electrode and the drain electrode with an overvoltage of the source electrode as a steady voltage;
Applying a voltage to the ion source gate electrode to remove the flow of the normal current to move the ion layer formed at the center of the conductive bridge of the ion channel layer to the first diffusion barrier layer to remove the conductive bridge ; And
And removing the steady-state current flow between the source electrode and the drain electrode. 16. The method of claim 15,
After the step of removing the steady current flow between the source electrode and the drain electrode,
Applying a reverse voltage to the ion source gate electrode to form a steady current flow to move the ion layer formed on the first diffusion barrier layer to the center of the ion channel layer to form a conductive bridge; And
Wherein the steady state current flow is between the source electrode and the drain electrode. 16. The method of claim 15,
After removing the conductive bridge by applying a voltage to the ion source gate electrode to remove the flow of the normal current to move the ions formed at the center of the ion channel layer onto the first diffusion prevention layer,
Maintaining a state of the ion layer formed on the first diffusion preventing layer in a state in which electric power is cut off and is not supplied; And
And maintaining the state of the steady current flow being interrupted between the source electrode and the drain electrode when power is supplied. 16. The method of claim 15,
Forming a conductive bridge between the source electrode and the drain electrode by applying a reverse voltage to the ion source gate electrode to move the ions on the first diffusion barrier layer to the center of the ion channel, After the step,
Maintaining the state of the ionic layer forming the conductive bridge in a state in which power is not supplied and is not supplied; And
Further comprising the step of generating said steady current flow between said source electrode and said drain electrode when power is supplied. 16. The method of claim 15,
Wherein applying the voltage to the ion source gate electrode comprises applying the voltage stepwise to adjust the amount of movement of the ions in the ion channel layer.

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