KR20170117863A - Neuromorphic Device Including Synapses Having Fixed Resistance - Google Patents

Abstract

Pre-synaptic neurons; Rows extending from the pre-synaptic neurons in a row direction; Post-synaptic neurons; Column lines extending from the post-synaptic neurons in a column direction; And synapses arranged on the intersections of the row lines and the column lines. The synapses include resistive wires having fixed resistance values.

Description

Neuromorphic Device Including Synapses Having Fixed Resistance < RTI ID = 0.0 >

The present invention relates to a read-only neuromorph element comprising synapses with fixed resistance values.

Recently, NyomopliK technology, which mimics the human brain, is attracting attention. The neuromotor technology includes multiple pre-synaptic neurons, multiple post-synaptic neurons, and multiple synapses. The neuromorph elements used in the neuromotor technology output pulses or spikes at various levels, sizes, or times depending on the learned state. Neuroreoptic devices, including synapses with variable resistors for read and write, have complex circuit configurations. For example, address coding / decoding circuits and row and column drivers are needed to designate a particular synapse in the enhancement and suppression process to change the synaptic weight. Further, in the case of having a plurality of multi-layers, peripheral circuits corresponding to the respective layers are further required. That is, the chip size of the neuromodule device can be increased. In addition, variable resistors may change their resistance values due to internal electrical influences, so that the data preservation ability of synapses may be degraded.

A problem to be solved by the present invention is to provide synapses having fixed resistance values.

A problem to be solved by the present invention is to provide a novel chromophore device including synapses having fixed resistance values.

A problem to be solved by the present invention is to provide neuromorphic devices including a plurality of synapse layers having fixed resistance values.

The various problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

The neuromorph element according to one embodiment of the technical idea of the present invention includes pre-synaptic neurons; Rows extending from the pre-synaptic neurons in a row direction; Post-synaptic neurons; Column lines extending from the post-synaptic neurons in a column direction; And synapses disposed on the intersections of the row lines and the column lines. The synapses may include resistive wires having fixed resistance values.

The fixed resistance values may have at least four levels.

The resistor wirings may comprise silicon doped with N-type ions.

The resistance wirings may include at least one of a lightly doped region, an intermediate concentration doped region, and a heavily doped region.

The synapses may each further include a row contact and a column contact. Each of the resistance wirings can electrically connect the row contact and the column contact.

The resistance wiring may include a plurality of via plugs electrically connected to each other.

The via plugs may further include a plurality of pads between the plurality of via plugs.

The plurality of via plugs may be vertically aligned with each other or not vertically aligned with each other to provide various resistance levels according to various conductive paths.

The plurality of via plugs may have different horizontal thicknesses.

The post-synaptic neurons may include an integrator and a comparator.

The neuromorph element according to one embodiment of the technical idea of the present invention includes pre-synaptic neurons; Rows extending from the pre-synaptic neurons in a row direction; Post-synaptic neurons; Column lines extending from the post-synaptic neurons in a column direction; And synapses disposed on the intersections of the row lines and the column lines. The synapses may have resistive wiring comprising doped ions at various concentrations.

The resistance wirings may be part of a substrate.

The post-synaptic neurons may include an integrator having an input coupled to the column lines and a comparator receiving an output of the integrator as an input.

The neuromorph element according to one embodiment of the technical idea of the present invention includes pre-synaptic neurons; Rows extending from the pre-synaptic neurons in a row direction; Post-synaptic neurons; Column lines extending from the post-synaptic neurons in a column direction; And synapses disposed on the intersections of the row lines and the column lines. The synapses may have conductive paths of different lengths.

The synapses may each further include a row contact and a column contact. Each of the resistance wirings can electrically connect the row contact and the column contact.

The resistance wiring may include a plurality of via plugs electrically connected to each other.

The via plugs may further include at least one pad between the plurality of via plugs.

The plurality of via plugs may include various cross-sectional areas.

The resistance wirings may include at least one of a plurality of doped regions having different doping concentrations.

The post-synaptic neurons may include post-synaptic circuits electrically connected to the column lines, respectively. The post-synaptic circuits may include an integrator and a comparator.

The details of other embodiments are included in the detailed description and drawings.

According to the technical idea of the present invention, since the synapses have fixed resistance values, a neuromorph element having various data patterns is provided without learning the synapses.

According to the technical idea of the present invention, since synapses have fixed resistance values, a neuromorph element having excellent data preservation ability of synapses is provided.

According to the technical idea of the present invention, since the synapses are formed using a low-priced fixed resistance material rather than an expensive variable resistance material, the production cost of the novelromot device is lowered. In other words, the optimum neurotic device that can be used in a specific field is provided at a low price.

According to the technical idea of the present invention, a neuromorphic chip having a specific function (which classifies a specific pattern) can be made in an integrated process step.

According to the technical idea of the present invention, neighboring circuits can be omitted, so that the neuromorph element becomes smaller.

According to the technical idea of the present invention, the number of data patterns recognizable by a synapse element is increased.

The technical idea of the present invention increases the recognition accuracy for complex patterns.

The effects of various embodiments of the present invention not otherwise mentioned will be mentioned in the text.

1 is a block diagram conceptually showing a neuromorph element according to an embodiment of the present invention.
FIGS. 2A through 5 are diagrams illustrating setting of synapses having fixed resistance values of a neuromorph element according to various embodiments of the technical idea of the present invention. FIG.
Figures 6a-6d illustrate methods of implementing synapses with fixed resistance values according to various embodiments of the inventive concepts.
FIG. 7A is a conceptual vertical sectional view of synapses having fixed resistance values according to one embodiment of the technical idea of the present invention, and FIG. 7B is a layout or plan view of synapses.
FIG. 8 is a block diagram conceptually illustrating a post-synaptic neuron according to an embodiment of the present invention.
FIGS. 7A and 7B are block diagrams conceptually illustrating a multi-neck pixel system according to embodiments of the present invention.
FIG. 8 is a block diagram conceptually showing a pattern recognition system according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions.

It is to be understood that one element is referred to as being 'connected to' or 'coupled to' another element when it is directly coupled or coupled to another element, One case. On the other hand, when one element is referred to as being 'directly connected to' or 'directly coupled to' another element, it does not intervene another element in the middle. &Quot; and / or " include each and every one or more combinations of the mentioned items.

Spatially relative terms such as 'below', 'beneath', 'lower', 'above' and 'upper' May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figure, an element described as 'below' or 'beneath' of another element may be placed 'above' another element.

Like reference numerals refer to like elements throughout the specification. Accordingly, although the same reference numerals or similar reference numerals are not mentioned or described in the drawings, they may be described with reference to other drawings. Further, even if the reference numerals are not shown, they can be described with reference to other drawings.

In this specification, the terms potentiation, set, and learning are used in the same or similar terms, and depressing, resetting, and initiation are used in the same or similar sense will be. For example, the action of lowering the resistance of the synapses will be described as enhancement, set, or learning, and the action of increasing the resistance of the synapses will be described as suppression, reset, or initialization. Also, when the synapses are enriched, set, or learned, the conductivity is increased, so that a progressively higher voltage / current can be output, and as the synapses are suppressed, reset, or initialized, . For ease of explanation, data patterns, electrical signals, pulses, spikes, and fire can be interpreted to be the same, similar, or compatible meanings. Also, voltage and current can be interpreted to be the same or compatible.

1 is a block diagram conceptually showing a neuromorph element according to an embodiment of the present invention. Referring to FIG. 1, a neuromorphic device according to an embodiment of the present invention includes a plurality of pre-synaptic neurons 10, each pre-synaptic neurons 10 A plurality of row lines R, a plurality of post-synaptic neurons 20 extending from the post-synaptic neurons 20 in a row direction from the post-synaptic neurons 20, And a plurality of synapses 30 (synapses) disposed on each of the intersections of the row lines R and the column lines C, have.

The pre-synaptic neurons 10 may transmit internal input signals to the synapses 30 via the low lines R. The internal input signals may include a data pattern.

The post-synaptic neurons 20 may receive internal output signals from the synapses 30 through the column lines C. [ The internal output signals may have information about registered, memorized, or saved data patterns in synapses 30. [

Each of the synapses 30 may comprise a fixed resistive device. Specifically, each of the synapses 30 may have one of multi-level fixed resistance values of at least four levels. The multi-level resistors of each synapse 30 can be interpreted as a synaptic weight.

FIGS. 2A through 5 are diagrams illustrating setting of synapses having fixed resistance values of a neuromorph element according to various embodiments of the technical idea of the present invention. FIG. 2a, 3a, and 4a are various input patterns P1-P3 and FIGS. 2b, 3b, and 4b illustrate synaptic weight maps M1-M2 computing input patterns P1- And Figs. 2C, 3C and 4C are synapse columns (C1-C3) set to have fixed resistance values programmed according to synapse weight maps Ml-M3. Illustratively, input patterns (P1-P3) are computed with synaptic weight maps (M1-M3) having 7 X 7 arrays of cells and programmed to have fixed resistance values corresponding to the synaptic weights of each cell The synaptic columns C1-C3 are shown. For ease of understanding the technical idea of the present invention, it is assumed that the input patterns P1-P3 are black-and-white image patterns having the shape of the number "1 ". Therefore, it is assumed that the synaptic weights have information corresponding to 1 or 0.

FIG. 2A is a first input pattern P1, FIG. 2B is a first synapse weight map M1 computing the first input pattern P1, and FIG. 2C is a graph of the first input pattern P1 having fixed resistance values corresponding to synapse weights The first synapse column C1 is shown. Referring to FIGS. 2A and 2B, the first input pattern P1 may be illustrated as a first synapse weight map M1, by way of example, separated into cells of the 7x7 array. Software and image processors may be used. The first synapse weight map M1 may be divided into cells having information of 1 and cells having information of 0. 1 are shown using hatching. Referring to FIG. 2C, the first synapse column C1 may include synapses 30 programmed to have fixed resistance values corresponding to synapse weights of the synapse weight map M1 of FIG. 2B. Specifically, the synapses 30 disposed on the first synapse column C1 can be sequentially programmed to correspond to the cells of the first synapse weight map M1. The cell numbers of the first synapse weight map M1 were interpreted and converted into the numbers of the row lines R1 to R49. Thus, the synapses 30 are blacked out in the first synapse weight map M1 with cells hatching, that is, cells having a synapse weight of one.

Referring to Figures 3A-3C, a second input pattern P2 may be computed as a second synapse weight map M2 and programmed into a second synapse column C2. Referring to Figures 4A-4C, a third input pattern P3 may be computed as a third synapse weight map M3, and may be programmed into a third synapse column C3.

In the technical concept of the present invention, the input patterns P1-P3 may be a color image or an image having multiple contrasts and colors. Further, in the expanded embodiments of the present invention, the input patterns Pl-P3 may be various auditory data. Thus, synapse weights and fixed resistance values can also be multi-level.

FIG. 5 is a diagram conceptually showing a final synaptic array SA including finally programmed synapses 30. FIG. 5, the final synapse array SA includes synapse weights of the first to third synapse weight maps M1 to M3 corresponding to the first to third input data P1 to P3, (C1-C3). Specifically, it may include all of the information of the synapse resistance values of the synapse columns C1-C3 shown in Figs. 2C, 3C and 4C. In addition, the synapse array SA can have information about as many input patterns as the number of column lines C.

6a-6d illustrate methods of implementing the synapses 30 with fixed resistance values according to various embodiments of the inventive concept.

6A is a conceptual layout or plan view of synapses 30 having fixed resistance values according to an embodiment of the present invention. Referring to FIG. 6A, synapses 30 having fixed resistance values according to an embodiment of the present invention include a row contact Rc, a column contact Cc, and a row contact Rc, And resistance wirings Ir for electrically connecting the contacts Cc. The row contact Rc may be electrically connected to one of the row lines R and the column contact Cc may be electrically connected to one of the column lines C. [ The resistive wirings Ir can have various geometric shapes to have various lengths. That is, the fixed resistance values of the resistance wirings Ir can be set by a length difference according to various geometrical shapes of the resistance wirings Ir. For example, the resistance wiring Ir of the synapse 30 having the synapse weight of "1" can be formed to be relatively short. If a very high resistance value is required, the resistance wiring Ir may be broken or not formed. The resistance wirings Ir may be formed and provided in the silicon substrate. For example, the resistance wirings Ir may be provided in the form of silicon doped with N-type ions such as phosphorous or As, arsenic, metal silicide wiring, or metal wiring. The resistive wirings Ir may be part of the silicon substrate.

6B is a layout or plan view of synapses 30 having fixed resistance values according to an embodiment of the present invention. Referring to FIG. 6B, synapses 30 having fixed resistance values according to an embodiment of the technical idea of the present invention are configured such that the resistance wires Ir are connected to the synapses 30, as compared to the synapses 30 shown in FIG. And may be formed to have various conductivities so as to have various resistance values according to the weights. Specifically, the resistance wirings Ir may have one of a high resistance region Hr, a middle resistance region Mr, a low resistance region Lr, or a combination thereof. The resistive wirings (Ir) may have more various doping concentrations. In one embodiment of the inventive concept, the resistive wirings Ir may comprise silicon regions with various doping concentrations.

6C is a longitudinal sectional view of synapses 30 having fixed resistance values according to one embodiment of the technical idea of the present invention. Referring to FIG. 6C, synapses 30 having fixed resistance values according to an embodiment of the present invention are formed in the row contact Rc, the column contact Cc, and the row contact Rc and the column contact (Ir) electrically connecting the electrodes Cc and Cc. The row contact Rc and the column contact Cc may be portions of the row line R or the column line C. [ The resistance wirings Ir may include a plurality of vertically extending via plugs Vr1-Vr4 and horizontally extending pads Pr1-Pr3. The via plugs Vr1-Vr4 may have a columnar shape, and the pads Pr1-Pr3 may have a square shape or a bar shape in a top view. The via plugs Vr1-Vr4 may have various geometries that are vertically aligned or non-aligned with one another so that the resistance wires Ir can have various fixed resistance values. Thus, the via plugs Vr1-Vr4 can provide various resistance levels according to various conductive paths. Illustratively, although the resistance wires Ir are shown as having four layers of via plugs (Vr1-Vr4), they may have more than five layers of via plugs Vrx. In this embodiment, the resistance wirings Ir may have various fixed resistance values depending on the difference in the electrical path of the row contact Rc and the column contact Cc. The via plugs (Vr1-Vr4) and pads Pr1-Pr3 may each comprise one of doped silicon, silicide, metal, or combinations thereof.

FIG. 6D is a longitudinal sectional view of synapses 30 having fixed resistance values according to an embodiment of the present invention. 6d, synapses having fixed resistance values according to an embodiment of the technical idea of the present invention are compared with the synapses 30 shown in FIG. 6c, and the via plugs having various horizontal widths or horizontal widths Vr1-Vr4). That is, the via plugs Vr1-Vr4 may have at least one of various cross-sectional areas. Thus, the via plugs Vr1-Vr4 can provide various resistance levels between the row contact Rc and the column contact Cc.

FIG. 7A is a conceptual vertical cross-sectional view of synapses 30 having fixed resistance values according to one embodiment of the inventive concept, and FIG. 7B is a layout or plan view of synapses 30.

Referring to FIG. 7A, synapses 30 having fixed resistance values according to an embodiment of the technical idea of the present invention include a resistance wiring Ir formed in a substrate sub, and a low- (Rc) and a column contact (Cc). The row contact Rc can be electrically connected to the resistance wiring Ir and the row line R through the first interlayer insulating layers ILD1 vertically and the column contact Cc can be electrically connected to the first interlayer insulating layer May be vertically penetrated through the insulating layers ILD1 and ID2 and electrically connected to the resistance wiring Ir and the column line C. The row contact Rc and the column contact Cc may be interchanged.

Referring to FIG. 7B, the resistance wiring Ir according to an embodiment of the present invention may include resistance wiring Ir formed using various conductive materials. For example, the resistance wirings Ir may include combinations of various resistance regions R1 to Rn. For example, the various resistance regions Rl to Rn of the resistive wirings Ir may include an intrinsic semiconductor region, a lightly doped semiconductor region, a heavily doped semiconductor region, a metal silicide region, a metal compound region, a metal alloy region, Metal regions, respectively. Therefore, the resistance wiring Ir may have multiple resistance levels selectively including various resistance regions R1 to Rn.

FIG. 8 is a block diagram conceptually illustrating a post-synaptic neuron 20 according to an embodiment of the present invention.

8, a post-synaptic neuron 20 according to an embodiment of the present invention includes post-synaptic circuits 20a to 20d connected independently to each of the column lines Ca to Cd And each post-synaptic circuit 20a-20d may include integrators 21a-21d and comparators 22a-22d, respectively. Specifically, it may include integrators 20a-20d having input portions electrically connected to the column lines Ca-Cd and comparators 22a-22d receiving inputs of the outputs of integrators 20a-20d. have. The post-synaptic circuits 20a-20d integrate the electrical signals received from the synapses 30 through corresponding column lines Ca-Cd, respectively, and the voltage of the integrated electrical signal is applied to the reference voltage Vr ), It can be fired.

FIGS. 9A and 9B are block diagrams conceptually illustrating a multi-neck pixel system according to embodiments of the present invention. Referring to Figs. 9A and 9B, the multi-nephropic systems according to embodiments of the technical idea of the present invention may include multi-synaptic arrays SA1-SA4. Specifically, a multi-synaptic neuromotion system may include an input device Di, an output device Do, three or more synaptic neurons N1-N5, and two or more synaptic arrays SA1-SA4. The input device Di may include an image sensor, a scanner, a keyboard, a mouse, a touch panel, a touch pen, a microphone, a sound receiver, a sampler, or various other recognition devices. Synaptic neurons (N1-N5) may comprise pre-synaptic neurons or post-synaptic neurons. The first synaptic neuron N1 may include a pre-processor that can convert the input pattern into a digital signal, such as an image processor or a sound processor. The synaptic arrays SA1-SA4 may comprise at least one of the final synaptic arrays SA according to various embodiments of the present invention. That is, it may include synapses 30 having a fixed resistance value. The novel Lomographic systems including the multi-synaptic arrays SA1-SA4 according to the present embodiments may further provide various data patterns that were not provided in one synapse array. In addition, the novel Lomographic systems, including the multi-synaptic arrays SA1-SA4, can more accurately recognize complex data patterns.

FIG. 10 is a block diagram conceptually showing a pattern recognition system 900 according to an embodiment of the technical idea of the present invention. For example, the pattern recognition system 900 may include a speech recognition system, an imaging recognition system, a code recognition system, a signal recognition system, And may be one of systems for recognizing various patterns.

10, a pattern recognition system 900 of an embodiment of the technical concept of the present invention includes a central processing unit 910, a memory unit 920, a communication control unit 930, a network 940, an output unit 950, an input unit 960, an analog-to-digital converter 970, a novel Lomographic unit 980, and / or a bus 990. The central processing unit 910 generates and transmits a variety of signals for learning of the novel Lomographic unit 980 and generates various signals for recognizing patterns such as voice, Processing, and function.

The central processing unit 910 is connected to a memory unit 920, a communication control unit 930, an output unit 950, an analog-to-digital converter 970 and a novel Lomographic unit 980 via a bus 990 .

The memory unit 920 may store various information required to be stored in the pattern recognition system 900. The memory unit 920 may be a volatile memory device such as DRAM or SRAM, non-volatile memory such as PRAM, MRAM, ReRAM, or NAND flash memory. Memory, or various storage units such as a hard disk drive (HDD) or a solid state drive (SSD).

The communication control unit 930 can transmit and / or receive the recognized voice, video, and other data via the network 940 to the communication control unit of the other system.

The output unit 950 can output the recognized voice, image, and other data in various manners. For example, the output unit 950 may include a speaker, a printer, a monitor, a display panel, a beam projector, a holographer, or various other output devices.

The input unit 960 may include at least one of a microphone, a camera, a scanner, a touch pad, a keyboard, a mouse, a mouse pen, or various sensors.

The analog-to-digital converter 970 can convert the analog data input from the input device 960 into digital data.

The neuromode unit 980 can perform learning, recognition, and the like using data output from the analog-to-digital converter 970, and can output data corresponding to the recognized pattern . The neodrome unit 980 may include at least one of the neuromorph elements according to various embodiments of the inventive concepts.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and not restrictive in every respect.

10: pre-synaptic neurons
20: Post-synaptic neuron
30: Synapse
C: Column line
Cc: Column contact
M1-M3: Synaptic weight map
P1-P3: Input pattern
Cl-Cn: synaptic column
SA: Final synaptic array
R: Lowline
Rc: Low contact
Ir: resistance wiring
Vrx: Via plug
Prx: Pad

Claims (20)

Pre-synaptic neurons;
Rows extending from the pre-synaptic neurons in a row direction;
Post-synaptic neurons;
Column lines extending from the post-synaptic neurons in a column direction; And
And synapses disposed on the intersections of the row lines and the column lines,
Wherein the synapses comprise resistive wires having fixed resistance values.
The method according to claim 1,
Wherein the fixed resistance values have at least four levels.
The method according to claim 1,
Wherein the resistance wirings comprise silicon doped with N-type or P-type ions.
The method of claim 3,
Wherein the resistance wirings include at least one of a lightly doped region, a lightly doped region, and a lightly doped region.
The method according to claim 1,
The synapses each further include a row contact and a column contact,
And each of the resistance wirings electrically connects the row contact and the column contact.
The method according to claim 1,
Wherein the resistance wiring includes a plurality of via plugs electrically connected to each other.
The method according to claim 6,
Wherein the via plugs further comprise a plurality of pads between the plurality of via plugs. The method according to claim 6,
Wherein the plurality of via plugs are vertically aligned with each other or do not vertically align with one another, thereby providing various resistance levels according to various conductive paths.
The method according to claim 6,
Wherein the plurality of via plugs have different horizontal thicknesses.
The method according to claim 1,
Wherein said post-synaptic neurons comprise an integrator and a comparator.
Pre-synaptic neurons;
Rows extending from the pre-synaptic neurons in a row direction;
Post-synaptic neurons;
Column lines extending from the post-synaptic neurons in a column direction; And
And synapses disposed on the intersections of the row lines and the column lines,
Wherein the synapses have resistance wirings comprising ions doped at various concentrations.
12. The method of claim 11,
Wherein the resistive wires are part of a substrate.
12. The method of claim 11,
Wherein the post-synaptic neurons include an integrator having an input coupled to the column lines and a comparator receiving an output of the integrator as an input.
Pre-synaptic neurons;
Rows extending from the pre-synaptic neurons in a row direction;
Post-synaptic neurons;
Column lines extending from the post-synaptic neurons in a column direction; And
And synapses disposed on the intersections of the row lines and the column lines,
Wherein the synapses have conductive paths of different lengths.
15. The method of claim 14,
The synapses each further include a row contact and a column contact,
And each of the resistance wirings electrically connects the row contact and the column contact.
15. The method of claim 14,
Wherein the resistance wiring includes a plurality of via plugs electrically connected to each other.
17. The method of claim 16,
Wherein the via plugs further comprise at least one pad between the plurality of via plugs.
17. The method of claim 16,
The plurality of via plugs including at least one of various cross-sectional areas.
15. The method of claim 14,
Wherein the resistance wirings comprise at least one of a plurality of doped regions having different doping concentrations.
15. The method of claim 14,
Wherein the post-synaptic neurons include post-synaptic circuits electrically connected to the column lines, respectively, and
Wherein the post-synaptic circuits comprise an integrator and a comparator.

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