KR20170109200A - Display driving device and display device - Google Patents

Abstract

A display driving apparatus according to an exemplary embodiment of the present invention includes a digital-to-analog converter for generating analog image data, a plurality of pads connected to a plurality of data lines included in a display panel, A buffer circuit having a plurality of buffers for outputting a plurality of buffers, a first switch connected between an output end of the plurality of buffers and the plurality of pads, and a second switch connected between an input of the plurality of buffers and the digital- When the data voltage is output to the plurality of data lines through the plurality of pads, turning off the first switch and turning on the second switch to turn the output of at least some of the plurality of buffers to a new data voltage .

Description

DISPLAY DRIVING DEVICE AND DISPLAY DEVICE

The present invention relates to a display driving apparatus and a display apparatus.

Display devices such as liquid crystal displays (LCDs) and organic light emitting display devices (OLEDs) have been widely applied to mobile devices such as tablet PCs, smart phones, laptop computers, as well as home and industrial displays such as televisions and monitors . Particularly in recent years, research on a display device capable of operating at a low power consumption while realizing a high resolution is actively progressing. As the resolution of the display device increases, the time to operate the driving line connected to the plurality of pixels and the time to reflect the data signal to the plurality of pixels may become shorter, and when the data signal is not sufficiently reflected in each pixel Distortion may occur in the image displayed by the display device. Therefore, various methods for sufficiently reflecting the data signal to a plurality of pixels within a short time have been proposed.

One of the problems to be solved by the technical idea of the present invention is to provide a display driving device and a display device which can prevent image distortion and deterioration and can operate with low power.

A display driving apparatus according to an exemplary embodiment of the present invention includes a digital-to-analog converter for generating analog image data, a plurality of pads connected to a plurality of data lines included in a display panel, A buffer circuit having a plurality of buffers for outputting a plurality of buffers, a first switch connected between an output end of the plurality of buffers and the plurality of pads, and a second switch connected between an input of the plurality of buffers and the digital- When the data voltage is output to the plurality of data lines through the plurality of pads, turning off the first switch and turning on the second switch to turn the output of at least some of the plurality of buffers to a new data voltage .

A display driving apparatus according to an embodiment of the present invention includes a latch circuit for sampling and storing digital image data, a shift register for controlling the sampling timing of the latch circuit, A plurality of buffers for receiving the analog video data to generate a data voltage and a plurality of pads for connecting the output ends of the plurality of buffers to a plurality of data lines, The data voltages output by at least a part of the buffers are output to the plurality of data lines through the plurality of pads after a predetermined delay time has elapsed.

A display device according to an embodiment of the present invention includes a display panel having a plurality of first pixels arranged along a first gate line and a plurality of second pixels arranged along a second gate line, And a plurality of buffers for outputting a first data voltage to a first pixel of the plurality of pixels and outputting a second data voltage to the plurality of second pixels during a second period following the first period, And a controller for updating the second data voltage with an output of at least a portion of the plurality of buffers during a first period.

The display driving apparatus according to the embodiment of the present invention may update the output of at least a part of the plurality of buffers connected to the plurality of data lines with the video data to be inputted to the plurality of data lines for the next period. Therefore, when the next period comes, the influence of the slew time of the plurality of operational amplifiers on the charging time of the pixel can be minimized, thereby preventing the image displayed on the display device from being distorted or deteriorated, The power consumption of the apparatus can be reduced.

The various and advantageous advantages and effects of the present invention are not limited to the above description, and can be more easily understood in the course of describing a specific embodiment of the present invention.

1 is a view illustrating a display device including a display driving device according to an embodiment of the present invention.
2 is a block diagram briefly showing a data driver included in a display driving apparatus according to an embodiment of the present invention.
3 and 4 are diagrams for explaining the operation of the display driving apparatus according to the embodiment of the present invention.
5 is a timing diagram for explaining an operation method of a display driving apparatus according to an embodiment of the present invention.
6 is a waveform diagram for explaining the operation of the display driving apparatus according to the embodiment of the present invention.
7 is a view for explaining the operation of the buffer circuit included in the display driving apparatus according to the embodiment of the present invention.
8 is a timing diagram provided to explain a method of operating a display driving apparatus according to an embodiment of the present invention.
9 is a flowchart illustrating a method of operating a display driving apparatus according to an embodiment of the present invention.
10 is a block diagram showing an electronic apparatus to which a display device according to an embodiment of the present invention can be applied.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a view illustrating a display device including a display driving device according to an embodiment of the present invention.

Referring to FIG. 1, a display device 10 according to an embodiment of the present invention may include a display driving device 20 and a panel 30. The display driver 20 may include a data driver 21, a gate driver 22, a controller 23, a power supply circuit 24, and the like.

The panel 30 may include at least one substrate and a plurality of gate lines GL ₁ -GL _m : GL and data lines DL ₁ -DL _n : DL may be disposed on the substrate so as to intersect with each other . A plurality of pixels PX may be defined at the intersections of the plurality of gate lines GL and the data lines DL. In one embodiment, a plurality of first pixels P ₁₁ -P _1n may be defined by a plurality of data lines DL intersecting the first gate line GL 1, and the second gate lines GL 2, A plurality of second pixels P ₂₁ -P _2n may be defined by a plurality of intersecting data lines DL.

The pixel PX may include a transistor having a gate electrode and a source electrode connected to a plurality of gate lines GL and a data line DL and a capacitor connected to a drain electrode of the transistor. The capacitor may include a storage capacitor, and when the display device 10 is a liquid crystal display (LCD), a liquid crystal capacitor may further be connected. When the display device 10 is an organic light emitting display (OLED), the capacitor may be used as a capacitor for supplying a constant current to the organic electroluminescent device included in each pixel PX.

The controller 23 may include a timing controller, a memory circuit, and the like. The timing controller can generate a signal for controlling the driving timings of the signals that the gate driver 22 and the data driver 21 provide to the plurality of gate lines GL and data lines DL.

The gate driver 22 can scan the plurality of gate lines GL based on a control signal transmitted from the controller 23. [ In one embodiment, the gate driver 22 may select at least one of the plurality of gate lines GL to apply the gate power supply voltage. The gate line GL selected by the gate power supply voltage can be activated. The data driver 21 may receive a data voltage for displaying an image on a pixel PX connected to the activated gate line GL by receiving a gate power supply voltage. The data voltage may be input through a plurality of data lines DL connected to the pixel PX.

The data driver 21 can input a data voltage to the plurality of data lines DL based on a control signal transmitted from the controller 23. [ The data voltages input to the plurality of data lines DL can be generated based on the video data input to the data driver 21. [ The image data may be digital image data. The data voltage may be input to the data line DL that receives the gate power supply voltage from the gate driver 22 and crosses the activated gate line GL. Accordingly, the image can be displayed in the order that the gate driver 22 scans the gate line GL, i.e., in units of horizontal lines of the panel 30. [

The power supply circuit 24 can generate various internal power supply voltages required for the operation of the display device 10 based on the external power supply voltage supplied from the outside. The internal power supply voltage may be a plurality of voltages having different values. The power supply circuit 24 may include a charge pump circuit for generating the internal power supply voltage. In one embodiment, the power supply circuit 24 can generate the gate power supply voltage necessary for driving the gate line GL based on the external power supply voltage. The gate power supply voltage may have a value different from the external power supply voltage.

2 is a block diagram briefly showing a data driver included in a display driving apparatus according to an embodiment of the present invention.

Referring to FIG. 2, a data driver 100 according to an embodiment of the present invention may include a shift register 110, a latch 120, a digital-to-analog converter 130, a buffer circuit 140, have. The latch 120 may include a sampling latch 121 for sampling data and a holding latch 122 for storing data sampled by the sampling latch 121. Each element 110-140 included in the data driver 100 is not limited to the embodiment shown in FIG. 2, and may be modified in various forms.

The shift register 110 can control the operation timing of each of the plurality of latch circuits included in the sampling latch 121 in response to the horizontal synchronizing signal Hysnc. The horizontal synchronization signal Hsync may be a signal having a predetermined period. The sampling latch 121 can sample the digital image data (DATA) according to the shift order of the shift register 110. [ The digital image data (DATA) sampled by the sampling latch 121 may be stored in the holding latch 122. The holding latch 122 may output the digital image data (DATA) stored in response to the second latch signal (S-latch) to the digital-analog converter 130.

The digital-to-analog converter 130 may convert the digital image data DATA to analog image data VIN ₁ -VIN _n : VIN. In one embodiment, the analog video data VIN generated by the digital-to-analog converter 130 may be converted to the data voltages VD ₁ -VD _n : VD by the buffer circuit 140. The data voltage VD may be output to a plurality of data lines DL ₁ -DL _n : DL connected to each pixel PX.

The data driver 100 can start its operation while the horizontal synchronization signal Hsync is input to the shift register 110. [ The shift register 110 receiving the horizontal synchronizing signal Hsync can sequentially operate a plurality of sampling circuits included in the sampling latch 121. [ The sampling latch 121 may sample the digital image data (DATA) and store the sampled data in the holding latch 122.

The holding latch 122 may transmit the stored digital image data (DATA) to the digital-to-analog converter 130 in response to a second latch signal (S-latch). The digital-to-analog converter 130 may convert the digital image data (DATA) to analog image data (VIN). The analog image data VIN may include data corresponding to a voltage to be input to each of the plurality of data lines DL. The buffer circuit 140 may generate the data voltage VD using the analog image data VIN.

The buffer circuit 140 may include a plurality of buffers implemented by an operational amplifier, and each of the plurality of buffers may be connected to the plurality of data lines DL through a plurality of pads. That is, a plurality of data lines DL and a switch element included in each pixel PX may be connected to an output terminal of each of the plurality of buffers. Therefore, when the resolution of the display device 10 increases, the load of the buffer output stage may increase. As the load on the buffer output stage increases, the slew time required to set the output of the buffer to the data voltage VD may become longer.

The time during which the capacitor included in the pixel PX is charged by the data voltage VD within one period of the horizontal synchronizing signal Hsync may be reduced when the slew time of the buffer becomes longer, ) May be degraded. In order to solve such a problem, it is possible to shorten the slew time by driving the buffer with a high current. In this case, however, the consumption power of the display device 10 may increase.

In the embodiment of the present invention, the above problem can be solved by controlling the operation method of the buffer circuit 140. [ For example, the above problem can be solved by previously updating the outputs of at least some of the plurality of buffers included in the buffer circuit 140. [

3 is a view for explaining the operation of the display driving apparatus according to the embodiment of the present invention. 3 shows the buffer circuit 140 shown in FIG. 2 in more detail.

3, a buffer circuit 140 according to an embodiment of the present invention includes a plurality of first switches OSW ₁ -OSW _n : OSW, a plurality of second switches ISW ₁ -ISW _n : ISW, A plurality of buffers (BF ₁ -BF _n : BF), a plurality of pads (PAD ₁ -PAD _n : PAD), and the like. The plurality of buffers BF can be implemented by an operational amplifier or the like and the first switch OSW is connected to the output terminal of the plurality of buffers BF and the second switch ISW is connected to the input terminal of the plurality of buffers BF .

The plurality of pads PAD may be connected to a plurality of data lines DL ₁ -DL _n (DL) included in the display panel PN. That is, when the first switch OSW is turned on, the data voltages VD ₁ -VD _n : VD stored in the plurality of buffers BF are input to the data lines DL via the plurality of pads PAD . In one embodiment, the plurality of pads PAD may have a better response speed than the output ends of the plurality of buffers BF. That is, the slew time of the plurality of pads PAD may be shorter than the plurality of buffers BF.

The pixels (PX) arranged along: a data voltage (VD) is a gate line is activated by a gate driver (GL GL ₁ -GL _m) in which a plurality of the buffer (BF) output by the plurality of pads (PAD) Can be input. For example, when the first gate line GL ₁ is scanned by the gate driver, the data voltage VD output from the plurality of buffers BF is supplied to the first gate line GL ₁ (P ₁₁ -P _1n ) arranged along the first pixel (P ₁₁ -P _1n ).

When the scan period of the first gate line GL ₁ is terminated, the gate driver can scan the second gate line GL ₂ . In a typical display driving apparatus, after the scan period of the second gate line GL ₂ is started, the first and second switches OSW and ISW are turned on together and a new data voltage VD are stored and a new data voltage VD stored in the buffer BF can be updated to a voltage to be input to the plurality of second pixels P ₂₁ -P _2n .

That is, in a general display driving apparatus, a data voltage VD to be inputted to a plurality of pixels PX arranged along a scanned gate line GL after a scan period of each of the plurality of gate lines GL starts And can be stored in a plurality of buffers BF. Therefore, due to the slew time of the operational amplifier included in the plurality of buffers BF, the charging time for each of the plurality of pixels PX may not be sufficiently secured, which may lead to deterioration of the image quality of the display device. To solve this problem, it is possible to increase the amount of current to shorten the slew time of the operational amplifier, but this may lead to an increase in power consumption of the display device.

In the embodiment of the present invention, the above problem can be solved by previously storing a new data voltage VD in at least a part of the plurality of buffers BF. In one embodiment, when the output of the data voltage VD for the plurality of first pixels P ₁₁ -P _1n in the scan period of the first gate line GL ₁ is completed, the first switch OSW turns on - It can be turned off. Therefore, the output end of each of the plurality of buffers BF can be electrically separated from the plurality of pads PAD.

On the other hand, while the first switch (OSW) is turned off, the second switch (ISW) can be turned on. When the second switch ISW is turned on, the digital-to-analog converter 130 connected to the buffer circuit 140 is output to the plurality of data lines DL in the scan period of the second gate line GL ₂ The analog voltage data VIN corresponding to the data voltage VD to be supplied to the plurality of buffers 143 can be input. Therefore, before the scan period of the first gate line GL ₁ is ended, the output of at least some of the plurality of buffers BF can be updated in advance. At this time, the output of the buffer BF that has been updated in advance may not affect the plurality of first pixels P ₁₁ -P _1n since the first switch OSW is turned off.

The first when the scanning period is ended, the gate lines (GL ₁₎ and start the scanning period of the second gate line (GL _2), the first switch (OSW) is turned on so that the plurality is an output terminal of the plurality of the buffer (BF) The pad PAD of FIG. Therefore, the output of the buffer BF, which has been previously updated during the scan period of the first gate line GL ₁ , can be input to the plurality of second pixels P ₂₁ -P _2n via the pad PAD. At this time, in order to update the output of the buffer BF that has not yet been updated during the scan period of the first gate line GL ₁ , the second switch ISW is at least one in the scan period of the second gate line GL ₂ Can be turned on more than once.

In other words, the display driving apparatus according to the embodiment of the present invention is configured such that after the data voltage (VD) output through the plurality of pads PAD is completed in each scan period of the gate driver, To the new data voltage (VD). The new data voltage VD may be a voltage to be input to the plurality of data lines DL through a plurality of pads PAD in the next scan period of the gate driver.

As described above, the plurality of buffers BF can have a relatively long slew time in comparison with the plurality of pads PAD. In the embodiment of the present invention, the output of the plurality of buffers 143 having a relatively long slew time is updated in advance so that the time required for inputting the data voltage VD to the pixel PX in each scan period is sufficient . Therefore, since the charging time of the storage capacitor or the like included in each pixel PX can be sufficiently secured, image quality distortion and deterioration of the display device can be prevented, the display device can be operated with a small current, .

4 is a diagram for explaining the operation of the display driving apparatus according to the embodiment of the present invention. 5 is a timing diagram for explaining an operation method of a display driving apparatus according to an embodiment of the present invention.

 4, a display driver 500 according to an exemplary embodiment of the present invention includes a shift register 210, a latch 220, a digital-to-analog converter 230, a buffer circuit 240, a gate driver 300, , And a controller (400). The shift register 210, the latch 220, the digital-to-analog converter 230, and the buffer circuit 240 may be included in the data driver 200.

The buffer circuit 240 may include a buffer 243 connected to the digital-to-analog converter 230 and first and second switches 241 and 242 connected to the output and input terminals of the buffer 243, respectively have. The output of the buffer 243 is connected to the pad 244 via the first switch 241 and the input of the buffer 243 is connected to the output of the digital- (Not shown). The pad 244 may be connected to a data line DL included in the display panel. In one embodiment, the buffer circuit 240 may include as many buffers 243 as the number of data lines DL, as shown in FIG.

The buffer output BOUT may be determined by the analog image data VIN output by the digital-to-analog converter 230 and the buffer output BOUT may be determined by a plurality of pads 244 during the first switch 241 is turned on To the data line DL. That is, when the first switch 241 is turned on by the first control signal SOUT_EN, the buffer output BOUT can be reflected in the pad output POUT.

On the other hand, when the second switch 242 is turned on by the second control signal S-latch, the analog image data VIN generated by the digital-analog converter 230 can be input to the buffer 243 have. In one embodiment, the second control signal (S-latch) may be a signal such as a second latch signal (S-latch) that controls the output of the latch 220. That is, when the second switch 242 is turned on by the second control signal (S-latch), the digital-to-analog converter 230 receives the digital image data (DATA) output from the latch 220, The video data VIN can be generated. The analog image data VIN generated from the digital image data DATA may include data for generating the data voltage VD to be input to the data line DL.

The horizontal synchronization signal Hsync is transmitted from the controller 400 to the shift register 210 and may be a signal having a predetermined period. During one period of the horizontal synchronization signal Hsync, the gate line GL can be scanned by the gate driver 300. The display driver 500 may input the data voltage VD to the data line DL which intersects with the scanned gate line GL during one period of the horizontal synchronization signal Hsync.

5, the buffer circuit 240 supplies the data voltage VD [N (N) to the data line DL that crosses the N-th gate line GL scanned by the gate driver 300 during the period T _N , Can be supplied. Meanwhile, the latch 220 may sample and store the digital image data DATA [N + 1] during the period T _N. The digital image data DATA [N + 1] may include data for generating the data voltage VD [N + 1]. The data voltage VD [N + 1] may be a voltage to be input to the data line DL while the gate driver 300 scans the (N + 1) th gate line GL in the period T _{N + 1} .

On the other hand, each of the first and second switches 241 and 242 can be controlled by the first and second control signals SOUT_EN and S-latch. The buffer output BOUT can be reflected in the pad output POUT while the first control signal SOUT_EN has a high value in the cycle T _N of the timing diagram shown in Fig. The pad 244 can input the data voltage VD [N] output from the buffer 243 to the data line DL.

The display driver 500 according to the embodiment of the present invention can turn off the first switch 241 after the data voltage VD [N] is inputted to the data line DL through the pad 244 have. The first switch 241 may be turned off by the controller 400 switching the first control signal SOUT_EN to low. The controller 400 turns off the first switch 241 and then toggles the second control signal S-latch one or more times during the time? T1 to turn the second switch 242 on And the digital image data DATA [N + 1] stored in the latch 220 can be output to the digital-analog converter 230 at the same time.

Therefore, during the time? T1 included in the period T _N , the buffer output BOUT can be changed in advance to the data voltage VD [N + 1] that must be input to the data line DL during the period T _{N + 1} . That is, the data voltage VD [N + 1] may be stored in the buffer 243 during the time? T1. In one embodiment, the data driver 200 may include a plurality of buffers 243 and the output of at least some of the plurality of buffers 243 may be changed to a data voltage VD [N + 1] have. The changed buffer output BOUT may not be reflected in the pad output POUT since the first switch 241 maintains the turn-off state for the time? T1. That is, at least some of the plurality of buffers 243 output the data voltage VD [N + 1] and the plurality of pads 244 can output the data voltage VD [N] during the time? T1.

When the period T _{N + 1} is started by the horizontal synchronizing signal Hsync, the controller 400 turns on the first switch 241 and outputs the data voltage VD [N + 1] stored in the buffer 243 to the pad output (POUT). Since the pad 244 has a relatively shorter slew time than the buffer 243, the period T _{N + 1} is started and the voltage of the data line DL is changed to the data voltage VD [N + 1] within a short time have. Therefore, the charging time of each pixel PX through the data line DL can be sufficiently secured, deterioration of the image quality of the display device can be prevented, and the display driving device 500 can be operated with less power.

When the period T _{N + 1} begins, the controller 400 may turn on the second switch 242 one or more times. By this operation, the buffer output BOUT which can not be changed to the data voltage VD [N + 1] for the time? T1 can be set to the data voltage VD [N + 1].

The operation of the display driver 500 in the period T _{N + 1} may be similar to the operation in the period T _N. During the period T _{N + 1} , the gate driver 300 may scan the (N + 1) th gate line GL. When the period T _{N + 1} begins, the controller 400 may turn on the first switch 241 via the first control signal SOUT_EN. By the first switch 241 being turned on, the buffer output BOUT updated to the data voltage VD [N + 1] during the time? T1 can be reflected in the pad output POUT.

Meanwhile, while the first switch 241 is turned on in the period T _{N + 1} , the controller 400 turns the second switch 242 one or more times through the second control signal (S-latch) Can come on. Therefore, it is possible to change the output (BOUT) of the period T _N time △ t1 during the data voltage VD [N + 1] to be not update buffer 243 of, the period from T _{N + 1.}

Referring to the timing diagram of FIG. 5, latch 220 may sample and store digital image data DATA [N + 2] during period T _{N + 1} . The digital image data (DATA [N + 2]) may be data for generating the data voltage VD [N + 2]. The data voltage VD [N + 2] may be a voltage that must be input to the data line DL while the gate driver 300 scans the (N + 2) th gate line GL in the period T _{N + 2} .

When the output of the data voltage VD [N + 1] is completed in the cycle T _{N + 1} , the controller 400 turns off the first switch 241 and turns on the second switch 242 once The buffer output (BOUT) can be previously updated to the data voltage VD [N + 2]. Therefore, the charging time of each pixel PX through the data line DL can be sufficiently secured, deterioration of the image quality of the display device can be prevented, and the display driving device 500 can be operated with less power.

6 is a waveform diagram for explaining the operation of the display driving apparatus according to the embodiment of the present invention. 7 is a circuit diagram provided for explaining the waveform diagram shown in Fig.

The waveform diagram shown in FIG. 6 may be a diagram showing the buffer output BOUT, the pad output POUT, and the pixel voltage V _PX in the circuit diagram shown in FIG. Referring to FIG. 7, the buffer circuit 610 may include first and second switches 611 and 612, a buffer 613, a pad 614, and the like. The first switch 611 may be coupled between the output of the buffer 613 and the pad 614 and the second switch 612 may be coupled to the input of the buffer 613, (611, 612).

The pixel PX is connected to the pad 614 via a data line and can be represented by an equivalent circuit of a resistor Rp and a capacitor Cp. In one embodiment, the capacitor Cp may be a storage capacitor present in each pixel PX, and the resistor Rp may be a resistive component present in the data line and the turn-on transistor or the like.

Referring to Fig. 6, the buffer output (BOUT) may be updated beforehand during the time? T of the cycle T1. The first switch 611 may be turned off during the time? T such that the buffer output BOUT, which is previously updated during the time? T, is not input to the pixel PX. On the other hand, the second switch 612 may be turned on to update the buffer output (BOUT) in advance during the time? T. The buffer output BOUT that is updated in advance may be a data voltage to be input to the pixel PX during the period T2.

Referring to FIG. 6, after the cycle T2 starts, the buffer output (BOUT) may be reflected in the pad output (POUT). In the embodiment of the present invention, the slew time necessary for changing the buffer output (BOUT) during the period T2 can be included in the time? T of the cycle T1. 6, since the pad 614 can have a faster response speed than the buffer 613, that is, a fast slew rate, the capacitor C _P included in the pixel PX in the period T2 It is possible to sufficiently secure the charging time. As a result, it is possible to prevent deterioration of the image displayed by the display device by sufficiently ensuring the charging time of the pixel PX, and to drive the display device with low consumption power.

8 is a timing diagram provided to explain a method of operating a display driving apparatus according to an embodiment of the present invention. Hereinafter, the timing diagram shown in Fig. 7 will be described with reference to the display drive apparatus 500 shown in Fig.

At least a part of the plurality of buffers 243 included in the data driver 200 may receive the data voltage VD to be supplied to the data line DL during the next period of the horizontal synchronizing signal Hsync Can be stored in advance. In the embodiment shown in Fig. 8, the times? T1,? T2, and the like for previously updating the outputs of at least some of the plurality of buffers 243 can be determined by the data enable signal DE. The data enable signal DE may be a signal for detecting whether the latch 220 has completed sampling and storing the digital image data (DATA).

In the timing diagram shown in Fig. 8, the buffer circuit 240 outputs the data voltage VD [N] during the period T _N , and the latch 220 can sample and store the digital image data DATA [N + 1]. Period T _N latch the digital image data 220 is stored for a DATA [N + 1] is the period T _{N + 1} from the buffer circuit 240, the data voltage to be output VD [N + 1] data, one corresponding to the .

The data enable signal DE may have a high value while the latch 220 is sampling or storing the digital image data DATA [N + 1] and the latch 220 may output the digital image data DATA [N +1] It can be changed to low when saving is completed. When the data enable signal DE is changed to low, the controller 400 may turn off the first switch 241 and turn on the second switch 242 for a time? T1 . During a time? T1, the output of at least some of the plurality of buffers 243 may be updated with the data voltage VD [N + 1] corresponding to the digital image data DATA [N + 1] stored in the latch 220.

When the period T _{N + 1} arrives, the controller 400 turns on the first switch 241 through the first control signal SOUT_EN, thereby responding to the digital image data DATA [N + 1] It is possible to reflect the buffer output BOUT previously updated to the data voltage VD [N + 1] to the pad output POUT. The pad 244 may have a relatively faster slew rate than the buffer 243. Therefore, the time for charging the pixel PX by the data voltage VD [N + 1] during the period T _{N + 1} can be relatively long.

9 is a flowchart illustrating a method of operating a display driving apparatus according to an embodiment of the present invention. Hereinafter, the operation of the display driving apparatus 500 according to the flowchart shown in FIG. 9 will be described with reference to FIG. 5 and FIG. 6 together for convenience of explanation.

Referring to FIG. 9, the operation of the display driver 500 according to the embodiment of the present invention may start with the start of the Nth cycle (S10). The Nth cycle may correspond to the cycle T _N of the horizontal synchronization signal Hsync in the timing diagram shown in FIG. When the Nth cycle T _N starts, the controller 400 turns on the first switch 241 and outputs the data voltage VD [N] stored in the buffer 243 to the data line DL (S11 ).

While the data voltage VD [N] is output, the latch 220 can receive the new digital image data DATA [N + 1] (S12). The digital image data DATA [N + 1] received in step S12 may be stored in the latch 220 and converted into a new data voltage VD [N + 1] by the digital-analog converter 230. The controller 400 may turn off the second switch 242 to prevent the new data voltage VD [N + 1] generated by the digital-to-analog converter 230 from being reflected in the output of the buffer 243 .

The controller 400 can determine whether the output of the data voltage VD [N] stored in the buffer 243 is terminated (S13). If it is determined in step S12 that the output of the data voltage VD [N] has not ended, the controller 400 continues to turn on the first switch 241 to turn on the data voltage VD [N] stored in the buffer 243, To the data line DL

On the other hand, if it is determined in step S13 that the output of the data voltage VD [N] is completed, the controller 400 turns off the first switch 241 to electrically connect the buffer 243 and the data line DL (S14). Next, the controller 400 may turn on the second switch 242 to store the data voltage VD [N + 1] output from the digital-to-analog converter 230 in the buffer 243 (S15). Data voltage is stored in Step S14 to the buffer (243) VD [N + 1 ] is, N th period T _N, and then coming N + 1 voltage to be inputted to the second period T _{N + 1} for a data line (DL) one to the .

The controller 400 may store the data voltage VD [N + 1] in the buffer 243 and check whether the _Nth cycle T _N is completed (S16). If it is determined in step S16 that the Nth cycle T _N has not ended, the controller 400 may continuously store the data voltage VD [N + 1] in the buffer 243. The number of buffers 243 may correspond to the number of data lines DL and the data driver 200 may include a plurality of buffers 243. [ Accordingly, the controller 400 can store the data voltage VD [N + 1] output from the digital-analog converter 230 in each of the plurality of buffers 243 until the _Nth cycle T _N ends.

If it is determined in step S16 that the Nth cycle T _N is ended and the (N + 1) th cycle T _{N + 1} is started, the controller 400 turns on the first switch 241 to turn on the buffer 243 The stored data voltage VD [N + 1] can be output to the data line DL (S11). The output of the buffer 243 having a relatively slow slew rate is updated in advance during the _Nth cycle T _N which is the previous cycle to charge the pixel PX through the data line DL in the ( _{N + 1} ) Sufficient time can be ensured.

On the other hand, in the embodiment shown in FIG. 9, step S13 may be replaced with a step of determining whether or not the controller 400 has received the new digital image data DATA [N + 1]. In this case, the controller 400 can determine whether or not the reception of the new digital video data DATA [N + 1] is completed using the data enable signal DE as shown in Fig.

10 is a block diagram showing an electronic apparatus to which a display device according to an embodiment of the present invention can be applied.

10, an electronic device 1000 according to an embodiment of the present invention includes a display device 1010, a memory 1020, a communication module 1030, a sensor module 1040, and a processor 1050, . The electronic device 1000 may include a television, a desktop computer, etc. in addition to mobile devices such as smart phones, tablet PCs, laptop computers, and the like. Components such as the display device 1010, the memory 1020, the communication module 1030, the sensor module 1040 and the processor 1050 can communicate with each other via the bus 1060.

Display device 1010 may include a display driver according to various embodiments of the present invention. The display device 1010 according to the embodiment of the present invention can store in advance the data voltage to be output to the data line in each scan period of the gate line in the buffer of the data driver in the previous scan period. Therefore, the slew time required to change the output of the buffer to the data voltage in each scan period of the gate line can be minimized, thereby improving the image quality of the display device 1010 and reducing the power consumption of the display device 1010 Can be driven.

The present invention is not limited to the above-described embodiment and the accompanying drawings, but is intended to be limited by the appended claims. It will be apparent to those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. something to do.

10: Display device
20: Display driving device
30: Display panel
100, 200: data driver
110, 210: Shift register
120, 320: latch
130, 330: Digital-analog conversion circuit
140, 340: buffer circuit
300: gate driver
400: controller

Claims (20)

A digital-to-analog converter for generating analog image data;
A plurality of pads connected to a plurality of data lines included in the display panel;
A plurality of buffers for receiving the analog video data and generating a data voltage, a first switch connected between an output end of the plurality of buffers and the plurality of pads, and a second switch connected between the input terminals of the plurality of buffers and the digital- A buffer circuit having a second switch connected thereto; And
When the data voltage is output to the plurality of data lines through the plurality of pads, turning off the first switch and turning on the second switch to turn the output of at least some of the plurality of buffers to a new data voltage ; And the display driver.
The method according to claim 1,
Wherein the plurality of buffers receive the analog image data generated by the digital-analog converter every predetermined period to generate the data voltage.
3. The method of claim 2,
Wherein the controller turns off the first switch and turns on the second switch after the completion of outputting the data voltage for each of the periods to output the output of at least a part of the plurality of buffers to the plurality of To a new data voltage to be output to the data line.
The method of claim 3,
Wherein the controller turns on the first switch when the next period arrives and outputs the new data voltage to the plurality of data lines.
The method of claim 3,
Wherein the controller sets the output of the plurality of buffers as the new data voltage by turning on the second switch when the next period arrives.
The method according to claim 1,
And the controller repeatedly turns on and off the second switch while turning off the first switch.
The method according to claim 1,
A latch circuit for sampling and storing digital image data corresponding to the analog image data; And
A shift register for controlling the sampling timing of the latch circuit so that the digital image data is sequentially stored in the latch circuit; And the display driver.
8. The method of claim 7,
Wherein the controller generates first and second control signals for controlling each of the first and second switches,
And the latch circuit transmits the digital image data to the digital-analog converter in accordance with the second control signal.
8. The method of claim 7,
Wherein the controller transmits a third control signal to the shift register to determine a cycle at which the plurality of buffers output the data voltage.
The method according to claim 1,
The display panel includes a plurality of first pixels arranged in a region where a first gate line intersects with the plurality of data lines and a plurality of second pixels arranged in a region where a second gate line crosses the plurality of data lines Pixels,
Wherein the plurality of buffers inputs a first data voltage to the plurality of first pixels during a first period in which the first gate line is activated and a second data voltage to the plurality of second pixels during a second period in which the second gate line is activated, And the second data voltage is input to the second data line.
11. The method of claim 10,
And the controller sets the output of at least a part of the plurality of buffers as the second data voltage during the first period.
A latch circuit for sampling and storing digital image data;
A shift register for controlling a sampling timing of the latch circuit;
A digital-analog converter for generating analog image data based on the digital image data stored by the latch circuit;
A plurality of buffers for receiving the analog video data and generating a data voltage; And
A plurality of pads connecting an output end of each of the plurality of buffers to a plurality of data lines; / RTI >
Wherein the data voltages output by at least some of the plurality of buffers are output to the plurality of data lines via the plurality of pads after a predetermined delay time has elapsed.
13. The method of claim 12,
Wherein the latch circuit includes a plurality of latches, and the plurality of latches sequentially samples and stores the digital image data based on the sampling timing controlled by the shift register.
13. The method of claim 12,
And during the delay time, at least some of the plurality of buffers output the data voltages different from the plurality of pads.
13. The method of claim 12,
A plurality of first switches connecting the plurality of buffers to the plurality of pads;
A plurality of second switches for connecting the plurality of buffers to the digital-analog converter; And
A controller for controlling the plurality of first and second switches; And the display driver.
16. The method of claim 15,
The controller turns off the plurality of first switches and turns on at least some of the plurality of second switches during the delay time.
17. The method of claim 16,
Wherein at least some of the plurality of buffers store the data voltage during the delay time.
A display panel having a plurality of first pixels arranged along a first gate line and a plurality of second pixels arranged along a second gate line;
And a plurality of buffers for outputting a first data voltage to the plurality of first pixels during a first period and outputting a second data voltage to the plurality of second pixels during a second period following the first period Lt; / RTI > And
A controller for, during the first period, updating an output of at least a portion of the plurality of buffers to the second data voltage; .
19. The method of claim 18,
The data driver includes:
A digital-to-analog converter for generating first and second analog image data necessary to generate each of the first and second data voltages;
A latch circuit for sampling and storing first and second digital image data necessary for generating the first and second analog image data, respectively; And
A shift register for controlling a sampling timing of the latch circuit; / RTI >
Wherein each of the plurality of buffers has an output terminal connected to the plurality of first pixels and the second pixel through a first switch and an input terminal connected to the digital-analog converter through a second switch.
20. The method of claim 19,
Wherein said controller turns off said first switch and turns said second switch on when said latch circuit has completed sampling and storing said second digital image data for said first period of time, And updates at least a part of the output to the second data voltage.

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