KR20170000633A - Semiconductor device - Google Patents

Abstract

A semiconductor device improved in device isolation characteristics is provided. A pin protruding from the substrate and extending in a first direction; First and second gate structures disposed crossing the pin; A recess formed in the fin between the first and second gate structures; An element isolation film which fills the recess and protrudes on the pin and has an upper surface located on the same plane as the upper surfaces of the first and second gate structures; A liner formed along an upper region of the device isolation film; And a source / drain region disposed on both sides of the recess and spaced apart from the device isolation film.

Description

Technical Field [0001] The present invention relates to a semiconductor device,

The present invention relates to a semiconductor device.

As one of the scaling techniques for increasing the density of a semiconductor device, a multi-channel active pattern (or a silicon body) in the form of a fin or a nanowire is formed on a substrate and a multi- A multi-gate transistor for forming a gate has been proposed.

Since such a multi-gate transistor uses a three-dimensional channel, scaling is easy. Further, the current control capability can be improved without increasing the gate length of the multi-gate transistor. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively suppressed.

A problem to be solved by the present invention relates to a semiconductor device which improves isolation characteristics.

Another problem to be solved by the present invention is to provide a semiconductor device that prevents shorts and epitaxially grows the source / drain without abnormality and improves the operating characteristics.

The technical objects of the present invention are not limited to the technical matters mentioned above, and other technical subjects not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a fin protruding from a substrate and extending in a first direction; First and second gate structures disposed crossing the pin; A recess formed in the fin between the first and second gate structures; Filling the recess, and projecting onto the pin. An element isolation layer having an upper surface located on the same plane as the upper surfaces of the first and second gate structures; A liner formed along an upper region of the device isolation film; And a source / drain region disposed on both sides of the recess, the source / drain region being spaced apart from the isolation film.

In some embodiments of the present invention, the device isolation film includes a first device isolation film disposed in the recess and a second device isolation film disposed in the upper region, wherein a width of the first device isolation film is larger than a width May be narrower than the width of the device isolation film.

In some embodiments of the present invention, the first isolation film and the second isolation film may be formed of different materials.

In some embodiments of the present invention, the spacer may further include a spacer formed between the second isolation film and the fin and in contact with the sidewall of the first isolation film.

In some embodiments of the present invention, the spacer may be disposed between the source / drain region and the device isolation film.

In some embodiments of the present invention, the lower surface of the liner may contact the upper surface of the spacer.

In some embodiments of the present invention, the upper surface of the spacer and the upper surface of the first isolation film may be coplanar.

In some embodiments of the present invention, the lower surface of the recess may be lower than the lower surface of the source / drain region.

In some embodiments of the present invention, the liner may extend upward along the sidewall of the device isolation film and be in contact with the same plane as the upper surface of the device isolation film.

In some embodiments of the present invention, the device further comprises an interlayer insulating film covering the fin between the first gate structure and the device isolation film, and between the second gate structure and the device isolation film, And may be located on the same plane as the upper surface of the device isolation film.

According to another aspect of the present invention, there is provided a semiconductor device including: a pin extending in a first direction in a shape protruding from a substrate; A recess formed in the fin; Filling the recess and forming a first device isolation film; A second isolation layer formed on the first isolation layer and having a width different from that of the first isolation layer; A source / drain region disposed on both sides of the recess, the source / drain region being spaced apart from the isolation film; A spacer disposed between the first isolation layer and the source / drain region; And a liner surrounding the sidewalls of the second isolation film.

In some embodiments of the present invention, the first device isolation film and the second device isolation film may be different materials.

In some embodiments of the present invention, the upper surface of the spacer may contact the lower surface of the liner.

In some embodiments of the present invention, the spacer and the liner may be different materials.

In some embodiments of the present invention, the upper surface of the spacer and the upper surface of the first isolation film may be coplanar.

The details of other embodiments are included in the detailed description and drawings.

1 is a perspective view of a semiconductor device according to an embodiment of the present invention.
Fig. 2 is a cross-sectional view taken along line A-A in Fig. 1; Fig.
FIGS. 3 to 21 are intermediate steps for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention.
22 is a diagram showing an intermediate step for explaining a semiconductor device according to another embodiment of the present invention.
23 is a diagram showing an intermediate step for explaining a semiconductor device according to another embodiment of the present invention.
24 is a diagram showing an intermediate step for explaining a semiconductor device according to another embodiment of the present invention.
25 to 30 are sectional views showing various shapes of a second recess included in semiconductor devices according to embodiments of the present invention.
31A is a circuit diagram for explaining a semiconductor device according to some embodiments of the present invention.
Fig. 31B is a layout diagram of the semiconductor device shown in Fig. 31A.
32 is a block diagram of an SoC system including a semiconductor device according to embodiments of the present invention.
33 is a block diagram of an electronic system including a semiconductor device according to embodiments of the present invention.
Figures 34-36 are exemplary semiconductor systems to which a semiconductor device according to some embodiments of the present invention may be applied.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. The dimensions and relative sizes of the components shown in the figures may be exaggerated for clarity of description. Like reference numerals refer to like elements throughout the specification and "and / or" include each and every combination of one or more of the mentioned items.

It is to be understood that when an element or layer is referred to as being "on" or " on "of another element or layer, All included. On the other hand, a device being referred to as "directly on" or "directly above" indicates that no other device or layer is interposed in between.

The terms spatially relative, "below", "beneath", "lower", "above", "upper" May be used to readily describe a device or a relationship of components to other devices or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions. The elements can also be oriented in different directions, so that spatially relative terms can be interpreted according to orientation.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. The terms " comprises "and / or" comprising "used in the specification do not exclude the presence or addition of one or more other elements in addition to the stated element.

Although the first, second, etc. are used to describe various elements or components, it is needless to say that these elements or components are not limited by these terms. These terms are used only to distinguish one element or component from another. Therefore, it is needless to say that the first element or the constituent element mentioned below may be the second element or constituent element within the technical spirit of the present invention.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

A semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG.

FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line A-A of FIG. In FIG. 1, the first and second interlayer insulating films 131 and 132 are omitted.

1 and 2, a semiconductor device according to an embodiment of the present invention includes a substrate 101, first to third pins F1, F2, and F3, a field insulating film 110, a recess 141b, The first and second gate structures 151a and 151b, the liner 138a, the gate spacer 115, the spacer 115a, the first to the second gate structures 151a and 151b, The first and second interlayer insulating films 131 and 132, the silicide film 161, the contact 163, and the like. Meanwhile, in the present invention, the first and second isolation films 175 and 177 can form an isolation film.

Specifically, the substrate 101 may be made of one or more semiconductor materials selected from the group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP. A silicon on insulator (SOI) substrate may also be used.

The first to third pins F1 to F3 may protrude from the substrate 101 in the third direction Z1. The first to third pins F1 to F3 may each extend in the longitudinal direction, that is, along the first direction X1. The first to third pins F1 may have a long side and a short side. The first to third pins F1 to F3 may be disposed on the substrate 101 so as to be spaced apart from each other. For example, the first to third pins F1 to F3 may be spaced apart in the second direction Y1. In Fig. 1, the long side direction is shown as a first direction (X1) and the short side direction is shown as a second direction (Y1), but the present invention is not limited thereto. For example, the first to third pins F1 to F3 may have a long side direction in a second direction Y1 and a short side direction in a first direction X1.

The first to third pins F1 to F3 may be a part of the substrate 101 or may include an epitaxial layer grown from the substrate 101. [ The first to third pins F1 to F3 may include, for example, Si or SiGe. The field insulating film 110 is formed on the substrate 100 and can cover a part of the side wall of the fin F1 and expose the top of the fin F1. The field insulating film 110 may be, for example, an oxide film.

The first and second gate structures 151a and 151b, and the first and second isolation films 175 and 175 are disposed apart from each other. Each of the first and second gate structures 151a and 151b and the first and second isolation layers 175 and 175 may intersect the first to third pins F1 to F3. The second device isolation film 177 is disposed on the first device isolation film 175. As described above, the first and second element isolation films 175 and 177 can form an element isolation film. Therefore, the upper region of the device isolation film may be the second device isolation film 177, and the lower region of the device isolation film may be the first device isolation film 175.

 1, the first and second gate structures 151a and 151b and the first and second isolation layers 175 and 177 extend in the second direction Y1. However, the present invention is not limited thereto. And the first and second gate structures 151a and 151b and the first and second isolation layers 175 and 177 are connected to the first to third pins F1 to F3 at acute or obtuse angles with the first to third pins F1 to F3, F3).

Each of the first to third pins F1 to F3 is formed with a recess 141b aligned in the second direction Y1. The recess 141b is formed in the first to third pins F1 to F3. The lower surface of the recess 141b is lower than or equal to the lower surface of the first to third source / drain regions 121, 123, In FIG. 2, the recess 141b has a trench shape that becomes narrower as it goes down from the upper portion to the lower portion. However, the present invention is not limited thereto, and the recess 141b may have a U- V-shaped, rectangular, trapezoidal, and the like.

The first device isolation film 175 may fill the recess 141b. The first device isolation film 175 may be formed on the field insulating film 110 and may be formed in the first to third pins F1 to F3. The lower surface of the first element isolation layer 175 is lower than the lower surface of the first to third source / drain regions 121, 123, and 125 because the first element isolation layer 175 fills the recess 141b. The first isolation film 175 may be separated from the source / drain regions 123 formed on both sides of the first isolation film 175 to prevent a short circuit and to prevent a current from flowing. The first isolation layer 175 may be, for example, an oxide layer, a nitride layer, an oxynitride layer, or the like, but is not limited thereto. The first isolation layer 175 is spaced apart from the first to third source / drain regions 121, 123 and 125.

On the other hand, the second isolation film 177 may be formed on the first isolation film 175. The width of the lower surface of the second isolation film 177 may be greater than the width of the upper surface of the first isolation film 175. [ The second device isolation film 177 and the first device isolation film 177 may be formed of different materials, but the present invention is not limited thereto. The second isolation layer 177 may be, for example, TOSZ (Tonen Sila Zene) or the like, but is not limited thereto.

The upper surfaces of the first and second gate structures 151a and 151b and the upper surface of the second element isolation film 177 may be located on the same plane.

The first and second gate structures 151a and 151b may include first and second gate insulating layers 153a and 153b and first and second gate electrodes 155a and 155b, respectively.

Each of the first and second gate insulating films 153a and 153b may be formed between the first to third pins F1 to F3 and the first and second gate electrodes 155a and 155b. As shown in FIG. 4, each of the first and second gate insulating films 153a and 153b may be formed on the upper surface and the upper surface of the first to third pins F1 to F3. The first and second gate insulating films 153a and 153b may be disposed between the first and second gate electrodes 155a and 155b and the field insulating film 110, respectively. The first and third gate insulating films 153a and 153b may include a high dielectric constant material having a higher dielectric constant than the silicon oxide film. For example, the first and second gate insulating films 153a and 153b may include HfO ₂ , ZrO ₂ , LaO, Al ₂ O 3, or Ta ₂ O ₅ .

Each of the first and second gate electrodes 155a and 155b may include first and second metal layers MG1 and MG2. As shown, each of the first and second gate electrodes 155a and 155b may be formed by stacking two or more first and second metal layers MG1 and MG2. The first metal layer MG1 controls the work function and the second metal layer MG2 functions to fill a space formed by the first metal layer MG1. The first metal layer MG1 may be conformally formed on the upper surface of the field insulating layer 110, the upper surfaces of the first to third pins F1 to F3, and the upper portion of the sidewalls, as shown in FIG. For example, the first metal layer MG1 may include at least one of TiN, TaN, TiC, TiAlC, and TaC. In addition, the second metal layer MG2 may include W or Al. Alternatively, the first to third gate electrodes 155a and 155b may be made of Si, SiGe or the like instead of a metal. The first and second gate structures 151a and 151b may be formed through, for example, a replacement process, but are not limited thereto.

The first and second gate structures 151a and 151b may be formed at the same time, and the details will be described later.

The gate spacers 115 may be formed on the sidewalls of the first and second gate structures 151a and 151b. The gate spacers 115 are disposed on the first to third pins F1 to F3 and not on the recesses 143. [ The gate spacer 115 may include at least one of, for example, an oxide layer, a nitride layer, and an oxynitride layer, and may be formed by stacking a plurality of layers rather than a single layer, as shown in the drawings.

On the other hand, the liner 138a may be formed on the side wall of the second isolation film 177. The spacer 115a may be formed on the upper sidewall of the first isolation film 175. [ A liner 138a may be formed on the spacer 115a. That is, the upper surface of the spacer 115a and the lower surface of the liner 138a can contact each other. The spacer 115a may include at least one of, for example, an oxide film, a nitride film, and an oxynitride film, and the liner 138a may include an oxide film, but is not limited thereto.

The first to third source / drain regions 121, 123 and 125 may be disposed on both sides of the first and second gate structures 151a and 151b and the first and second isolation films 175 and 177 . In other words, the first to third source / drain regions 121, 123, and 125 are formed between the first gate structure 151a and the first and second isolation layers 175 and 177, the second gate structure 151b, And may be disposed between the first and second isolation films 175 and 177. The first to third source / drain regions 121, 123, and 125 may be disposed in the first to third pins F1 to F3. Accordingly, the first to third source / drain regions 121, 123, and 125 partially etch the first to third fins F1 to F3, and the first to third source / drain regions 121, 123, and 125 may be formed.

Although the first to third source / drain regions 121, 123 and 125 are illustrated as being in contact with each other in FIG. 1, the present invention is not limited thereto, and the first to third source / 125 may be spaced apart from one another.

The first to third source / drain regions 121, 123, and 125 may be elevated source / drain regions. Therefore, the upper surfaces of the first to third source / drain regions 121, 123, and 125 may be higher than the upper surfaces of the first to third pins F1 to F3.

When the semiconductor device according to an embodiment of the present invention is a PMOS transistor, the first to third source / drain regions 121, 123, and 125 may include a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than Si, and may be, for example, SiGe. The compressive stress material increases the mobility of carriers in the channel region by applying a compressive stress to the first to third pins F1 to F3, that is, the channel region under the first and second gate structures 151a and 152b. .

The first to third source / drain regions 121, 123, and 125 may include the same material as the substrate 101, or a tensile stress material, when the semiconductor device according to one embodiment of the present invention is an NMOS transistor . For example, when the substrate 101 is Si, the first to third source / drain regions 121, 123, and 125 may be Si or a material having a smaller lattice constant than Si (e.g., SiC, SiP) .

The first to third source / drain regions 121, 123, and 125 may be formed by epitaxial growth.

A silicide film 161 is disposed on the first to third source / drain regions 121, 123, and 125. The silicide film 161 may be formed along the upper surfaces of the first to third source / drain regions 121, 123, and 125. The silicide film 161 may reduce the surface resistance and the contact resistance when the first to third source / drain regions 121, 123 and 125 are in contact with the contact 163, For example, Pt, Ni, Co, or the like.

On the silicide film 161, a contact 163 is formed. The contact 163 may be formed of a conductive material and may include, for example, W, Al Cu, and the like, but is not limited thereto

The first interlayer insulating film 131 and the second interlayer insulating film 132 are sequentially formed on the field insulating film 110. The first interlayer insulating film 131 covers the sidewalls of the silicide film 161 and the gate spacers 115 and may cover a part of the side walls of the contacts 163. [ The second interlayer insulating film 131 may cover the remaining side wall of the contact 163.

2, the upper surface of the first interlayer insulating film 131 is located on the same plane as the upper surfaces of the first and second gate structures 151a and 151b and the first and second isolation films 175 and 177 can do. The upper surface of the first interlayer insulating film 181 and the upper surfaces of the first and second gate electrodes 151a and 151b and the first and second isolation films 175 and 177 are planarized by a planarization process (for example, a CMP process) Can be aligned. The second interlayer insulating film 132 may be formed to cover the first and second gate structures 151a and 151b and the first and second isolation films 175 and 177. [ The first interlayer insulating film 131 and the second interlayer insulating film 132 may include at least one of an oxide film, a nitride film, and an oxynitride film.

Meanwhile, the spacer 115a, the liner 138a, and the interlayer insulating layers 131 and 132 may include the same material or may include different materials.

3 to 21, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described.

FIGS. 3 to 21 are intermediate steps for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention. 3, 4, 5, 8, 9 and 11 are perspective views, and FIGS. 6, 10 and 12 to 21 are sectional views taken along line A-A of FIGS. 5 and 9 And Fig. 7 is a cross-sectional view taken along line B-B in Fig.

Referring to FIG. 3, first to third pins F1 to F3 are formed on a substrate 101. In FIG. The first to third pins F1 to F3 are formed on the substrate 101 and can protrude in the third direction Z1. The first to third pins F1 to F3 may extend along the first direction X1 which is the longitudinal direction and may have the long side of the first direction X1 and the short side of the second direction Y1 . However, the present invention is not limited thereto. For example, the long side direction may be the second direction Y1 and the short side direction may be the first direction X1. The first to third pins F1 to F3 may be disposed apart from each other.

The first to third pins F1 to F3 may be a part of the substrate 101 or may include an epitaxial layer grown from the substrate 101. [ For example, Si or SiGe.

Referring to FIG. 4, an insulating layer 110a is formed to cover the sidewalls of the first to third pins F1 to F3. The field insulating film 110a may be formed of a material including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

5 to 7, the upper portion of the insulating film 110a is recessed to form the field insulating film 110, and the upper portions of the first to third pins F1 to F3 are exposed. The recess process may include an optional etch process.

Meanwhile, a part of the first to third pins F1 to F3 protruded above the field insulating film 110 may be formed by an epitaxial process. For example, after the formation of the insulating film 110a, the first to third pins F1 to F3 exposed by the insulating film 110a without a recess process are epitaxially grown on the upper surfaces of the first to third pins F1 to F3, A part of the pins F1 to F3 may be formed.

Also, doping for threshold voltage adjustment can be performed on the exposed first to third pins F1 to F3. For example, when the NMOS transistor is formed, the impurity may be boron (B), and when forming the PMOS transistor, the impurity may be phosphorus (P) or arsenic (As).

Then, first to third sacrificial gate structures 111a, 111b and 111c crossing the first to third pins F1 to F3 are formed on the first to third pins F1 to F3. The first to third sacrificial gate structures 111a, 111b, and 111c are spaced apart from each other. 28, the first through third sacrificial gate structures 111a, 111b, and 111c are shown as crossing the first through third pins F1 through F3 at right angles, that is, in the first direction X1, The first to third sacrificial gate structures 111a, 111b and 111c may be formed by intersecting the first to third pins F1 to F3 at an acute angle and / or an obtuse angle with the first direction X1, can do.

The first to third sacrificial gate structures 111a, 111b and 111c may be formed on the upper surfaces of the first to third pins F1 to F3 and on the sidewalls. Also, the first to third sacrificial gate structures 111a, 111b, and 111c may be disposed on the field insulating film 110. The first to third sacrificial gate structures 111a, 111b, and 111c may be, for example, a silicon oxide film.

The first to third hard mask films 113a, 113b, and 113c may be formed on the first to third sacrificial gate structures 111a, 111b, and 111c, respectively. The first to third hard mask films 113a, 113b, and 113c may be formed of a material including at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

Next, gate spacers 115 are formed on both side walls of the first to third sacrificial gate structures 111a, 111b, and 111c. The gate spacer 115 may expose the upper surfaces of the first to third hard mask films 113a, 113b, and 113c. The gate spacer 115 may be a silicon nitride film or a silicon oxynitride film.

Referring to FIG. 8, the first to third pins F1 to F3 are etched. The remaining portions of the first to third pins F1 to F3 are etched except for the portion covered with the first to third sacrificial gate structures 111a, 111b and 111c. Accordingly, the first to third pins F1 to F3 exposed between the first to third sacrificial gate structures 111a, 111b and 111c can be etched. The first to third pins F1 to F3 may be etched using the gate spacer 115 and the first to third hard mask films 113a to 113c as an etch mask.

Referring to FIGS. 9 and 10, the first to third source / drain regions 121, 123 and 125 are formed in the etched portions of the first to third pins F1 to F3. A first source / drain region 121 is formed in the first fin F1, a second source / drain region 123 is formed in the second fin F2 and a third source / drain region 123 is formed in the third fin F3. 125 may be formed. The first to third source / drain regions 121, 123, and 125 may be elevated source / drain regions. Therefore, the upper surfaces of the first to third source / drain regions 121, 123, and 125 may be higher than the upper surfaces of the first to third pins F1 to F3.

When the semiconductor device according to an embodiment of the present invention is a PMOS transistor, the first to third source / drain regions 121, 123, and 125 may include a compressive stress material. For example, the compressive stress material may be a material having a larger lattice constant than Si, and may be, for example, SiGe. The compressive stress material increases the mobility of carriers in the channel region by applying a compressive stress to the first to third pins F1 to F3, that is, the channel region under the first and second gate structures 151a and 152b. .

When the semiconductor device according to an embodiment of the present invention is an NMOS transistor, the first to third source / drain regions 123 and 125 may include a tensile stress material. The first to third source / drain regions 121, 123, and 125 may be the same material as the substrate 101 or a tensile stress material. For example, when the substrate 101 is Si, the first to third source / drain regions 121, 123, and 125 may be Si or a material having a smaller lattice constant than Si (e.g., SiC, SiP) .

The first to third source / drain regions 121, 123, and 125 may be formed by epitaxial growth.

Although the first to third source / drain regions 121, 123 and 125 are shown as being in contact with each other in FIG. 9, the present invention is not limited thereto, and the first to third source / 123, and 125 may be spaced apart from each other.

Referring to FIGS. 11 and 12, a first interlayer insulating film 131 covering the first to third source / drain regions 121, 123, and 125 is formed. The first interlayer insulating film 131 may cover the sidewall of the gate spacer 115 and expose the upper surfaces of the first to third hard mask films 113a, 113b, and 113c. The first interlayer insulating film 131 may include, for example, an oxide film.

Referring to FIG. 13, the first to third hard mask films 113a, 113b, and 113c are removed. A planarization process (for example, a CMP process) may be performed to remove the first to third hard mask films 113a, 113b, and 113c, and the first interlayer insulating film 131 is partially etched when the planarization process is performed .

After the planarization process is performed and the cleaning process is performed, residues and the like generated by the planarization process can be removed. At this time, the first interlayer insulating film 131 may be partially removed, so that the upper surface of the first interlayer insulating film 131 may be lower than the upper surfaces of the first through third sacrificial gate structures 111a, 111b, and 111c. 14, the upper surface of the first interlayer insulating layer 131 is located on the same plane as the upper surfaces of the first through third sacrificial gate structures 111a, 111b, and 111c .

Referring to FIG. 14, a protective film 133 is formed to cover the top surfaces of the first interlayer insulating film 131 and the first through third sacrificial gate structures 111a, 111b, and 111c. The protective film 133 can prevent the first interlayer insulating film 131 from being etched in a subsequent process. The protective film 133 may include, for example, a nitride film, an oxynitride film, and the like.

Further, a buffer film 135 is formed on the protective film 133. The buffer film 135 can offset a step generated while the protective film 133 is formed. The buffer layer 135 may include the same material as the first interlayer insulating layer 131.

Referring to FIG. 15, an etch mask pattern 137a is formed on the protective film 133. FIG. The etching mask pattern 137a may expose the upper portion of the second sacrificial gate structure 111b and cover the remaining portion.

Referring to FIG. 16, a part of the second sacrificial gate structure 111b may be removed. In addition, the second sacrificial gate structure 111b and a portion of the gate spacer 115 adjacent to the second sacrificial gate structure 111b may be removed to form the spacer 115a.

In the present embodiment, a part of the second sacrificial gate structure 111b is removed, but the present invention is not limited thereto. Thus, all of the second sacrificial gate structures 111b can be removed. In the present embodiment, the second sacrificial gate structure 111b and a portion of the gate spacer 115 adjacent to the sacrificial gate structure 111b are removed. However, the present invention is not limited thereto. Therefore, the second sacrificial gate structure 111b and the adjacent gate spacers 115 can be completely removed or entirely removed.

The protective film 133 on the second sacrificial gate structure 111b is first removed using the etch mask pattern 137a and then a part of the second sacrificial gate structure 111b is removed.

17, all the remaining portions of the second sacrificial gate structure 111b are removed and a first recess 141a is formed.

The first to third pins F1 to F3 may be exposed by the first recess 141a.

Referring to Fig. 18, a liner 138 is formed. The liner 138 may be conformally formed along the top and sidewalls of the buffer film 155, the top and side walls of the spacer 115a, and the top surfaces of the first to third pins F1 to F3. The liner 138 may include at least one of an oxide film, a nitride film, and an oxynitride film.

Referring to FIG. 19, the liner 138 is etched to expose the first to third pins F1 to F3 again. The liner 138a may remain on the side wall of the first interlayer insulating film 131 and on the upper surface of the spacer 115 through an etch-back process or the like. The liner 138 may be disposed on the side wall of the first recess 141a.

The exposed first through third fins F1 through F3 are etched to form a second recess 141b under the first recess 141a. Although not shown, a portion of the spacer 115 and a portion of the liner 138 may also be etched while forming the second recess 141b. The lower surface of the second recess 141b is lower than the lower surfaces of the first to third source / drain regions 121, 123 and 125.

In FIG. 19, the second recess 141b has a trench shape that becomes narrower from the upper portion to the lower portion. However, the second recess 141b may have various shapes. This will be described later.

Referring to FIG. 20, a first device isolation film 175 filling the second recess 141b is formed. The first element isolation film 175 may be, for example, an oxide film, a nitride film, an oxynitride film, or the like.

Referring to FIG. 21, a second isolation layer 177 is formed on the first isolation layer 175. The first element isolation film 175 may be, for example, TOSZ (TonenSilaZene) or the like. The lower surface of the second element isolation film 177 can contact the upper surface of the spacer 115a and at the same time can contact the liner 138a at the side wall.

The protective film 133 covering the first and third sacrificial gate structures 111a and 111c and the buffer film 135 may be removed together through a planarization process or the like at the time of forming the second isolation film 177. [ The element isolation films 175 and 177 remain only in the first recess 141a and the second recess 141b.

Referring to FIGS. 1 and 2 again, the first and third sacrificial gate structures 111a and 111c are removed, and the first and third sacrificial gate structures 111a and 111c are removed. 2 gate structures 151a and 151b are formed.

The first and second gate structures 151a and 151b may include first and second gate insulating layers 153a and 153b and first and second gate electrodes 155a and 155b, respectively.

Each of the first and second gate insulating films 153a and 153b may be formed between the first to third pins F1 to F3 and the first and second gate electrodes 155a and 155b. Each of the first and second gate insulating films 153a and 153b may be formed along the sidewalls of the gate spacer 115 and the upper surfaces of the first to third pins F1 to F3. The first and third gate insulating films 153a and 153b may include a high dielectric constant material having a higher dielectric constant than the silicon oxide film. For example, the first and second gate insulating films 153a and 153b may include HfO ₂ , ZrO ₂ , LaO, Al ₂ O 3, or Ta ₂ O ₅ .

Each of the first and second gate electrodes 155a and 155b may include first and second metal layers MG1 and MG2. As shown, each of the first and second gate electrodes 155a and 155b may be formed by stacking two or more first and second metal layers MG1 and MG2. The first metal layer MG1 controls the work function and the second metal layer MG2 functions to fill a space formed by the first metal layer MG1. The first metal layer MG1 may be formed along the sidewalls of the gate spacer 115 and the upper surfaces of the first to third pins F1 to F3. For example, the first metal layer MG1 may include at least one of TiN, TaN, TiC, TiAlC, and TaC. In addition, the second metal layer MG2 may include W or Al. Alternatively, the first and second gate electrodes 155a and 155b may be made of Si, SiGe or the like instead of a metal.

Then, a second interlayer insulating film 132 is formed. The second interlayer insulating film 132 may cover the first interlayer insulating film 131, the first and second gate structures 151a and 151b, and the first and second element isolation films 175 and 177.

Subsequently, a silicide film 161 is formed on the first to third source / drain regions 121, 123, and 125, and a contact 163 is formed on the silicide film 161. In accordance with an embodiment of the present invention, A semiconductor device can be manufactured.

22 is a diagram showing an intermediate step for explaining a semiconductor device according to another embodiment of the present invention.

The intermediate stage diagram of the semiconductor device according to the present embodiment can correspond to the intermediate stage diagram of FIG. 21, among the intermediate stage diagrams according to the above-described one embodiment. The intermediate step of the semiconductor device according to the present embodiment is the same as the first embodiment except that one third isolation film 178 is formed in the first recess 141a and the second recess 141b, Is substantially the same as that of the semiconductor device according to the first embodiment. Therefore, repetitive description of the same components is omitted.

Referring to FIG. 22, a third isolation layer 178 may be formed in the first recess 141a and the second recess 141b. The third device isolation film 178 may include the same material as one of the first and second device isolation films 175 and 177 described above.

23 is a diagram showing an intermediate step for explaining a semiconductor device according to another embodiment of the present invention.

The intermediate stage diagram of the semiconductor device according to the present embodiment can correspond to the intermediate stage diagram of FIG. 17 among the intermediate stage diagrams according to the above-described one embodiment. The intermediate stage view of the semiconductor device according to the present embodiment is substantially the same as the semiconductor device according to the above embodiment except that a part of the gate spacer 115 in the first recess 141a is not removed Do. Therefore, repetitive description of the same components is omitted.

Referring to FIG. 23, a first isolation layer 175 may be formed in the second recess 141b, and a third isolation layer 178 may be formed in the first recess 141a. A gate spacer 115 may be disposed on the sidewall of the third isolation film 178. The upper surface of the third isolation film 178 and the upper surface of the gate spacer 115 may be arranged on the same plane. That is, the third isolation film 178 and the gate spacer 115 may have the same height.

24 is a diagram showing an intermediate step for explaining a semiconductor device according to another embodiment of the present invention.

The intermediate stage diagram of the semiconductor device according to the present embodiment can correspond to the intermediate stage diagram of FIG. 21, among the intermediate stage diagrams according to the above-described one embodiment. The intermediate diagram of the semiconductor device according to the present embodiment is substantially the same as the semiconductor device according to the embodiment described above except that the liner 138a in the first recess 141a is removed. Therefore, repetitive description of the same components is omitted.

Referring to Fig. 24, the liner 138a in the first recess 141a may be unseated. Therefore, the sidewall of the third isolation film 178 disposed in the first recess 141a can directly contact the first interlayer insulating film 131. [

25 to 30 are sectional views showing various shapes of a second recess included in semiconductor devices according to embodiments of the present invention.

The second recess 141b may have a V-shape as shown in Fig. 25, a rectangular prism as shown in Fig. 26, a trapezoid as shown in Fig. 27, an angular U-shape as shown in Fig. 28, a U- Shape. However, the present invention is not limited thereto.

31A is a circuit diagram for explaining a semiconductor device according to some embodiments of the present invention. Fig. 31B is a layout diagram of the semiconductor device shown in Fig. 31A.

Hereinafter, a description of the differences from the embodiments described above will be omitted and the differences will be mainly described.

31A, a semiconductor device includes a pair of inverters INV1 and INV2 connected in parallel between a power supply node VCC and a ground node VSS and a pair of inverters INV1 and INV2 connected in parallel between a power supply node VCC and a ground node VSS. And a first pass transistor PS1 and a second pass transistor PS2 coupled to the output node. The first pass transistor PS1 and the second pass transistor PS2 may be connected to the bit line BL and the complementary bit line BLb, respectively. The gates of the first pass transistor PS1 and the second pass transistor PS2 may be connected to the word line WL.

The first inverter INV1 includes a first pull-up transistor PU1 and a first pull-down transistor PD1 connected in series and a second inverter INV2 includes a second pull-up transistor PU2 and a second pull- And a transistor PD2. The first pull-up transistor PU1 and the second pull-up transistor PU2 are PFET transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 may be NFET transistors.

The first inverter INV1 and the second inverter INV2 are connected to the output node of the second inverter INV2 so that the input node of the first inverter INV1 is configured to constitute one latch circuit , The input node of the second inverter INV2 may be connected to the output node of the first inverter INV1.

31A and 31B, the first active pin 210, the second active pin 220, the third active pin 230, and the fourth active pin 240, which are spaced from each other, As shown in FIG. Here, the second active pin 220 and the third active pin 230 may have a shorter extension than the first active pin 210 and the fourth active pin 240.

The first gate electrode 251, the second gate electrode 252, the third gate electrode 253 and the fourth gate electrode 254 are elongated in the other direction and the first gate electrode 251, 4 gate electrode 254 may be formed to cross the first active pin 210 to the fourth active pin 240.

Specifically, the first gate electrode 251 completely intersects the first active pin 210 and the second active pin 220, and may partially overlap the end of the third active pin 230. The third gate electrode 253 completely intersects the fourth active pin 240 and the third active pin 230 and can partially overlap the end of the second active pin 220. The second gate electrode 252 and the fourth gate electrode 254 may be formed to cross the first active pin 210 and the fourth active pin 240, respectively.

As shown, the first pull-up transistor PU1 is defined around the region where the first gate electrode 251 and the second active pin 220 intersect and the first pull-down transistor PD1 is defined around the region where the first gate electrode 251 and the second active pin 220 intersect. And the first pass transistor PS1 is defined around the region where the second gate electrode 252 and the first active pin 210 intersect with each other . The second pull-up transistor PU2 is defined around the region where the third gate electrode 253 and the third active pin 230 intersect and the second pull-down transistor PD2 is defined around the third gate electrode 253 and the fourth The second pass transistor PS2 may be defined around the region where the fourth gate electrode 254 and the fourth active pin 240 intersect.

A source and a drain may be formed on both sides of the region where the first to fourth gate electrodes 251 to 254 and the first to fourth active pins 210, 220, 230, and 240 intersect with each other And a plurality of contacts 250 may be formed.

In addition, the first shared contact 261 can simultaneously connect the second active pin 220, the third gate line 253, and the wiring 271. The second shared contact 262 can simultaneously connect the third active pin 230, the first gate line 251, and the wiring 272.

At least one of the semiconductor devices according to the above-described embodiments of the present invention can be applied to the illustrated semiconductor device.

For example, the first pass transistor PS1 and the first pull-down transistor PD1 are separated from each other, or the second pass transistor PS2 and the second pull-down transistor PD2 are separated from each other. At least one of the semiconductor devices according to the embodiments of the present invention described above can be employed.

The above-described semiconductor device according to the embodiment of the present invention can be employed as the structure for forming the first and second pull-up transistors PU1 and PU2 and the first and second pull-down transistors PD1 and PD2 .

32 is a block diagram of an SoC system including a semiconductor device according to embodiments of the present invention.

Referring to FIG. 32, the SoC system 1000 includes an application processor 1001 and a DRAM 1060.

The application processor 1001 may include a central processing unit 1010, a multimedia system 1020, a bus 1030, a memory system 1040, and a peripheral circuit 1050.

The central processing unit 1010 can perform operations necessary for driving the SoC system 1000. [ In some embodiments of the invention, the central processing unit 1010 may be configured in a multicore environment that includes a plurality of cores.

The multimedia system 1020 may be used in the SoC system 1000 to perform various multimedia functions. The multimedia system 1020 may include a 3D engine module, a video codec, a display system, a camera system, a post-processor, and the like .

The bus 1030 can be used for data communication between the central processing unit 1010, the multimedia system 1020, the memory system 1040, and the peripheral circuit 1050. In some embodiments of the invention, such a bus 1030 may have a multi-layer structure. For example, the bus 1030 may be a multi-layer Advanced High-performance Bus (AHB) or a multi-layer Advanced Extensible Interface (AXI). However, the present invention is not limited thereto.

The memory system 1040 can be connected to an external memory (for example, DRAM 1060) by the application processor 1001 to provide an environment necessary for high-speed operation. In some embodiments of the invention, the memory system 1040 may include a separate controller (e.g., a DRAM controller) for controlling an external memory (e.g., DRAM 1060).

The peripheral circuit 1050 can provide an environment necessary for the SoC system 1000 to be smoothly connected to an external device (e.g., a main board). Accordingly, the peripheral circuit 1050 may include various interfaces for allowing an external device connected to the SoC system 1000 to be compatible.

The DRAM 1060 may function as an operation memory required for the application processor 1001 to operate. In some embodiments of the invention, the DRAM 1060 may be located external to the application processor 1001 as shown. Specifically, the DRAM 1060 can be packaged in an application processor 1001 and a package on package (PoP).

At least one of the elements of the SoC system 1000 may include the semiconductor device according to the embodiments of the present invention described above.

33 is a block diagram of an electronic system including a semiconductor device according to embodiments of the present invention.

33, an electronic system 1100 according to an embodiment of the present invention includes a controller 1110, an input / output device 1120, a memory device 1130, an interface 1140, and a bus 1150, bus). The controller 1110, the input / output device 1120, the storage device 1130, and / or the interface 1140 may be coupled to each other via a bus 1150. The bus 1150 corresponds to a path through which data is moved.

 The controller 1110 may include at least one of a microprocessor, a digital signal process, a microcontroller, and logic elements capable of performing similar functions. The input / output device 1120 may include a keypad, a keyboard, a display device, and the like. The storage device 1130 may store data and / or instructions and the like. The interface 1140 may perform the function of transmitting data to or receiving data from the communication network. Interface 1140 may be in wired or wireless form. For example, the interface 1140 may include an antenna or a wired or wireless transceiver.

Although not shown, the electronic system 1100 is an operation memory for improving the operation of the controller 1110, and may further include a high-speed DRAM and / or an SRAM. At this time, as the operation memory, for example, the semiconductor device according to the embodiment of the present invention described above can be employed. The semiconductor device according to the embodiment of the present invention described above may be provided in the storage device 1130 or may be provided as a part of the controller 1110, the input / output device 1120, I / O, and the like.

 Electronic system 1100 can be a personal digital assistant (PDA) portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player a music player, a memory card, or any electronic device capable of transmitting and / or receiving information in a wireless environment.

Figures 34-36 are exemplary semiconductor systems to which a semiconductor device according to some embodiments of the present invention may be applied.

Fig. 34 shows a tablet PC 1200, Fig. 35 shows a notebook 1300, and Fig. 36 shows a smartphone 1400. Fig. At least one of the semiconductor devices according to embodiments of the present invention may be used in such a tablet PC 1200, a notebook 1300, a smart phone 1400, and the like.

It will also be apparent to those skilled in the art that the semiconductor device according to some embodiments of the present invention may also be applied to other integrated circuit devices not illustrated. That is, although only the tablet PC 1200, the notebook computer 1300, and the smartphone 1400 have been described as examples of the semiconductor system according to the present embodiment, examples of the semiconductor system according to the present embodiment are not limited thereto. In some embodiments of the invention, the semiconductor system may be a computer, an Ultra Mobile PC (UMPC), a workstation, a netbook, a Personal Digital Assistant (PDA), a portable computer, a wireless phone, A mobile phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, A digital audio recorder, a digital audio recorder, a digital picture recorder, a digital picture player, a digital video recorder, ), A digital video player, or the like.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

101: substrate
110: field insulating film
111a, 111b, 111c: a sacrificial gate structure
113a, 113b, and 113c: a hard mask film
115, 116, 117: gate spacer
121, 123, 125: source / drain region
131: a first interlayer insulating film
132: second interlayer insulating film
133: Shield
135: buffer film
137: first etching mask pattern
138: etch stop film
139: second etching mask pattern
141a: First recess
141b: the second recess
175, 177: Element isolation film
151a, 151b: gate structure
152, 252: a dummy gate structure
161: silicide film
163: Contact
138a: Liner

Claims (10)

A pin protruding from the substrate and extending in a first direction;
First and second gate structures disposed crossing the pin;
A recess formed in the fin between the first and second gate structures;
An element isolation layer which fills the recess and protrudes on the fin and has an upper surface located on the same plane as the upper surfaces of the first and second gate structures;
A liner formed along an upper region of the device isolation film; And
And a source / drain region disposed on both sides of the recess, the source / drain region being spaced apart from the isolation film. The method according to claim 1,
Wherein the device isolation film includes a first device isolation film disposed in the recess and a second device isolation film disposed in the upper region, the width of the first device isolation film being narrower than the width of the second device isolation film. 3. The method of claim 2,
Wherein the first device isolation film and the second device isolation film are formed of different materials. 3. The method of claim 2,
And a spacer formed between the second isolation film and the fin and in contact with a sidewall of the first isolation film. 5. The method of claim 4,
And the spacer is disposed between the source / drain region and the device isolation film. 5. The method of claim 4,
And the lower surface of the liner contacts the upper surface of the spacer. 5. The method of claim 4,
Wherein the upper surface of the spacer and the upper surface of the first isolation film are located on the same plane. The method according to claim 1,
And the lower surface of the recess is lower than the lower surface of the source / drain region. The method according to claim 1,
Wherein the liner extends upward along a sidewall of the isolation film and is in contact with the same plane as the upper surface of the isolation film. The method according to claim 1,
Further comprising an interlayer insulating film which covers the fins between the first gate structure and the device isolation film and between the second gate structure and the device isolation film, wherein an upper surface of the layered insulating film is located on the same plane as the upper surface of the device isolation film A semiconductor device.

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