KR20160134483A - Solar cell and method for manufacturing the same - Google Patents

Abstract

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate; A first conductive type region and a second conductive type region formed on one surface of the semiconductor substrate; A passivation film formed on the conductive region and having a contact hole; A passivation layer formed on the conductive region within the contact hole, the passivation layer being formed on at least one of the inner surface of the contact hole and the passivation layer; And an electrode electrically connected to the conductive region through the contact hole with the protective film interposed therebetween.

Description

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solar cell and a manufacturing method thereof, and more particularly, to a back electrode type solar cell and a manufacturing method thereof.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such solar cells, various layers and electrodes can be fabricated by design. However, solar cell efficiency can be determined by the design of these various layers and electrodes. In order to commercialize solar cells, it is required to overcome low efficiency, and various layers and electrodes are required to be designed so as to maximize the efficiency of the solar cell.

On the photoelectric conversion portion, an insulating layer is formed in consideration of passivation characteristics, insulation characteristics, and the like. Thereafter, a contact hole is formed in the insulating layer to electrically connect the photoelectric conversion portion and the electrode, and an electrode is formed in the contact hole. As a method of forming the contact hole, various methods can be applied. Among them, when the electrode is miniaturized, a method of using a contact hole by irradiating the insulating layer with laser is applied. However, when a contact hole is formed by irradiating a laser beam, the heat generated by the laser directly reaches a portion of the photoelectric conversion portion in a portion where the contact hole is directly formed, so that the portion is damaged by heat and the characteristic of the portion is deteriorated Respectively.

The present invention relates to a solar cell having a high efficiency and a method of manufacturing the same, because no damage or degradation of characteristics occurs even when a laser application process is applied.

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate; A first conductive type region and a second conductive type region formed on one surface of the semiconductor substrate; A passivation film formed on the conductive region and having a contact hole; A passivation layer formed on the conductive region within the contact hole, the passivation layer being formed on at least one of the inner surface of the contact hole and the passivation layer; And an electrode electrically connected to the conductive region through the contact hole with the protective film interposed therebetween.

A solar cell according to an embodiment of the present invention includes: a semiconductor substrate; A first conductive type region and a second conductive type region formed on one surface of the semiconductor substrate; A passivation film formed on the conductive region and having a contact hole; A protective film formed on the conductive region in the contact hole; And an electrode electrically connected to the conductive region through the contact hole with the protective film interposed therebetween. The passivation film includes a first layer overlying the conductive region and a second layer overlying the first layer and comprising a different material than the first layer. The contact hole includes a first contact hole portion formed in the first layer and a second contact hole portion formed in the second layer and communicating with the first contact hole portion. The first contact hole includes a portion larger than the second contact hole or a step is located between the inner surface of the first contact hole and the inner surface of the second contact hole.

A method of manufacturing a solar cell according to an embodiment of the present invention includes: forming a conductive type region on a semiconductor substrate; Forming a passivation film having a contact hole on the conductive type region; Forming a passivation layer on the passivation layer and the conductive region exposed through the contact hole; And forming an electrode electrically connected to the conductive region through the contact hole of the passivation film with the protective film interposed therebetween.

In the solar cell and the manufacturing method thereof according to the present embodiment, the conductive type region and the electrode are connected to each other with a protective film interposed therebetween to improve the passivation property in the contact hole and to protect the conductive type region. In addition, the passivation layer may be formed as a separate layer in a separate process from the rear passivation layer, and the passivation layer may be formed to have a thickness smaller than that of the rear passivation layer. This makes it possible to maintain excellent electrical connection characteristics between the conductive type region and the electrode. At this time, the rear passivation film includes the first and second layers which are different materials, and the first contact hole portion formed in the first layer and the second contact hole portion formed in the second layer are formed in different processes, It is possible to effectively prevent the conductive type region from being damaged. Thus, efficiency and productivity of the solar cell can be improved.

1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention.
2 is a partial rear plan view of the solar cell shown in Fig.
3A to 3N are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
4 is a partial rear plan view of a solar cell according to another embodiment of the present invention.
5 is a cross-sectional view illustrating a portion of a solar cell according to another embodiment of the present invention.
6 is a cross-sectional view illustrating a portion of a solar cell according to another embodiment of the present invention.
7 is a cross-sectional view illustrating a portion of a solar cell according to another embodiment of the present invention.
8 is a cross-sectional view illustrating a portion of a solar cell according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

FIG. 1 is a cross-sectional view illustrating a solar cell according to an embodiment of the present invention, and FIG. 2 is a partial rear plan view of the solar cell shown in FIG. 1. FIG.

1 and 2, a solar cell 100 according to the present embodiment includes a semiconductor substrate 10, a tunneling layer 20 formed on one surface (hereinafter referred to as "rear surface") of the semiconductor substrate 10, A passivation film (hereinafter, referred to as a "rear passivation film") 40 having a contact hole 46 located on the conductive type region 32 and a conductive type region 32, 34 located on the tunneling layer 20, Formed on the conductive type regions 32 and 34 in the contact hole 46 and on the inner side of the contact hole 46 (i.e., the side surface of the rear passivation film 40 adjacent to the contact hole 46) And electrodes 42 and 44 electrically connected to the conductive regions 32 and 34 through the contact holes 46 of the rear passivation film 40 with the protective film 41 interposed therebetween. The conductive regions 32 and 34 include a first conductive type region 32 having a first conductivity type and a second conductive type region 34 having a second conductive type. Includes a first electrode 42 connected to the first conductive type region 32 and a second electrode 44 connected to the second conductive type region 34. The solar cell 100 may further include a passivation film (hereinafter, referred to as a "front passivation film") 24, an antireflection film 26, and the like disposed on the front surface of the semiconductor substrate 10. This will be explained in more detail.

The semiconductor substrate 10 may include a base region 110 having a second conductivity type including a second conductivity type dopant at a relatively low doping concentration. The base region 110 may be formed of a crystalline semiconductor including a second conductive dopant. In one example, the base region 110 may be composed of a single crystal or a polycrystalline semiconductor (e.g., single crystal or polycrystalline silicon) including a second conductive type dopant. In particular, the base region 110 may be comprised of a single crystal semiconductor (e.g., a single crystal semiconductor wafer, more specifically a semiconductor silicon wafer) comprising a second conductive dopant. The electrical characteristics are excellent based on the base region 110 or the semiconductor substrate 10 having high crystallinity and few defects.

The second conductivity type may be p-type or n-type. For example, if the base region 110 has an n-type, the p-type (n-type) semiconductor layer forming a junction with the base region 110 and forming a carrier by photoelectric conversion It is possible to increase the photoelectric conversion area by forming the first conductivity type region 32 of the first conductivity type. In this case, the first conductivity type region 32 having a large area can effectively collect holes having a relatively low moving speed, thereby contributing to the improvement of photoelectric conversion efficiency. However, the present invention is not limited thereto.

The semiconductor substrate 10 may include a front electric field area (or an electric field area) 130 positioned on the other surface (hereinafter referred to as "front surface") side of the semiconductor substrate 10. The front field region 130 may have a doping concentration higher than that of the base region 110 while having the same conductivity type as that of the base region 110. [

In this embodiment, the front electric field region 130 is formed in the semiconductor substrate 10 as a doped region formed by doping a dopant having a second conductivity type with a relatively high doping concentration. Accordingly, the front electric field area 130 includes a crystalline (single crystal or polycrystalline) semiconductor having a second conductivity type to constitute a part of the semiconductor substrate 10. For example, the front electric field area 130 can form a part of a single crystal semiconductor substrate having a second conductivity type (for example, a single crystal silicon wafer substrate). At this time, the doping concentration of the front electric field region 130 may be smaller than the doping concentration of the second conductive type region 34 having the same second conductivity type.

However, the present invention is not limited thereto. Therefore, it is also possible to form the front electric field area 130 by doping a second conductive type dopant to a semiconductor layer other than the semiconductor substrate 10 (for example, an amorphous semiconductor layer, a microcrystalline semiconductor layer, or a polycrystalline semiconductor layer) have. Alternatively, the front electric field region 130 has a role similar to that doped by the fixed electric charge of the layer (for example, the front passivation film 24 and / or the antireflection film 26) formed adjacent to the semiconductor substrate 10 As shown in FIG. For example, when the base region 110 is n-type, the front passivation film 24 may be formed of an oxide (for example, aluminum oxide) having a fixed negative charge to form an inversion layer ) Can be formed and used as an electric field region. In this case, the semiconductor substrate 10 does not have a separate doping region but consists only of the base region 110, thereby minimizing defects in the semiconductor substrate 10. [ The front electric field area 130 having various structures can be formed by various other methods.

In the present embodiment, the front surface of the semiconductor substrate 10 may be textured to have irregularities such as pyramids. The texturing structure formed on the semiconductor substrate 10 may have a certain shape (e.g., a pyramid shape) having an outer surface formed along a specific crystal plane of the semiconductor. If the surface roughness of the semiconductor substrate 10 is increased by forming concavities and convexities on the front surface of the semiconductor substrate 10 by such texturing, the reflectance of light incident through the front surface of the semiconductor substrate 10 can be reduced. Accordingly, the amount of light reaching the pn junction formed by the base region 110 and the first conductivity type region 32 can be increased, and the light loss can be minimized.

The rear surface of the semiconductor substrate 10 may be made of a relatively smooth and flat surface having a surface roughness lower than that of the front surface by mirror polishing or the like. When the first and second conductivity type regions 32 and 34 are formed together on the rear side of the semiconductor substrate 10 as in the present embodiment, the characteristics of the solar cell 100 This can vary greatly. As a result, unevenness due to texturing is not formed on the rear surface of the semiconductor substrate 10, so that passivation characteristics can be improved and the characteristics of the solar cell 100 can be improved. However, the present invention is not limited thereto, and it is also possible to form concavities and convexities by texturing on the rear surface of the semiconductor substrate 10 according to circumstances. Various other variations are possible.

A tunneling layer 20 may be formed on the rear surface of the semiconductor substrate 10. For example, the tunneling layer 20 may be formed in contact with the rear surface of the semiconductor substrate 10 to simplify the structure and improve the tunneling effect. However, the present invention is not limited thereto.

The tunneling layer 20 acts as a kind of barrier to electrons and holes to prevent the minority carriers from passing therethrough and to prevent the majority carriers from being accumulated in the portion adjacent to the tunneling layer 20, so that only the majority carriers can pass through the tunneling layer 20. At this time, a plurality of carriers having energy above a certain level can easily pass through the tunneling layer 20 by the tunneling effect. The tunneling layer 20 may also serve as a diffusion barrier to prevent the dopants of the conductive regions 32 and 34 from diffusing into the semiconductor substrate 10. [ The tunneling layer 20 may include various materials through which a plurality of carriers can be tunneled. For example, the tunneling layer 20 may include an oxide, a nitride, a semiconductor, a conductive polymer, and the like. For example, the tunneling layer 20 may comprise silicon oxide, silicon nitride, silicon oxynitride, intrinsic amorphous silicon, intrinsic polycrystalline silicon, and the like. In particular, the tunneling layer 20 may be comprised of a silicon oxide layer comprising silicon oxide. This is because the silicon oxide layer is a film which has excellent passivation characteristics and is susceptible to tunneling of the carrier.

At this time, the tunneling layer 20 may be formed entirely on the rear surface of the semiconductor substrate 10. Accordingly, it can be easily formed without additional patterning.

The thickness of the tunneling layer 20 may be smaller than the thickness of the rear passivation film 40 in order to sufficiently realize the tunneling effect. In one example, the thickness of the tunneling layer 20 may be 5 nm or less (more specifically, 2 nm or less, for example, 0.5 nm to 2 nm). When the thickness T of the tunneling layer 20 exceeds 5 nm, the tunneling does not smoothly occur and the solar cell 100 may not operate. When the thickness of the tunneling layer 20 is less than 0.5 nm, It may be difficult to form the electrode 20. In order to further improve the tunneling effect, the thickness of the tunneling layer 20 may be 2 nm or less (more specifically, 0.5 nm to 2 nm). At this time, the thickness of the tunneling layer 20 may be 0.5 nm to 1.2 nm so as to further improve the tunneling effect. However, the present invention is not limited thereto, and the thickness of the tunneling layer 20 may have various values.

On the tunneling layer 20, a semiconductor layer 30 including conductive regions 32 and 34 may be located. For example, the semiconductor layer 30 may be formed in contact with the tunneling layer 20 to simplify the structure and maximize the tunneling effect. However, the present invention is not limited thereto.

In this embodiment, the semiconductor layer 30 includes a first conductivity type region 32 having a first conductivity type dopant and exhibiting a first conductivity type, a second conductivity type region 32 having a second conductivity type dopant and exhibiting a second conductivity type, Type region 34. [0040] The first conductive type region 32 and the second conductive type region 34 may be coplanar on the tunneling layer 20. That is, no other layer is located between the first and second conductivity type regions 32 and 34 and the tunneling layer 20, or the first and second conductivity type regions 32 and 34 and the tunneling layer 20 20, the other layers may have the same lamination structure. And a barrier region 36 may be positioned between the first conductivity type region 32 and the second conductivity type region 34 on the same plane.

The first conductive type region 32 forms a pn junction (or a pn tunnel junction) between the base region 110 and the tunneling layer 20 to form an emitter region for generating carriers by photoelectric conversion.

At this time, the first conductive type region 32 may include a semiconductor (for example, silicon) including a first conductive type dopant opposite to the base region 110. The first conductive type region 32 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically, on the tunneling layer 20) and the first conductive type dopant is doped As shown in Fig. Accordingly, the first conductive type region 32 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so that the first conductive type region 32 can be easily formed on the semiconductor substrate 10. For example, the first conductivity type region 32 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (e.g., amorphous silicon, microcrystalline silicon, or polycrystalline silicon) that can be easily fabricated by various methods, And the first conductive type dopant. The first conductive dopant may be included in the semiconductor layer in the step of forming the semiconductor layer or may be included in the semiconductor layer by various doping methods such as a heat diffusion method and an ion implantation method after forming the semiconductor layer.

At this time, the first conductive type region 32 may include a first conductive type dopant that can exhibit a conductive type opposite to the base region 110. That is, when the first conductivity type dopant is a p-type, a Group 3 element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. When the first conductivity type dopant is n-type, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used. As an example, the first conductivity type dopant may be boron (B) having a p-type.

The second conductivity type region 34 forms a back surface field to prevent carriers from being lost by recombination on the surface of the semiconductor substrate 10 (more precisely, the back surface of the semiconductor substrate 10) Thereby constituting a rear electric field area.

At this time, the second conductive type region 34 may include a semiconductor (e.g., silicon) including the same second conductive type dopant as the base region 110. In this embodiment, the second conductivity type region 34 is formed separately from the semiconductor substrate 10 on the semiconductor substrate 10 (more specifically on the tunneling layer 20) and the second conductivity type dopant is doped As shown in Fig. Accordingly, the second conductive type region 34 may be formed of a semiconductor layer having a crystal structure different from that of the semiconductor substrate 10 so that the second conductive type region 34 can be easily formed on the semiconductor substrate 10. For example, the second conductivity type region 34 may be an amorphous semiconductor, a microcrystalline semiconductor, or a polycrystalline semiconductor (e.g., amorphous silicon, microcrystalline silicon, or polycrystalline silicon) that can be easily fabricated by various methods, And the second conductive type dopant. The second conductive dopant may be included in the semiconductor layer in the step of forming the semiconductor layer or may be included in the semiconductor layer by various doping methods such as a thermal diffusion method and an ion implantation method after forming the semiconductor layer.

At this time, the second conductive type region 34 may include a second conductive type dopant that can exhibit the same conductivity type as the base region 110. That is, when the second conductivity type dopant is n-type, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) can be used. When the second conductivity type dopant is p-type, a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. As an example, the second conductivity type dopant may be phosphorus (P) having n-type conductivity.

A barrier region 36 is positioned between the first conductive type region 32 and the second conductive type region 34 to separate the first conductive type region 32 and the second conductive type region 34 from each other. When the first conductive type region 32 and the second conductive type region 34 are in contact with each other, a shunt may be generated to deteriorate the performance of the solar cell 100. Accordingly, in this embodiment, unnecessary shunt can be prevented by positioning the barrier region 36 between the first conductive type region 32 and the second conductive type region 34.

The barrier region 36 may comprise a variety of materials that can substantially insulate them between the first conductive type region 32 and the second conductive type region 34. That is, an undoped (i.e., unshown) insulating material (e.g., oxide, nitride) or the like may be used for the barrier region 36. Alternatively, the barrier region 36 may comprise an intrinsic semiconductor. At this time, the first conductive type region 32, the second conductive type region 34, and the barrier region 36 are formed of the same semiconductor (for example, amorphous silicon, microcrystalline silicon, , The barrier region 36 may be an i-type (intrinsic) semiconductor material substantially free of dopants. For example, a semiconductor layer containing a semiconductor material may be formed, and then a first conductive type dopant may be doped in a part of the semiconductor layer to form a first conductive type region 32, and a second conductive type dopant A region where the first conductivity type region 32 and the second conductivity type region 34 are not formed may constitute the barrier region 36. In this case, This makes it possible to simplify the manufacturing method of the first conductivity type region 32, the second conductivity type region 34, and the barrier region 36.

However, the present invention is not limited thereto. Therefore, when the barrier region 36 is formed separately from the first conductivity type region 32 and the second conductivity type region 34, the thickness of the barrier region 36 is different from that of the first conductivity type region 32 and the second conductivity type region 34, Conductivity type region 34. [0060] For example, the barrier region 36 may include a first conductive type region 32 and a second conductive type region 34 to more effectively prevent shorting of the first conductive type region 32 and the second conductive type region 34, Or may have a thickness greater than that of the substrate. Alternatively, the thickness of the barrier region 36 may be made smaller than the thickness of the first conductivity type region 32 and the second conductivity type region 34 in order to reduce the raw material for forming the barrier region 36. Of course, various modifications are possible. In addition, the basic constituent material of the barrier region 36 may include a material different from the first conductive type region 32 and the second conductive type region 34.

In this embodiment, the barrier region 36 is entirely spaced apart from the first conductivity type region 32 and the second conductivity type region 34. However, the present invention is not limited thereto. Therefore, the barrier region 36 may be formed to separate only a part of the boundary portions of the first conductive type region 32 and the second conductive type region 34. According to this, other portions of the boundaries of the first conductivity type region 32 and the second conductivity type region 34 may be in contact with each other.

Here, the area of the first conductivity type region 32 having a conductivity type different from that of the base region 110 can be wider than the area of the second conductivity type region 34 having the same conductivity type as that of the base region 110 have. Accordingly, the pn junction formed through the tunneling layer 20 between the base region 110 and the first conductive type region 32 can be made wider. At this time, when the base region 110 and the second conductivity type region 34 have the n-type conductivity and the first conductivity type region 32 has the p-type conductivity, the first conductivity type region It is possible to effectively collect holes having a relatively slow moving speed by the electron beam 32. [ The planar structure of the first conductive type region 32, the second conductive type region 34, and the barrier region 36 will be described later in detail with reference to FIG.

The rear passivation film 40 may be formed on the first and second conductivity type regions 32 and 34 and the barrier region 36 on the rear surface of the semiconductor substrate 10. [ For example, the rear passivation film 40 may be formed in contact with the first and second conductivity type regions 32 and 34 and the barrier region 36 to simplify the structure. However, the present invention is not limited thereto.

The rear passivation film 40 has contact holes 46 for electrical connection between the conductive regions 32 and 34 and the electrodes 42 and 42. The contact hole 46 includes a first contact hole 461 for connecting the first conductivity type region 32 and the first electrode 42 and a second contact hole 461 for connecting the second conductivity type region 34 and the second electrode 44, And a second contact hole 462 for connection of the second contact hole 462. As a result, the rear passivation film 40 is formed in the same manner as that of the first conductive type region 32 and the second conductive type region 34 in the case of the electrode to which the first conductive type region 32 and the second conductive type region 34 should not be connected 44 in the case of the second conductivity type region 34 and the first electrode 42 in the case of the second conductivity type region 34). In addition, the back passivation film 40 may have the effect of passivating the first and second conductivity type regions 32, 34 and / or the barrier region 36.

The rear passivation film 40 may be positioned on the semiconductor layer 30 at a portion not located at the electrodes 42 and 44. [ The back passivation film 40 may have a greater thickness than the tunneling layer 20. As a result, the insulating characteristics and the passivation characteristics can be improved. Various other variations are possible.

For example, in the present embodiment, the front passivation film 24 and / or the antireflection film 26 and the rear passivation film 40 may not include a dopant or the like so as to have excellent insulating properties, passivation properties, and the like.

The back passivation film 40 in this embodiment includes a first layer 40a positioned (e.g., in contact with) the conductive regions 32 and 34 and the barrier region 36 (or the semiconductor layer 40) And may include a second layer 40b located on the first layer 40a and containing a different material than the first layer 40a. The contact hole 46 is formed in the first layer 40a and the first contact hole 46a formed in the second layer 40b and formed in the position corresponding to the first contact hole 46a, And a second contact hole portion 46b communicating with the contact hole portion 46a. In this embodiment, the first contact hole portion 46a and the second contact hole portion 46b are formed by different processes in the first layer 40a and the second layer 40b having different materials, , Shape, and the like. This will be described in more detail later.

At this time, the second contact hole portion 46b may be formed by laser etching, and the first contact hole portion 46a may be formed by wet etching. The first contact hole 46a formed in the first layer 40a may include a portion larger than the second contact hole 46b formed in the second layer 40b. This is because the undercut occurred due to the isotropic etching during the wet etching, which will be described later in more detail. The size of the first contact hole portion 46a may be larger at a portion adjacent to the second layer 40b than a portion adjacent to the conductive type region 30 by undercut. More specifically, the size of the first contact hole portion 46a can be gradually increased toward the portion adjacent to the second layer 40b than the portion adjacent to the conductive type region 30, and the first contact hole portion 46a, And the side surface of the first layer 40a may have a concave curved surface. Accordingly, a step may be formed between the side surface of the first contact hole portion 46a and the side surface of the second contact hole portion 46b. That is, the side surface of the second layer 40b protrudes from the side surface of the first layer 40a toward the inside of the contact hole 46, and the side surface of the second layer 40b Concave or recessed portion. By this step difference, a void space V may be located between the protective film 41 and the electrodes 42 and 44 positioned (e.g., in contact with) the side surface of the second layer 40b, Will be described in detail.

In one example, the inner surface of the second contact hole portion 46b may have a plane that is inclined at right angles to the upper or lower surface of the conductive regions 32, 34 or at an angle similar thereto. However, the present invention is not limited thereto.

At this time, the conductive type regions 32 and 34 and the conductive type regions 32 and 34 on the barrier region 36 and the conductive type region 32 and 34 and the barrier layer 36 are positioned (for example, in contact) between the second layer 40b The first layer 40a prevents damage to the conductive regions 32 and 34 that may occur when the second contact hole 46b is formed in the second layer 40b. Unlike the present embodiment, when the first layer 40a does not exist, when the second contact hole 46b is formed by removing a part of the second layer 40b through the second layer 40b by etching or the like A part of the conductive type regions 32 and 34 located under the second layer 40b may be removed or the characteristics of the conductive type regions 32 and 34 may be deteriorated. If the conductive type regions 32 and 34 are damaged as described above, the characteristics and efficiency of the solar cell 100 deteriorate. Accordingly, in this embodiment, the first layer 40a, which is not removed when the second layer 40b is removed, is placed on the conductive regions 32 and 34 to remove the second layer 40b. Contact with the first layer (40a) and not with the conductive regions (32, 34). As a result, damage to the conductive type regions 32 and 34 can be prevented at the source.

The second layer 40b should be removed and the first layer 40a should remain without being removed in the formation of the contact hole 46. [ For example, when laser etching is used in forming the contact hole 46, the band gap between the first layer 40a and the second layer 40b may be different from each other. That is, the band gap of the first layer 40a is larger than the band gap of the conductive type regions 32, 34 and the second layer 40b, and the bandgap of the laser used for laser etching is larger than that of the second layer 40b And may have a value between the band gap and the band gap of the first layer 40a. Since the band gap of the laser is related to the wavelength of the laser, a value converted from the laser wavelength can be used. Then, the second layer 40b having a bandgap smaller than the bandgap of the laser is melted and removed by the laser, and the first layer 40a having a bandgap larger than the bandgap of the laser transmits the laser, do. Accordingly, the contact hole 46 is formed in the second layer 40b when the laser is etched, and the first layer 40a may remain as it is or only the laser etching trace may be formed.

In the case where the conductive type regions 32 and 34 include the polycrystalline semiconductor layer, the bandgap of the conductive type regions 32 and 34 has a band gap of about 1.12 eV and is the same as the second layer 40b Or a band gap smaller than this. Therefore, when the first layer 40a is not provided, a part of the conductive type regions 32 and 34 may be etched during the etching of the second layer 40b, and the conductive type regions 32 and 34 may be damaged. On the other hand, in this embodiment, the first layer 40a having a larger band gap than the conductive type regions 32 and 34 is formed so that the conductive type regions 32 and 34 are not etched when the second layer 40b is etched .

For example, the band gap of the first layer 40a may have a band gap of 3 eV or more, and the second layer 40b may have a band gap of 3 eV or less. More specifically, the band gap of the first layer 40a may be at least 5 eV (e.g., 5 eV to 10 eV), and the band gap of the second layer 40b may be at least 0.5 eV and less than 3 eV. This is based on the wavelength of the laser used in the laser etching, and the above-described values may vary if the wavelength of the laser is changed. The lasers used in laser etching will be described later in more detail in the manufacturing method. However, the present invention is not limited thereto.

Various methods can be used as a method of adjusting the band gap. In this embodiment, materials of the first layer 40a and the second layer 40b may be made different from each other considering the bandgap different depending on the material . For example, the first layer 40a may include an oxide having a relatively high bandgap (e.g., silicon oxide, aluminum oxide, titanium oxide, etc.) or amorphous silicon. Since the oxide has a high band gap (generally 8 eV to 9 eV) of 5 eV or more, it may remain unetched even if there is a laser etching or the like. Amorphous silicon also has a band gap of 3 eV or more and can remain without being etched by laser etching. The first layer 40a may have a single film or a multi-layer structure in which two or more films are combined.

The second layer 40b may use nitride, carbide (e.g., silicon nitride, silicon carbide, or the like) having a relatively small bandgap. Such a silicon nitride or silicon carbide has a bandgap of generally less than 3 eV (for example, 0.5 eV to 3 eV) although it varies depending on the composition. The second layer 40b may have a single film or a multi-layer structure in which two or more films are combined.

The first layer 40a may have a thickness that is not etched or damaged when forming the second contact hole portion 46b. Accordingly, the first layer 40a may have a thickness greater than that of the tunneling layer 20 and the protective film 41. The first layer 40a may have a thickness that does not become etched or damaged when forming the second contact hole portion 46b. If the first layer 40a has an excessively large thickness, the process time may become long. In view of this, the first layer 40a may have a thickness less than the conductivity type regions 32 and 34, and may have a thickness equal to or less than the second layer 40b. Here, the first layer 40a may have a smaller thickness than the second layer 40b.

In one example, the thickness of the first layer 40a may be between 5 nm and 100 nm. When the thickness of the first layer 40a is less than 5 nm, it may be difficult to effectively protect the conductive type regions 32 and 34 when forming the second contact hole portion 46b. If the thickness of the first layer 40a exceeds 100 nm, the time of the manufacturing process may be increased and the productivity may be lowered. The thickness of the first layer 40a may be 10 nm to 50 nm (e.g., 10 nm to 30 nm) so as to reduce the processing time while more effectively protecting the conductive regions 32 and 34. However, the present invention is not limited thereto, and the first layer 40a may have various thicknesses.

The first contact hole portion 46a formed in the first layer 40a may be formed in a process different from the process of forming the second contact hole portion 46b after forming the second contact hole portion 46b. As described above, in order to prevent the conductive type regions 32 and 34 from being damaged in the process of forming the second contact hole portion 46b or the like, the first layer 40a has a thickness of a predetermined value or more. Therefore, if the conductive layers 32 and 34 and the electrodes 42 and 44 are electrically connected to each other with the first layer 40a left under the second contact hole 46b, the first layer 40a The electrical connection characteristics between the conductive type regions 32 and 34 and the electrodes 42 and 44 may be degraded. In consideration of this, in the present embodiment, the first contact hole 46a is also formed in the first layer 40a at a portion where the second contact hole 46b is located. The process of forming the first contact hole portion 46a may be performed in a different process from the process of forming the second contact hole portion 46b so as to minimize the damage and the deterioration of characteristics occurring in the conductive type regions 32 and 34 . This will be described in more detail later.

The contact hole 46 including the first contact hole portion 46a and the second contact hole portion 46b is formed through the rear passivation film 40. [

The protective film 41 is located between the conductive type regions 32 and 34 and the electrodes 42 and 44 in the contact hole 46 of the rear passivation film 40. Since the contact hole 46 is formed in the rear passivation film 40, if the passivation film 41 is not located, the passivation film 40 is not present at the portion where the contact hole 46 is formed, . In order to prevent this, in the present embodiment, the protective film 41 is placed on the conductive type regions 32 and 34 in the contact hole 46. This makes it possible to effectively prevent the degradation of the passivation characteristic that may occur due to the presence of the contact hole 46. [

And the protective film 41 can prevent the conductive type regions 32 and 34 from being damaged in various processes performed after the contact holes 46 are formed. For example, when the electrodes 42 and 44 are formed in the contact hole 46 by a method such as sputtering, the surface exposed by the contact hole 46 is exposed to the plasma. Unlike the present embodiment, if the protective layer 41 is not provided, the conductive regions 32 and 34 may be directly exposed to the plasma, thereby causing surface damage. On the other hand, when the protective film 41 is provided as in the present embodiment, the protective film 41 can prevent the conductive type regions 32 and 34 from being exposed to plasma or plasma. In addition, the passivation film 41 serves to passivate the surfaces of the conductive type regions 32 and 34, thereby improving passivation characteristics.

The protective layer 41 may be formed after forming the contact hole 46 including the first and second contact hole portions 46a and 46a and may be patterned together when the electrodes 42 and 44 are patterned. The passivation layer 41 may be formed entirely on the portion where the electrodes 42 and 44 are formed between the electrodes 42 and 44 and the rear passivation layer 40.

More specifically, the protective film 41 is formed on the bottom surface of the contact hole 46 (that is, on the surface of the conductive type regions 32 and 34 exposed by the contact hole 46) And a portion that is located (for example, in contact with) the side surface of the contact hole 46 (that is, the side surface of the first and second layers 40a and 40b) and the outer surface of the rear passivation film 40, (For example, contact) between the surface of the electrodes 42 and 44 facing the rear passivation film 40 and the rear passivation film 40 above the lower passivation film 40 (lower surface in the figure). The portions of the protective film 41 described above may be composed of the same layer continuously formed to be integrated with each other. At this time, the side surfaces of the electrodes 42 and 44 and the side surface of the protective film 41 may be formed on the same plane. This is because the protective film 41 can be etched together when the electrodes 42 and 44 are patterned.

At this time, since the conductive regions 32 and 34 and the electrodes 42 and 44 are electrically connected with the protective film 41 interposed therebetween, the electrical connection between the conductive type regions 32 and 34 and the electrodes 42 and 44 The protective film 41 may be formed thin so as to improve the characteristics. That is, the protective film 41 may have a smaller thickness than the rear passivation film 40 (more specifically, each of the first layer 40a and the second layer 40b).

The protective film 41 has a thickness smaller than that of the rear passivation film 40, more specifically, each of the first layer 40a and the second layer 40b. The passivation film 40 must have a relatively thick thickness for sufficient passivation characteristics while the passivation film 41 is thin enough to protect the conductive regions 32 and 34 without degrading the electrical connection properties It is because it has thickness.

For example, the protective film 41 may have a thickness smaller than that of the tunneling layer 20. According to this, even when the protective film 41 exists, the electrical connection characteristics between the conductive type regions 32 and 34 and the electrodes 42 and 44 can be excellent. However, the present invention is not limited thereto, and the protective layer 41 may have a thickness equal to or larger than that of the tunneling layer 20.

For example, the thickness of the protective film 41 may be 0.5 nm to 2 nm (for example, 0.5 nm to 1.2 nm). If the thickness of the protective film 41 is less than 0.5 nm, it may be difficult to form the protective film 41 as a whole with a uniform thickness, and the effect of the protective film 41 may not be sufficient. If the thickness of the protective film 41 exceeds 2 nm, the electrical connection characteristics between the conductive type regions 32 and 34 and the electrodes 42 and 44 may be somewhat lowered. The thickness of the protective film 41 may be 1.2 nm or less to further improve the electrical connection characteristics. However, the present invention is not limited thereto and various modifications are possible.

The passivation layer 41 can be easily formed by a simple process, and can be made of a material capable of improving the passivation characteristics and protecting the conductive regions 32 and 34. At this time, the passivation layer 41 may be formed of a material different from that of the back passivation layer 40. In this embodiment, the protective layer 41 may be formed of a material different from that of the second layer 40a.

In one example, the protective film 41 may be composed of an oxide. In particular, the protective film 41 may be composed of a silicon oxide formed by bonding oxygen with a semiconductor material (for example, silicon) included in the conductive type regions 32 and 34. When the protective film 41 contains an oxide (particularly, silicon oxide), it has excellent passivation characteristics and can be easily formed by a chemical oxidation process, a thermal oxidation process, or the like. This will be described later in more detail in the manufacturing method.

Electrodes 42 and 44 located on the rear surface of the semiconductor substrate 10 include a first electrode 42 electrically and physically connected to the first conductivity type region 32 and a second electrode 42 electrically connected to the second conductivity type region 34 And a second electrode 44 electrically and physically connected.

The first electrode 42 is formed by filling at least a part of the contact hole 46 of the rear passivation film 40 and is connected to the first conductive type region 32 through the protective film 41, The second electrode 44 is formed by filling at least a portion of the contact hole 46 of the rear passivation film 40 and is connected to the second conductive type region 34. As described above, in the undercut of the first layer 40a between the first layer 40a of the rear passivation film 40 and the side surface of the second layer 40b (i.e., the inner surface of the contact hole 46) And a protective film 41 formed by a chemical oxidation process or the like is formed in close contact with the side surfaces of the first layer 40a and the second layer 40b. That is, the protective layer 41 is formed with the steps, bends, and the like located on the sides of the first layer 40a and the second layer 40b. However, the electrodes 42 and 44 may not be completely formed in the stepped portion where the undercut is formed (i.e., the concave portion on the side surface of the first layer 40a). Therefore, the void space V may remain between the first layer 40a and the protective film 41 adhered to the first layer 40a and the electrodes 42 and 44. This void space V does not cause a serious problem in the characteristics, and it can be confirmed that the first layer 40a is formed by the wet etching due to the existence of the vacant space V and the undercut is formed. However, the present invention is not limited thereto. The voids V are not formed between the protective film 41 and the electrodes 42 and 44 at the side of the contact hole 46 and the electrodes 42 and 44 are not formed at the side of the contact hole 46 (Or contact) with the first and second electrodes 41 and 41. This will be described in detail later with reference to FIG.

At this time, for example, the protective film 41 may be formed by chemical oxidation. Since the first layer 40a and the second layer 40b of the conductive type regions 32 and 34 and the rear passivation film 40 each contain silicon, the protective film 41 is formed of a protective film 41 may be formed entirely over the conductive regions 32, 34, on the sides of the first layer 40a and the second layer 40b, and over the second layer 40b by chemical oxidation. At this time, since the silicon ratio of the first layer 40a and the second layer 40b is smaller than the silicon ratio of the conductive type regions 32 and 34, the protective film 41 formed on the conductive type regions 32 and 34 The thickness may be greater than the thickness of the portion formed on the side surface of the first layer 40a, the side surface of the second layer 40b, and the outer surface of the second layer 40b. However, the present invention is not limited thereto, and the thickness of the protective film 41 may be uniform. If the first layer 40a and / or the second layer 40b of the rear passivation film 40 does not contain silicon, a protective film 41 is formed on the protective layer 41 by chemical oxidation . The protective layer 41 may be formed by various methods other than chemical oxidation so that the first layer 40a and / or the second layer 40b may be formed entirely with a uniform thickness thereon without containing silicon . Various other variations are possible.

The first and second electrodes 42 and 44 may include various metal materials. The first and second electrodes 42 and 44 are connected to the first conductive type region 32 and the second conductive type region 34 without being electrically connected to each other, And can have a variety of planar shapes. That is, the present invention is not limited to the planar shapes of the first and second electrodes 42 and 44.

1 and 2, the first conductive type region 32 and the second conductive type region 34, the barrier region 36, and the planar shape of the first and second electrodes 42 and 44 Will be described in detail.

1 and 2, in the present embodiment, the first conductive type region 32 and the second conductive type region 34 are formed to be long in a stripe shape, and alternate with each other in the direction crossing the longitudinal direction Respectively. Barrier regions 36 may be located between the first conductivity type region 32 and the second conductivity type region 34 to isolate them. Although not shown, a plurality of first conductive regions 32 spaced apart from each other may be connected to each other at one edge, and a plurality of second conductive regions 34 separated from each other may be connected to each other at the other edge. However, the present invention is not limited thereto.

At this time, the area of the first conductivity type region 32 may be larger than the area of the second conductivity type region 34. In one example, the areas of the first conductivity type region 32 and the second conductivity type region 34 can be adjusted by varying their widths. That is, the width W1 of the first conductivity type region 32 may be greater than the width W2 of the second conductivity type region 34. [

The first electrode 42 may be formed in a stripe shape corresponding to the first conductivity type region 32 and the second electrode 44 may be formed in a stripe shape corresponding to the second conductivity type region 34 . The contact hole 46 may be formed to connect only a part of the first and second electrodes 42 and 44 to the first conductive type region 32 and the second conductive type region 34, respectively. For example, the contact hole 46 may be formed of a plurality of contact holes. Alternatively, a contact hole (reference numeral 46 in FIG. 1, hereinafter the same) may be formed in the entire length of the first and second electrodes 42 and 44 corresponding to the first and second electrodes 42 and 44 . The contact area between the first and second electrodes 42 and 44 and the first conductivity type region 32 and the second conductivity type region 34 can be maximized to improve the carrier collection efficiency. Various other variations are possible. Although not shown in the figure, the first electrodes 42 may be connected to each other at one edge, and the second electrodes 44 may be connected to each other at the other edge. However, the present invention is not limited thereto.

1, a front passivation film 24 and / or an antireflection film (not shown) are formed on the front surface of the semiconductor substrate 10 (more precisely, on the front electric field area 130 formed on the front surface of the semiconductor substrate 10) 26) can be located. Only the front passivation film 24 may be formed on the semiconductor substrate 10 or only the antireflection film 26 may be formed on the semiconductor substrate 10 or the front passivation film 26 may be formed on the semiconductor substrate 10. [ The antireflection film 24 and the antireflection film 26 may be sequentially disposed. The front passivation film 24 and the antireflection film 26 are sequentially formed on the semiconductor substrate 10 so that the semiconductor substrate 10 is contacted with the front passivation film 24. However, the present invention is not limited thereto, and the semiconductor substrate 10 may be formed in contact with the anti-reflection film 26, and various other modifications are possible.

The front passivation film 24 and the antireflection film 26 may be formed entirely on the entire surface of the semiconductor substrate 10. [ Here, the term " formed as a whole " includes not only completely formed physically but also includes cases where there are inevitably some exclusion parts.

The front passivation film 24 is formed in contact with the front surface of the semiconductor substrate 10 to passivate defects existing in the front surface or bulk of the semiconductor substrate 10. [ Thus, the recombination site of the minority carriers can be removed to increase the open-circuit voltage of the solar cell 100. The antireflection film 26 reduces the reflectance of light incident on the front surface of the semiconductor substrate 10. The amount of light reaching the pn junction formed at the interface between the base region 110 and the first conductive type region 32 can be increased. Accordingly, the short circuit current Isc of the solar cell 100 can be increased. As described above, the open-circuit voltage and the short-circuit current of the solar cell 100 can be increased by the front passivation film 24 and the anti-reflection film 26, thereby improving the efficiency of the solar cell 100.

The front passivation film 24 and / or the antireflection film 26 may be formed of various materials. For example, the front passivation film 24 and / or the antireflection film 26 may include a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a silicon carbide film, MgF ₂ , ZnS, TiO ₂ , ₂ , or a multilayer film structure in which two or more films are combined. For example, the front passivation film 24 may be formed on the semiconductor substrate 10 and may be a silicon oxide film, and the anti-reflection film 26 may have a structure in which a silicon nitride film and a silicon carbide film are sequentially stacked.

When light is incident on the solar cell 100 according to the present embodiment, electrons and holes are generated by the photoelectric conversion at the pn junction formed between the base region 110 and the first conductivity type region 32, And electrons tunnel to the tunneling layer 20 to move to the first and second electrodes 42 and 44 after moving to the first conductivity type region 32 and the second conductivity type region 34, respectively. Thereby generating electrical energy.

In the solar cell 100 having the rear electrode structure in which the electrodes 42 and 44 are formed on the rear surface of the semiconductor substrate 10 and electrodes are not formed on the front surface of the semiconductor substrate 10 as in the present embodiment, The shading loss can be minimized at the front of the display device. Thus, the efficiency of the solar cell 100 can be improved. However, the present invention is not limited thereto.

Since the first and second conductive regions 32 and 34 are formed on the semiconductor substrate 10 with the tunneling layer 20 interposed therebetween, the first and second conductive type regions 32 and 34 are formed of different layers from the semiconductor substrate 10. As a result, the loss due to the recombination can be minimized as compared with the case where the doped region formed by doping the semiconductor substrate 10 with the dopant is used as the conductive type region.

A protective film 41 is formed in the contact hole 46 of the rear passivation film 40 and the electrodes 42 and 44 are connected to the conductive type regions 32 and 34 with the protective film 41 interposed therebetween The passivation property in the contact hole 46 can be improved and the conductive type regions 32 and 34 can be protected. The passivation layer 41 may be formed as a separate layer in a process different from the rear passivation layer 40 so that the passivation layer 41 may be formed to have a thickness smaller than that of the rear passivation layer 40. As a result, the electrical connection characteristics between the conductive type regions 32 and 34 and the electrodes 42 and 44 can be maintained to be excellent. At this time, the rear passivation film 40 includes a first layer 40a and a second layer 40b which are different materials, and includes a first contact hole portion 46a formed in the first layer 40a and a second contact hole portion 46b formed in the second layer 40b It is possible to effectively prevent the conductive type regions 32 and 34 from being damaged when the contact holes 46 are formed. Thus, the efficiency of the solar cell 100 can be improved.

A manufacturing method of the solar cell 100 having the above-described structure will be described in detail with reference to FIGS. 3A to 3N. 3A to 3N are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.

First, as shown in FIG. 3A, a semiconductor substrate 10 composed of a base region 110 having a second conductive dopant is prepared. In this embodiment, the semiconductor substrate 10 may be formed of a silicon substrate (for example, a silicon wafer) having an n-type dopant. As the n-type dopant, a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb) may be used. However, the present invention is not limited thereto, and the base region 110 may have a p-type dopant.

Next, as shown in FIG. 3B, a tunneling layer 20 is formed on the rear surface of the semiconductor substrate 10. The tunneling layer 20 may be formed entirely on the rear surface of the semiconductor substrate 10.

Here, the tunneling layer 20 can be formed, for example, by a thermal growth method, a deposition method (for example, chemical vapor deposition (PECVD), atomic layer deposition (ALD), or the like). However, the present invention is not limited thereto, and the first tunneling layer 20 may be formed by various methods.

3C and 3F, a first conductive type region 32, a second conductive type region 34 and a front electric field region 130 are formed on the tunneling layer 20 and the semiconductor substrate 10 A texturing structure may be formed on the entire surface of the substrate. This will be described in more detail as follows.

As shown in FIG. 3C, a semiconductor layer 30 is formed on the tunneling layer 20. The semiconductor layer 30 may be composed of a microcrystalline, amorphous, or polycrystalline semiconductor. The semiconductor layer 30 can be formed, for example, by a thermal growth method, a deposition method (for example, chemical vapor deposition (PECVD)), or the like. However, the present invention is not limited thereto, and the semiconductor layer 30 may be formed by various methods.

Then, as shown in Fig. 3D, a first conductivity type region 32 is formed in the semiconductor layer 30. Then, as shown in Fig. For example, the first conductive type region 32 may be formed by doping a first conductive type dopant in a region corresponding to the first conductive type region 32 by various methods such as an ion implantation method, a thermal diffusion method, a laser doping method, can do.

Then, as shown in FIG. 3E, the entire surface of the semiconductor substrate 10 may be textured so as to have irregularities. Wet or dry texturing may be used for texturing the surface of the semiconductor substrate 10. [ The wet texturing can be performed by immersing the semiconductor substrate 10 in the texturing solution, and has a short process time. In dry texturing, the surface of the semiconductor substrate 10 is cut by using a diamond grill or a laser, so that irregularities can be uniformly formed, but the processing time is long and damage to the semiconductor substrate 10 may occur. Alternatively, the semiconductor substrate 10 may be textured by reactive ion etching (RIE) or the like. As described above, the semiconductor substrate 10 can be textured in various ways in the present invention.

In this embodiment, the front surface of the semiconductor substrate 10 is textured after the semiconductor layer 30 is formed. However, the present invention is not limited thereto. Therefore, the surface of the semiconductor substrate 10 can be textured before or after the semiconductor layer 30 is formed.

3F, a second conductive type region 34 and a barrier region 36 are formed in the semiconductor layer 30 and a front electric field region 130 is formed on the entire surface of the semiconductor substrate 10 do.

For example, the second conductivity type region 34 may be formed by doping a region of the second conductivity type region 34 with a second conductivity type dopant by various methods such as ion implantation, thermal diffusion, laser doping, can do. Then, a region located between the first conductivity type region 32 and the second conductivity type region 34 constitutes the barrier region 36. A front electric field region 130 may be formed on the entire surface of the semiconductor substrate 10 by doping a second conductive dopant by various methods such as ion implantation, thermal diffusion, and laser doping. For example, the second conductive type region 34 and the front electric field region 130 may be simultaneously formed by a thermal diffusion method or the like, thereby simplifying the process.

However, the present invention is not limited thereto, and various modifications are possible in the method or order of forming the conductive type regions 32 and 34, the barrier region 36, and the front electric field region 130. It is also possible not to form the barrier region 36.

3G, a passivation film 24 and an antireflection film 26 are sequentially formed on the entire surface of the semiconductor substrate 10. Then, as shown in Fig. That is, the passivation film 24 and the antireflection film 26 are formed on the entire surface of the semiconductor substrate 10. The passivation film 24 and the antireflection film 26 may be formed by various methods such as a vacuum deposition method, a chemical vapor deposition method, a spin coating method, a screen printing method or a spray coating method.

3H, the first layer 40a may be formed entirely on the rear surface of the semiconductor substrate 10, and the second layer 40b may be formed as a whole on the first layer 40a as shown in FIG. 3I. . The backside passivation film 40 is formed on the rear surface of the semiconductor substrate 10 to cover the first and second conductivity type regions 32 and 34 and includes a first layer 40a and a second layer 40b. ).

The rear passivation film 40 including the first layer 40a and the second layer 40b may be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing, or spray coating. For example, the first layer 40a and the second layer 40b may be formed by plasma enhanced chemical vapor deposition (PECVD) and may be formed in a continuous process in the same plasma chemical vapor deposition equipment .

In the drawings and the description, it is exemplified that the first layer 40a and the second layer 40b of the rear passivation film 40 are formed after the front passivation film 24 and the antireflection film 26 are formed. However, the present invention is not limited thereto, and the order of forming the first layer 40a and the second layer 40b of the first passivation film 24, the antireflection film 26, and the rear passivation film 40 may be varied It can be deformed.

Next, as shown in FIG. 3J, the second contact hole portion 46b is formed in the second layer 40b while leaving the first layer 40a. Various methods can be applied as a method of forming the second contact hole portion 46b.

For example, the second contact hole portion 46b can be formed by laser etching using the laser 200 in this embodiment. By using the laser etching, the width of the second contact hole portion 46b can be reduced and the second contact hole portion 46b of various patterns can be easily formed. In addition, only the second layer 40b can be selectively removed while leaving the first layer 40a according to the type and wavelength of the laser.

Laser etching can remove the portion of the second layer 40b while leaving the first layer 40a using the laser 200 that can melt the second layer 40b and can not melt the first layer 40a Thereby forming the second contact hole portion 46b. At this time, the laser 200 may have a band gap smaller than the band gap of the first layer 40a and a band gap larger than the band gap of the second layer 40b due to a specific wavelength. That is, since the wavelength of the laser 200 is directly related to the band gap, the value obtained by converting the wavelength of the laser into the band gap has a band gap smaller than the band gap than the first layer 40a and the band gap of the second layer 40b It is necessary to have a larger band gap. For example, the band gap of the laser 200 can be calculated by dividing the value of 1.24 eV 占 퐉 by the wavelength (um) of the laser 200. [ However, since the types and characteristics of the laser 200 may vary, the present invention is not limited thereto.

Thus, in this embodiment, the second contact hole portion 46b can be formed only in the second layer 40b by adjusting the band gap of the first layer 40a and the second layer 40b. Accordingly, a process of remaining the first layer 40a and selectively etching only the second layer 40b can be easily performed.

In one example, in laser etching, the laser 200 may have a wavelength of 1064 nm or less. It is difficult to generate the laser 200 at a level exceeding 1064 nm. For example, the laser 200 can be easily created and can have a wavelength of 300 nm to 600 nm to easily etch the second layer 40b. In one example, the laser 200 may be an ultraviolet laser. The laser 200 may have a laser pulse width in the range of picoseconds (ps) to nanoseconds (ns) to allow laser etching to occur well. In particular, the laser 200 has a laser pulse width in the order of picoseconds (ps) (i.e., 1 ps to 999 ps), so that laser etching can be performed well. The laser 200 may have a laser shot mode of a single shot or a burst shot. The burst shot is a process of irradiating one laser beam into a plurality of shots. By using the burst shot, damage to the first layer 40a and the conductive type regions 32 and 34 can be minimized. However, the present invention is not limited thereto and various lasers can be used.

At this time, the first layer 40a has a thickness of 5 nm to 100 nm and has a band gap larger than that of the laser 200, so that the laser is only passed. Therefore, the first layer 40a is not damaged by the laser. The intensity of the laser 200 that has reached the conductive regions 32 and 34 after passing through the first layer 40a is extremely small so that the laser 200 or heat by the laser is applied to the conductive regions 32 and 34 The conductive type regions 32 and 34 can not be melted or damaged.

Next, as shown in FIG. 3K, the first contact hole portion 46a is formed by wet-etching the first layer 40a using the second layer 40b as a mask. That is, the etching solution contacts the first layer 40a through the second contact hole portion 46b formed in the second layer 40b, so that the first layer 40a is isotropically etched. As the etching solution, various materials may be used that do not etch the second layer 40b while etching the first layer 40a or etch the second layer 40b at a very low speed. For example, diluted HF or buffered oxide etch (BOE) diluted with an etching solution can be used. For example, the diluted hydrofluoric acid may comprise from 0.5 wt% to 2 wt% hydrofluoric acid. In this etching solution, the first layer 40a made of oxide or the like can be easily etched, but the second layer 40b made of nitride, carbide or the like is etched or etched at a very small rate. Thus, only the first layer 40a can be selectively etched.

Since the first contact hole portion 46a is formed by isotropic etching as described above, the first contact hole portion 46a is etched at the same speed in all directions. Accordingly, the inner surface of the first contact hole portion 46a or the side surface of the first layer 40a may be curved.

And the first contact hole portion 46a is etched to have a relatively wide width or size at a portion adjacent to the second layer 40b and the conductive type regions 32 and 34 spaced apart from the second layer 40b Is etched to have a relatively narrow width or size. The width of the first contact hole portion 46a adjacent to the second layer 40b on one side is larger than the width of the first contact hole portion 46a adjacent to the conductive type regions 32 and 34, The width of the hole 46a or the second contact hole 46b may be about 50% to 100% of the thickness of the first layer 40a. That is, the thickness of the first layer 40a on the side surfaces of the first layer 40a and the second layer 40b (or the inner surfaces of the first contact hole portion 46a and the second contact hole portion 46b) And may have a level difference of about 50% to 100%.

Then, as shown in FIG. 3L, the upper surface of the passivation film 40 is exposed on the conductive regions 32 and 34 exposed by the contact holes 46, on the side surface of the rear passivation film 40, A protective film 41 is formed entirely on the surface (lower surface of the drawing). The protective film 41 may be formed by various processes.

In the present embodiment, the conductive passivation film 40 is formed on the conductive regions 32 and 34 exposed by the contact holes 46 by the chemical oxidation process, on the side surfaces of the rear passivation film 40, A silicon oxide layer entirely formed on the silicon oxide layer 41 may be used as the protective film 41.

For example, a silicon oxide layer may be formed by a chemical etching process by immersing the bottom surface of the solar cell in an etching solution of a nitric acid base. As another example, a silicon oxide layer may be formed by a chemical oxidation process with hydrogen peroxide used in the process of cleaning the lower surface of the solar cell. For example, a cleaning solution containing hydrogen peroxide, hydrochloric acid, and ultrapure water may be used to form a silicon oxide layer while being cleaned. Then, the protective film 41 composed of a silicon oxide layer can be formed without additionally adding a manufacturing process.

The silicon oxide layer formed by the chemical oxidation is formed on the conductive type regions 32 and 34 exposed by the contact hole 46 to a thickness of about 0.5 nm to 2 nm and on the side surface of the rear passivation film 40 Can be formed uniformly on the entire outer surface or the wide surface of the rear passivation film 40 as a whole. As a result, a thin and uniform protective film 41 can be formed.

However, the present invention is not limited thereto, and it may be formed by a silicon oxide layer formed in a thermal oxidation process or the like, and various layers or films may be used as the protective film 41.

Next, as shown in Figs. 3M and 3N, first and second electrodes 42 and 44 are formed so as to fill in the contact hole 46. Then, as shown in Figs.

More specifically, as shown in FIG. 3M, the electrode layer 400 is formed on the protective film 41 as a whole by sputtering, plating or the like. The electrode layer 400 is stably and uniformly formed on the rear passivation film 40. A portion of the electrode layer 400 may not be formed due to the step difference in the vicinity of the side surfaces of the first layer 40a and the second layer 40b. Particularly, the first layer 40a is not retreated or recessed more than the second layer 40b or the first contact hole portion 46a can not fill a portion having a large size adjacent to the second layer 40b, (V in FIG. 1, the same applies hereinafter) may be located between the light emitting element 41 and the light emitting element 41. However, the present invention is not limited thereto, and it is also possible that the empty space V is not located.

The electrode layer 400 may be formed of various materials (e.g., metal materials such as silver, gold, copper, and aluminum) known in the art.

Next, as shown in FIG. 3N, the electrode layer 400 is patterned using an etching solution or etching paste capable of patterning an electrode layer (reference numeral 400 in FIG. 3). Thus, electrodes 42 and 44 are formed. As described above, since the protective layer 41 has a small thickness, the electrode layer 400 can be removed at the portion where the electrode layer 400 is removed when the electrode layer 400 is patterned. Then, the protective film 41 is partially left only in the portion where the electrodes 42 and 44 are located.

The first layer 40a can prevent the laser 200 from damaging the conductive type regions 32 and 34 when the second contact hole portion 46b is formed and the first contact hole portion 46a May be formed of an etching solution which does not etch the conductive type regions 32 and 34. [ As a result, damage to the conductive regions 32 and 34, which may occur when the contact hole 46 is formed, can be minimized. The passivation layer 41 may be formed to cover the portion where the contact hole 46 is formed to improve the passivation characteristics of the conductive regions 32 and 34 at the portion where the contact hole 46 is located. Since the protective film 41 is formed on the contact hole 46 when the first and second electrodes 42 and 44 or the electrode layer 400 are formed, the conductive regions 32 and 34 are not exposed to the outside. Therefore, it is possible to prevent the conductive type regions 32 and 34 from being damaged in the process of forming the first and second electrodes 42 and 44. Thus, the solar cell 100 having excellent characteristics and efficiency can be manufactured.

Hereinafter, a solar cell according to another embodiment of the present invention and a method of manufacturing the same will be described in detail with reference to FIGS. Detailed descriptions will be omitted for the same or extremely similar parts as those described above, and only different parts will be described in detail. Embodiments that combine the above-described embodiments and modifications and the embodiments and modifications described below are also within the scope of the present invention.

4 is a partial rear plan view of a solar cell according to another embodiment of the present invention. In FIG. 4, the rear passivation film (40 in FIG. 1) is omitted and the first and second conductivity type regions 32 and 34, the barrier region 36, and the first and second electrodes 42 and 44 ). The rear passivation film 40 may be formed of the first and second conductive type regions 32 and 34 and the barrier region 36 and the first and second electrodes 42 and 44. However, Respectively. In the portion of the back passivation film 40 where the first conductivity type region 32 overlaps with the first electrode 42, a contact hole (reference numeral 46 in FIG. 1) for connecting to the first conductivity type region 32, And a contact hole 46 for connecting to the second conductive type region 34 may be formed at a portion where the second conductive type region 34 and the second electrode 44 overlap.

Referring to FIG. 4, in the solar cell 100 according to the present embodiment, the second conductivity type regions 34 are formed in island shapes and are spaced apart from each other, 2 conductive type region 34 and the barrier region 36 surrounding the conductive type region 34

Then, the first conductive type region 32 functioning as the emitter region is formed with a maximally wide area, so that the photoelectric conversion efficiency can be improved. In addition, the second conductive type region 34 can be positioned entirely on the semiconductor substrate 10 while minimizing the area of the second conductive type region 34. The surface area of the second conductivity type region 34 can be maximized while effectively preventing the surface recombination by the second conductivity type region 34. However, the present invention is not limited thereto, and it goes without saying that the second conductivity type region 34 may have various shapes that minimize the area.

Although the second conductivity type region 34 has a circular shape in the drawing, the present invention is not limited thereto. Therefore, it is needless to say that the second conductivity type region 34 may have an elliptical shape or a polygonal planar shape such as a triangle, a square, or a hexagon.

5 is a cross-sectional view illustrating a portion of a solar cell according to another embodiment of the present invention. For clarity and simplicity, only the portion corresponding to the enlargement circle in Fig. 1 is shown in Fig.

Referring to FIG. 5, in this embodiment, the first electrode 42 may be formed entirely on the protective film 41 in the first contact hole portion 46a and the second contact hole portion 46b. For example, the first electrode 42 is formed by filling the first contact hole portion 46a and the second contact hole portion 46b as a whole. The protective layer 41 is formed on the surface of the first conductivity type region 32 and the first layer 40a even if a step or bend is formed on the side surfaces of the first layer 40a and the second layer 40b. (Or contact with) the side surfaces of the second layer 40b and the first electrode 42 on the protective layer 41 as a whole. The first electrode 42 can completely fill the contact hole 46 on the protective film 41 so that the void space v does not exist between the first electrode 42 and the side surfaces of the contact hole 46. [ This is because the first electrode 42 can be formed so as to fill the contact hole 46 entirely on the protective film 41 according to process conditions and the like. According to this, the volume and density of the first electrode 42 can be increased and the resistance can be reduced. The protective film 41 may also be located between the outer surface of the second layer 40b (the surface opposite to the first layer 40a) and the first electrode 42.

Although the first electrode 42 and the first conductivity type region 32 are mainly described in the drawings and the foregoing description, the above description is applicable to the case where the second electrode (reference numeral 44 in FIG. 1) and the second conductivity type region The reference numeral 34 of FIG.

6 is a cross-sectional view illustrating a portion of a solar cell according to another embodiment of the present invention. For clarity and simplicity, only the portion corresponding to the enlargement circle in Fig. 1 is shown in Fig.

Referring to FIG. 6, in this embodiment, the protective film 41 is formed only in the portions adjacent (or contacting) the first conductive type region 32 and the first layer 40a, .

More specifically, the protective film 41 is formed on the bottom surface of the contact hole 46 (that is, on the surface of the conductive type regions 32 and 34 exposed by the contact hole 46) And a portion positioned (e.g., in contact with) a side surface of the first layer 40a or the first contact hole portion 46a. The protective film 41 is formed on the side surfaces of the second layer 40b or the second contact hole portion 46b and on the inner surface of the second layer 40b (adjacent to the first layer 40a or the first conductive type region 32) Surface) and the outer surface (the surface opposite to the inner surface).

This is because the surface of the first conductive type region 32 can be easily oxidized by reaction with oxygen including a semiconductor (for example, silicon), so that it can be easily formed when the protective film 41 is composed of silicon oxide Because. When the first layer 40a includes an oxide (for example, silicon oxide) or an amorphous semiconductor (for example, amorphous silicon), and the protective film 41 is made of silicon oxide, 40a. ≪ / RTI > If the first layer 40a includes silicon oxide, a protective layer 41 including the same material can be easily formed. If the first layer 40a includes amorphous silicon, the first layer 40a easily reacts with oxygen to form silicon oxide This is because the protective film 41 can be formed. On the other hand, even if the second layer 40a contains silicon nitride or silicon carbide containing silicon or nitride because it contains nitride or carbide, a protective layer composed of silicon oxide, which is completely different from the silicon nitride or silicon carbide, (41) may be difficult to be formed.

Although the first electrode 42 and the first conductivity type region 32 are mainly described in the drawings and the foregoing description, the above description is applicable to the case where the second electrode (reference numeral 44 in FIG. 1) and the second conductivity type region The reference numeral 34 of FIG.

7 is a cross-sectional view illustrating a portion of a solar cell according to another embodiment of the present invention. For the sake of clarity and simplicity, only the portion corresponding to the enlargement circle in Fig. 1 is shown in Fig.

7, in this embodiment, the protective film 41 is formed only at a portion adjacent to the first conductive type region 32, and only a portion is formed or not formed at a portion adjacent to the first layer 40a, And is not formed in the portion adjacent to the recessed portion 40b.

More specifically, the protective film 41 is formed on the bottom surface of the contact hole 46 (that is, on the surface of the conductive type regions 32 and 34 exposed by the contact hole 46) . ≪ / RTI > The protective film 41 may be formed on the side of the first layer 40a or the first contact hole 46a at a portion contacting the bottom surface of the contact hole 46 (for example, in contact). Or the protective film 41 may be locally formed only on the first conductive type region 32 corresponding to the contact hole 46 and may not contact the side surface of the first contact hole portion 46a. Thus, the protective film 41 is not formed entirely on the side surfaces of the first layer 40a or the first contact hole 46a. The side surfaces of the second layer 40b or the second contact hole portion 46b and the inner surface of the second layer 40b (the surface adjacent to the first layer 40a or the first conductive type region 32) Is not formed on the surface (the opposite surface of the inner surface).

As described above, the surface of the first conductivity type region 32 may be easily oxidized by reaction with oxygen including a semiconductor (for example, silicon) to form a protective film 41 composed of silicon oxide. The first layer 40a is formed to have a small thickness, and the protective layer 41 may not be formed on the side surface of the first layer 40a due to the presence of undercuts or various process conditions. On the second layer 40b, the protective film 41 may not be formed for the same reason as described with reference to FIG.

Although the first electrode 42 and the first conductivity type region 32 are mainly described in the drawings and the foregoing description, the above description is applicable to the case where the second electrode (reference numeral 44 in FIG. 1) and the second conductivity type region The reference numeral 34 of FIG.

The protective film 41 is formed after the contact hole portion 46 is formed and is not located between the passivation film 40 and the conductive type regions 32 and 34 in this embodiment. The electrodes 42 and 44 may be spaced apart from the conductive regions 32 and 34 with the protective film 41 therebetween.

In the above-described drawings, the protective film 41 has a clear boundary with the first layer 40a, and the protective film 41 and the first layer 40a are completely different layers. However, the protective layer 41 and the first layer 40a may include the same material (for example, silicon oxide). In this case, a boundary is separately provided between the protective layer 41 and the first layer 40a . In this case, the first layer 40a or the silicon oxide layer is formed to have a thin thickness adjacent (or in contact with) the conductive regions 32 and 34 in the portion where the contact hole 46 is formed, and the contact hole 46 It may be judged or measured that the first layer 40a or the silicon oxide layer is formed to have a thicker thickness in a portion where the first layer 40a is not formed. In the embodiment of FIGS. 1 and 5, it may be determined or measured that the first layer 40a or the silicon oxide layer is extended between the second layer 40b and the electrodes 42 and 44.

8 is a cross-sectional view illustrating a portion of a solar cell according to another embodiment of the present invention. 8 shows a portion corresponding to the enlargement circle of Fig. 1 for the sake of simplicity and clarity.

8, in the present embodiment, the protection film 41 is formed on the bottom surface of the contact hole 46 (i.e., the surface of the conductive type regions 32 and 34 exposed by the contact hole 46) For example, contact).

The protective film 41 is not formed on the surface of the second layer 40b of the rear passivation film 40 opposite to the second conductivity type region 32 in this embodiment. This is because the protective layer 41 is formed on the surface of the second layer 40b opposite to the second conductive type region 32 in the portion of the first contact hole portion 46a located below the second layer 40b It may be difficult to form. Alternatively, the protective film 41 may be formed on the surface of the second conductive type region 32 located below the second layer 40b of the first contact hole portion 46a and / or on the side surface of the first contact hole portion 46a . This is because it is difficult for the protective film 41 to be formed on the surface in the manufacturing process. As described above, the protective film 41 may not be formed at a portion of the first contact hole 46a adjacent to the empty space V located below the second layer 40b.

Alternatively, the protective film 41 may be formed on the side surface of the second layer 40b and / or on the second layer 40b (the first electrode 42 in the drawing and / or the second electrode 44, (Hereinafter referred to as " electrodes 42 and 44 "). This may be because the protective film 41 is intentionally removed before the formation of the electrodes 42 and 44 or during another process and the protective film 41 is formed with a certain pattern As shown in FIG.

The protective film 41 is formed only in the second conductivity type region 32 corresponding to the portion where the electrodes 42 and 44 are formed. However, the protective film 41 may be formed on the portion adjacent to the void space V, Or on the side surface or the surface of the layer 40b.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
10: semiconductor substrate
32: first conductivity type region
34: second conductivity type region
36: Barrier area
40: rear passivation film
40a: First layer
40b: second layer
42: first electrode
44: Second electrode
46: contact hole
46a: first contact hole portion
46b: second contact hole portion

Claims (20)

A semiconductor substrate;
A conductive type region including a first conductive type region and a second conductive type region formed on one surface of the semiconductor substrate;
A passivation film formed on the conductive region and having a contact hole;
A passivation film formed on the conductive region within the contact hole, the passivation film being formed on at least one of the inner surface of the contact hole and the passivation film; And
An electrode electrically connected to the conductive region through the contact hole with the protective film interposed therebetween;
≪ / RTI > The method according to claim 1,
Wherein the protective film is formed entirely in a portion between the electrode and the passivation film where the electrode is formed. The method according to claim 1,
Wherein the protective film is formed on at least a part of the inner surface of the passivation film and on the conductive type region exposed through the contact hole. The method according to claim 1,
Wherein the passivation film comprises a first layer overlying the conductive region and a second layer overlying the first layer and comprising a material different from the first layer. 5. The method of claim 4,
Wherein the contact hole includes a first contact hole portion formed in the first layer and a second contact hole portion formed in the second layer and communicating with the first contact hole portion,
Wherein the first contact hole includes a portion larger than the second contact hole or a step is located between an inner surface of the first contact hole and an inner surface of the second contact hole. 5. The method of claim 4,
Wherein a size of the first contact hole portion is larger in a portion adjacent to the second layer than a portion adjacent to the conductive type region. The method according to claim 1,
The passivation film is formed in contact with the side surface of the passivation film,
And the electrode is spaced apart from the conductive region on the protective film. The method of claim 3,
Wherein a band gap of the first layer is larger than a band gap of the second layer. The method of claim 3,
Wherein a thickness of the protective film is smaller than that of each of the first layer and the second layer. The method of claim 3,
Wherein the first layer comprises an oxide or an amorphous semiconductor,
Wherein the second layer comprises nitride or carbide,
Wherein the protective film comprises an oxide. A semiconductor substrate;
A conductive type region including a first conductive type region and a second conductive type region formed on one surface of the semiconductor substrate;
A passivation film formed on the conductive region and having a contact hole;
A protective film formed on the conductive region in the contact hole; And
An electrode electrically connected to the conductive region through the contact hole with the protective film interposed therebetween;
/ RTI >
Wherein the passivation film comprises a first layer overlying the conductive region and a second layer overlying the first layer and comprising a material different from the first layer,
Wherein the contact hole includes a first contact hole portion formed in the first layer and a second contact hole portion formed in the second layer and communicating with the first contact hole portion,
Wherein the first contact hole includes a portion larger than the second contact hole or a step is located between an inner surface of the first contact hole and an inner surface of the second contact hole. Forming a conductive type region including a first conductive type region and a second conductive type region on one surface of a semiconductor substrate;
Forming a passivation film having a contact hole on the conductive type region;
Forming a protective film on the conductive region exposed through the contact hole; And
Forming an electrode electrically connected to the conductive region through the contact hole of the passivation film with the protective film interposed therebetween
Wherein the method comprises the steps of: 13. The method of claim 12,
Wherein forming the passivation film comprises:
Forming a first layer over the conductive region; And
Forming a second layer overlying the first layer and comprising a material different from the first layer;
Forming a second contact hole through the second layer; And
Forming a first contact hole penetrating through the first layer by a method different from the method of forming the second contact hole part, forming the contact hole composed of the second contact hole part and the first contact hole part
Wherein the method comprises the steps of: 14. The method of claim 13,
Wherein the second contact hole is formed by laser etching in the step of forming the second contact hole, and the first layer remains. 15. The method of claim 14,
Wherein the first contact holes are formed by wet etching in the step of forming the first contact holes. 16. The method of claim 15,
And the first contact hole portion includes an undercut. 13. The method of claim 12,
Wherein the protective film is formed by chemical oxidation. 12. The method of claim 11,
Wherein the protective film is formed on the conductive region in at least the contact hole in the step of forming the protective film. 19. The method of claim 18,
Wherein the protective film is further formed on at least one of an inner surface of the contact hole and an outer surface of the passivation film. 13. The method of claim 12,
Wherein the first layer and the second layer are formed by an in-situ process by chemical vapor deposition,
Wherein the electrode is formed by sputtering or plating.

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