KR20160094503A - Testing method of mother substrate for display device - Google Patents

Abstract

The present invention provides a mother board for a display device capable of inspecting a defective pixel by disposing an inspecting gate driver in a dummy portion of a mother substrate and an inspecting method thereof, Wherein the first to the n-th gate built-in circuits successively output the first to the n-th gate signals to the first to the n-th gate wirings to perform inspection, and then remove the dummy portion.

Description

[0001] The present invention relates to a mother board for a display device,

The present invention relates to a mother board for a display device, and more particularly, to a mother board inspection method for a display device capable of inspecting a defective pixel by arranging an inspection gate driver in a dummy portion of a mother board.

The display device includes a plurality of first substrates formed on a first mother substrate having a large area, a plurality of second substrates formed on a second mother substrate, and two first mother substrates and a second mother substrate, A plurality of display panels are simultaneously formed to improve the yield.

Accordingly, a process of cutting the first and second mother substrates to a plurality of unit display panels is required.

At this time, gate lines and data lines are arranged in an intersecting manner on the display panel, and pixels are located at intersections of the gate lines and the data lines.

Each of the display devices includes a gate driver for driving the gate wiring, a data driver for driving the data line, a timing controller for controlling the gate driver and the data driver, and a power supply for supplying the driving voltage.

The timing controller controls the driving timings of the gate driver and the data driver and supplies a data signal to the data driver.

The power supply unit generates driving voltages such as a common voltage (Vcom), a gate high voltage (Vgh), a gate low voltage (Vgl), and the like by using an input power source.

The gate driver sequentially supplies the gate signal to the gate line, and the data driver supplies the data signal to each data line each time a gate signal is supplied to the gate line.

At this time, the data driver and the gate driver are integrated into several ICs (Integrated Circuits).

The integrated data driving IC is mounted on a TCP (Tape Carrier Package), connected to a liquid crystal panel by a TAB (Tape Automated Bonding) method, and the integrated gate driving IC is mounted on a display panel by a COG (Chip On Glass) method .

Here, the data driving IC receives a control signal and a driving voltage from a PCB (Printed Circuit Board) (i.e., a timing control unit and a power supply unit) connected to the TCP.

The gate driving IC receives a control signal and driving voltages from a timing control unit and a power supply unit through signal wiring mounted on a line-on-glass type.

On the other hand, before the TCP is connected to the display panel, defective pixels on the display panel are inspected using a display panel inspection apparatus (Auto Probe).

That is, after the display panel is completed, the defective pixels are checked and the checked defective pixels are repaired to secure a reliable display panel.

 After securing the reliability of the display panel, TCP is connected to the display panel.

1 is a schematic view showing a part of a conventional mother board.

As shown in the drawing, the mother substrate 10 includes a plurality of first substrates 1 divided into a display area AA in which an image is displayed and a non-display area NAA arranged outside the display area AA, And a dummy portion DMY disposed outside the non-display area NAA of the first substrate 1. [

In this case, the first to nth gate wirings GL1 to GLn are arranged in the display area AA of the first substrate 1, and the first to nth gate wirings GL1 to GLn And a gate pad portion 5 connected to the gate pad portion 5 are disposed.

Each of the first to nth gate wirings GL1 to GLn is connected to the gate pad portion 5 through the first to nth gate link wirings GLL1 to GLLn arranged in the non-display area NAA.

A plurality of data lines DL cross the first to the n-th gate lines GL1 to GLn and are disposed in the display region AA. The first to n-th gate lines GL1 to GLn and the plurality of data A thin film transistor (not shown) is disposed at an intersection of the wirings DL.

On the other hand, the dummy portion DMY is an area which is removed in the cutting step of cutting along the line along which the object is to be cut SL formed on the mother substrate 10.

In order to inspect the defective pixels of the first substrate 1 formed on the mother substrate 10, gate signals must be sequentially output to the first to nth gate wirings GL1 to GLn.

To this end, a gate driver for inspection (not shown) is brought into direct contact with the gate pad portion 5 to sequentially apply gate signals to the gate lines GL1 to GLn.

The gate pad unit 5 includes a plurality of gate pads (not shown) for applying gate signals to the respective gate lines GL1 to GLn. The gate pads (not shown) are connected to the gate lines GL1 to GLn, Are arranged in the same number as the number.

The inspecting gate driver (not shown) has a plurality of pins which are in contact with respective gate pads (not shown). These pins are arranged in the same number as the number of gate pads do.

Particularly, in the case of a high-resolution display device, the interval between the gate lines GL1 to GLn and the interval between the gate pads (not shown) are narrowly narrowed and accordingly the gate driver for inspection The spacing of the pins of the semiconductor device is also narrow.

Due to such a narrow gap, when inspecting the gate driving part (not shown) for inspection by contacting the gate pad part 5, the gate pad (not shown) and the inspection gate driver (not shown) Misalignment occurs frequently, and the data pad unit 5 is damaged when adjusting the misalignment, which increases the time required for the inspection.

SUMMARY OF THE INVENTION The present invention has been conceived to solve the above-mentioned problems of the prior art, and it is an object of the present invention to provide an inspection gate driving unit in a dummy portion of a mother board, And a method for inspecting a mother board for an apparatus.

According to an aspect of the present invention, there is provided a liquid crystal display device including a plurality of first substrates divided into a display region in which an image is displayed, a non-display region disposed outside the display region, a dummy portion arranged outside the non- And a gate driver disposed in the dummy portion and connected to the gate pad portion, the gate driver portion being disposed in the non-display region and connected to the first to the n-th gate lines, A mother board for a display device is provided.

The inspection gate driver includes first to nth gate built-in circuits, and the first to nth gate built-in circuits sequentially output first to nth gate signals to first to nth gate wirings.

Further, the inspection gate driver is connected to at least one start signal line and a clock signal line arranged in the dummy portion.

The dummy portion further includes a test pad portion for applying a start signal and a clock signal to the start signal wiring and the clock signal wiring, respectively.

Also, first to nth gate link wirings for connecting the first to nth gate wirings and the gate pad portion, and first to nth test link wirings for connecting the gate pad portion and the inspection gate driver are further included.

The thin film transistor further includes a plurality of data lines disposed in the display region and intersecting the first to the n-th gate lines, and a thin film transistor disposed at the intersection of the first to the n-th gate lines and the plurality of data lines.

In the method for inspecting a mother substrate for a display device, the step of inspecting the mother substrate by the inspection gate driving unit disposed in the dummy unit, and the step of forming the plurality of first substrates by cutting the mother substrate and removing the dummy unit The present invention provides a method of inspecting a mother board including a mother board.

In the method for inspecting a mother substrate for a display device, the step of cutting the mother substrate into a plurality of first substrates provided with dummy portions and the step of inspecting the plurality of first substrates by the inspection gate driver arranged in the dummy portion And cutting the dummy portion attached to the plurality of first substrates.

The step of inspecting the mother substrate or the first substrate may include a step in which the first gate built-in circuit receives the start signal and the first clock signal and outputs a first gate signal to the first gate wiring, The first gate signal and the second clock signal, and outputting a second gate signal to the second gate wiring; and a third gate integrated circuit receiving the second gate signal and the third clock signal, A step of outputting a third gate signal to the first gate wiring, a step of outputting a fourth gate signal to the fourth gate wiring by receiving the third gate signal and the fourth clock signal, And outputting the n-th gate signal.

According to the present invention, inspecting is performed by disposing the inspecting gate driver in the dummy portion of the mother substrate, inspection can be performed without contacting the inspecting gate driver directly with the gate pad portion, and damage to the gate pad portion can be prevented.

In addition, it is possible to prevent misalignment caused by contacting the inspection gate driver directly with the gate pad portion, thereby shortening the inspection time.

1 is a view schematically showing a part of a conventional mother board.
2 is a view schematically showing a part of a mother board according to an embodiment of the present invention.
FIG. 3 is a block diagram of the inspection gate driving unit of FIG. 2, illustrating a method of inspecting a mother substrate according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a schematic view showing a part of a mother board according to an embodiment of the present invention. FIG. 3 is a block diagram of the inspection gate driving unit of FIG. 2, illustrating a method of inspecting a mother board according to an embodiment of the present invention Fig.

As shown in the drawing, the mother substrate 100 according to the present invention includes a plurality of first substrates (not shown) divided into a display area AA in which an image is displayed and a non-display area NAA disposed outside the display area AA A display region 11, and a dummy portion DMY disposed outside the non-display region NAA.

In this case, the first to nth gate wirings GL1 to GLn are disposed in the display area AA of the first substrate 11, and the first to nth gate wirings GL1 to GLn And a gate pad portion 50 connected to the gate pad portion 50 are disposed.

The inspection gate drive unit 70 connected to the gate pad unit 50 is disposed in the dummy DMY.

At this time, the first to nth gate wirings GL1 to GLn are connected to the gate pad portion 50 through the first to nth gate link wirings GLL1 to GLLn arranged in the non-display area NAA, The gate pad unit 50 is connected to the inspection gate driver 70 through the first to nth test link lines TLL1 to TLLn.

The gate pad unit 50 includes a plurality of gate pads for sequentially applying gate signals to the first to nth gate wirings GL1 to GLn.

A plurality of data lines DL cross the first to the n-th gate lines GL1 to GLn and are disposed in the display region AA. The first to n-th gate lines GL1 to GLn and the plurality of data A thin film transistor (not shown) is disposed at an intersection of the wirings DL.

The first to n-th gate built-in circuits GIP1 to GIPn include first through n-th gate interconnections GL1 through GLn ) Sequentially from the first to n-th gate signals Vout1 to Voutn.

At this time, the gate built-in circuits GIP1 to GIPn are formed together when a thin film transistor (not shown) arranged in the display area AA is formed, so that a separate gate driver for inspection (not shown) 50).

The inspection gate driver 70 is connected to at least one of the start signal lines VSL and the clock signal lines CL1 to CL4 and starts the start signal line VSL and the clock signal lines CL1 to CL4, And a test pad unit 90 for applying the signal VST and the clock signals CLK1 to CLK4.

At this time, the start signal line (VSL), the clock signal lines (CL1 to CL4), and the test pad portion (90) are arranged in the dummy portion (DMY).

That is, in the mother substrate 100 according to the embodiment of the present invention, the gate driver for inspection 70, the start signal line VSL, the clock signal lines CL1 to CL4, and the test pad unit 90 are connected to the dummy portion DMY ) To inspect the defective pixels of a plurality of first substrates 11 arranged on the mother substrate 100 before cutting operation at the same time and then cut along the line SL to be cut formed on the mother substrate 100 Is removed together with the dummy portion (DMY) during the cutting process.

The mother substrate 100 is cut into a plurality of first substrates with the dummy DMY attached thereto and the first substrate in a state in which the dummy DMY is attached is inspected, May be cut off and removed.

Accordingly, in the mother substrate 100 according to the embodiment of the present invention, the gate built-in circuits GIP1 to GIPn are disposed in the dummy DMY, and a separate inspection gate driver (not shown) It is possible to perform the inspection without contacting the gate pad portion 50, thereby preventing the gate pad portion 50 from being damaged.

In addition, it is possible to prevent misalignment caused by contacting the inspection gate driver (not shown) directly with the gate pad portion 50, thereby shortening the inspection time.

After the inspection of the plurality of first substrates 11 formed on the mother substrate 100 described above is completed, a TCP (Tape Carrier Package) on which a gate driving integrated circuit (IC) is mounted is connected to the gate pad unit 50 , The dummy portion DMY is removed and a plurality of first substrates 11 are formed by performing the cutting process.

Next, an inspection method of the mother substrate 100 according to the embodiment of the present invention will be described.

The gate signals Vout1 to Voutn output from the respective gate built-in circuits GIP1 to GIPn are sequentially supplied to the gate wirings GL1 to GLn.

Specifically, the first gate built-in circuit GIP1 outputs the first gate signal Vout1 to the first gate wiring GL1, the second gate built-in circuit GIP2 outputs the second gate signal GL2 to the second gate wiring GL2, The third gate internal circuit GIP3 outputs the third gate signal Vout3 to the third gate wiring GL3 and the fourth gate internal circuit GIP4 outputs the third gate signal Vout3, The ninth gate internal circuit GIPn outputs the nth gate signal Voutn to the nth gate wiring GLn.

Since the first gate built-in circuit (GIP1) does not have a gate built-in circuit of the previous stage, it can not start receiving the gate signal of the gate built-in circuit of the previous stage as a trigger signal, (VST).

Accordingly, when the start signal VST is applied to the first gate internal circuit GIP1, the first gate internal circuit GIP1 outputs the first gate signal Vout1 using the first clock signal CLK1 , The first gate signal Vout1 outputted from the first gate built-in circuit GIP1 is supplied to the second gate built-in circuit GIP2 to start the second gate built-in circuit GIP2, (GIP2) outputs the second gate signal (Vout2) using the second clock signal (CLK2).

Next, the second gate signal Vout2 outputted from the second gate built-in circuit GIP2 is supplied to the third gate built-in circuit GIP3 to start the third gate built-in circuit GIP3, The circuit GIP3 outputs the third gate signal Vout3 using the third clock signal CLK3 and the third gate signal Vout3 output from the third gate internal circuit GIP3 is output to the fourth gate built- The fourth gate built-in circuit GIP4 outputs the fourth gate signal Vout4 using the fourth clock signal CLK4, and the fourth gate built-in circuit GIP4 outputs the fourth gate signal Vout4, ..., the n-th gate built-in circuit GIPn outputs the n-th gate signal Voutn.

After inspecting the defective pixels of the mother substrate 100, the inspecting gate driver 70, the start signal line VSL and the clock signal lines CL1 to CL4, which are disposed in the dummy portion DMY, The inspection can be performed without contacting the gate pad portion 50 directly to the gate pad portion 50. This prevents the gate pad portion 50 from being damaged can do.

In addition, it is possible to prevent misalignment caused by contacting the inspection gate driver (not shown) directly with the gate pad portion 50, thereby shortening the inspection time.

The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

11: a first substrate
100: Mosquito board
GL1 to GLn: first to nth gate wirings
50: gate pad portion
70: Gate driver for inspection
90: Test pad section

Claims (6)

A display device comprising: a plurality of first substrates divided into a display area in which an image is displayed and a non-display area disposed outside the display area; a dummy part arranged outside the non-display area; and a gate driver disposed in the non-display area and connected to the first to the n-th gate lines, and a gate driver for inspection connected to the gate pad, In a method for inspecting a mother board,
Inspecting the mother board by the inspection gate driver disposed in the dummy section; And
Cutting the mother substrate to form the plurality of first substrates, removing the dummy unit
Wherein the inspecting method comprises the steps of:
The method according to claim 1,
Wherein the first to the n-th gate built-in circuits include first to n-th gate interconnection lines for sequentially outputting first to n-th gate signals to the first to n- Method of inspecting a motherboard for a device.
3. The method of claim 2,
The step of inspecting the mother board,
The first gate built-in circuit receiving the start signal and the first clock signal and outputting the first gate signal to the first gate line;
Wherein the second gate built-in circuit receives the first gate signal and the second clock signal and outputs the second gate signal to the second gate wiring;
The third gate built-in circuit receiving the second gate signal and the third clock signal and outputting the third gate signal to the third gate wiring;
The fourth gate built-in circuit receiving the third gate signal and the fourth clock signal and outputting the fourth gate signal to the fourth gate wiring; And
Wherein the n-th gate built-in circuit outputs the n-th gate signal to the n-th gate wiring
Wherein the inspecting method comprises the steps of:
A display device comprising: a plurality of first substrates divided into a display area in which an image is displayed and a non-display area disposed outside the display area; a dummy part arranged outside the non-display area; and a gate driver disposed in the non-display area and connected to the first to the n-th gate lines, and a gate driver for inspection connected to the gate pad, In a method for inspecting a mother board,
Cutting the mother substrate to the plurality of first substrates to which the dummy unit is attached;
Inspecting the plurality of first substrates by the inspecting gate driver disposed in the dummy portion; And
Cutting the dummy portion attached to the plurality of first substrates
Wherein the inspecting method comprises the steps of:
5. The method of claim 4,
Wherein the first to the n-th gate built-in circuits include first to n-th gate interconnection lines for sequentially outputting first to n-th gate signals to the first to n- Method of inspecting a motherboard for a device.
6. The method of claim 5,
The step of inspecting the plurality of first substrates, respectively,
The first gate built-in circuit receiving the start signal and the first clock signal and outputting the first gate signal to the first gate line;
Wherein the second gate built-in circuit receives the first gate signal and the second clock signal and outputs the second gate signal to the second gate wiring;
The third gate built-in circuit receiving the second gate signal and the third clock signal and outputting the third gate signal to the third gate wiring;
The fourth gate built-in circuit receiving the third gate signal and the fourth clock signal and outputting the fourth gate signal to the fourth gate wiring; And
Wherein the n-th gate built-in circuit outputs the n-th gate signal to the n-th gate wiring
Wherein the inspecting method comprises the steps of:

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