KR20150087743A - Method and apparatus for controlling a memory synchronization on multi-threading processor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory synchronization control method and apparatus in a multi-threading processor, and more particularly, to a memory-pool control method and apparatus for a memory- And more particularly to a method and apparatus for controlling synchronization for each of the memory pools.
A memory synchronization control method in a multi-threading processor according to the present invention includes: generating a memory pool allocated from a system memory in response to generation of a thread; registering an identifier capable of identifying a memory pool; Mapping the thread to a thread, allocating memory to the thread from the memory pool, returning the allocated memory to the memory pool in response to the thread's expiration, releasing the system memory for the memory pool, And deleting the step and synchronization variable.
According to the memory synchronization control method in the multithreading processor of the present invention, a memory pool corresponding to one or more threads is created in the system memory to perform synchronization for each corresponding memory pool for each thread, It is possible to save the waiting time required for the hardware and the memory, and to use the hardware and the memory efficiently.

Description

METHOD AND APPARATUS CONTROLLING A MEMORY SYNCHRONIZATION ON MULTI-THREADING PROCESSOR BACKGROUND OF THE INVENTION [0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory synchronization control method and apparatus in a multi-threading processor, and more particularly, to a memory-pool control method and apparatus for a memory- And more particularly to a method and apparatus for controlling synchronization for each of the memory pools.

Background of the Invention [0002] With the development of integrated circuit technology for computing devices, a multi-core CPU and a multi-threading processor utilizing a large-capacity memory technology have become popular.

In the conventional memory synchronization method, even though a plurality of threads are used, since only one thread can access the memory at a moment, the remaining threads can not access the memory until the memory access is released. did. Further, as the memory allocation and release are frequently performed in a plurality of threads, there is a problem that performance is deteriorated due to waiting time due to memory synchronization. In this regard, some techniques for synchronizing a plurality of threads and memories have also improved the approach to memory in a thread, but have not been able to utilize a multi-core CPU and a multi-threading processor based on a large amount of memory.

Therefore, in order to synchronize a thread and a memory in a multi-threading processor, development of a memory synchronization method and apparatus capable of efficiently utilizing a multi-core CPU and a large-capacity memory has been required.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems occurring in the prior art, and it is an object of the present invention to provide a multi-threading processor capable of generating a memory-pool corresponding to one or more threads in a system memory, In order to reduce the waiting time.

Another object of the present invention is to efficiently utilize hardware and memory by minimizing the waiting time required for memory synchronization in a multi-threading processor.

The problems of the present invention are not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a method for controlling memory synchronization in a multi-threading processor, the method comprising: generating a memory pool allocated from a system memory in response to generation of a thread; Creating a synchronization variable for the memory pool and mapping it to the thread, allocating memory to the thread from the memory pool, returning the memory allocated to the thread to the memory pool, Releasing system memory for the memory pool, and deleting the synchronization variable.

According to another aspect of the invention, allocating memory from a memory pool to a thread includes: pinning a synchronization variable for the memory pool; allocating memory for the thread to the thread; writing the identifier to the memory; And unlocking the synchronization variable for the pool.

According to another aspect of the present invention, the step of releasing the memory pool comprises the steps of: detecting an identifier from memory; pinning a synchronization variable for the memory pool having the identifier; returning the memory to the memory pool; And releasing the fixation of the synchronization variable with respect to the synchronization variable.

According to another aspect of the present invention, a plurality of threads are provided.

According to an aspect of the present invention, there is provided a computer-readable medium including a set of instructions, the set of instructions including instructions for: It creates a memory pool, registers an identifier that can identify the memory pool, creates a synchronization variable for the memory pool, maps it to the thread, allocates memory from the memory pool to the thread, Returning the allocated memory to the memory pool, releasing the system memory for the memory pool, and deleting the synchronization variable.

In accordance with another aspect of the present invention, a set of instructions for causing a thread to allocate memory from a memory pool includes fixing a synchronization variable for the memory pool, allocating memory for the memory pool to the thread, And a set of instructions to cause the unlocking of the synchronization variables for the memory pool.

In accordance with another aspect of the present invention, a set of instructions for causing a memory pool to be released includes detecting the identifier from memory, fixing a synchronization variable for the memory pool having the identifier, returning the memory to the memory pool, And a set of instructions for causing the synchronization variable for the pool to be unlocked.

According to another aspect of the present invention, a plurality of threads are provided.

According to an aspect of the present invention, there is provided an apparatus for controlling a memory synchronization in a multithreading processor, the apparatus comprising: a memory pool allocated from a system memory in response to generation of a thread; And allocates memory to the thread from the memory pool, returns the allocated memory to the memory pool in response to the termination of the thread, and writes the system to the memory pool A control unit for releasing the memory and deleting the synchronization variable, and a recognition unit for recognizing generation and disappearance of the thread and transmitting the recognition to the control unit.

According to the method and apparatus for controlling memory synchronization in a multi-threading processor of the present invention, a memory pool corresponding to one or more threads is created in a system memory to perform synchronization for each corresponding memory pool for each thread, This has the effect of saving the waiting time for memory synchronization.

According to the method and apparatus for controlling memory synchronization in the multithreading processor of the present invention, it is possible to efficiently utilize hardware and memory by minimizing the waiting time required for memory synchronization.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 shows a schematic configuration of a memory synchronization control algorithm in a multithreading processor according to an embodiment of the present invention.
2A and 2B illustrate a general memory synchronization structure in a multi-threading processor and an embodiment of a memory synchronization structure according to an embodiment of the present invention.
3 is a flowchart of a method for controlling memory synchronization in a multi-threading processor according to an embodiment of the present invention.
4A and 4B are flowcharts of a method for controlling memory synchronization in a multi-threading processor according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

Although the first, second, etc. are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, it is needless to say that the first component mentioned below may be the second component within the technical spirit of the present invention.

In the drawings, the same reference numerals are used for the same elements in different drawings unless otherwise indicated.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other partially or entirely and technically various interlocking and driving is possible as will be appreciated by those skilled in the art, It may be possible to cooperate with each other in association.

Transmission is not limited to transmission of information and signals directly between a receiving object and a transmitting object, but includes transmission through other components.

In this specification, a thread refers to a control flow or an execution unit that executes a task in a computing program, in particular, a process. A multi-threading processor is a program in which a plurality of threads operate simultaneously Means a processor that can process a task concurrently or divide one task in parallel.

As used herein, a system memory refers to an entire memory including a storage area of various variables used by a user or a computing program, such as a stack area, a heap area, a data area, and a code area, Area.

A memory-pool is a block-by-block memory having a specific size allocated to a heap area corresponding to a memory area that is allocated and released as needed during execution of a computing program. Assignment means allocating the memory of the heap area in which the memory pool is created to a place where memory is needed.

Various embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

1 shows a schematic configuration of a memory synchronization control algorithm in a multithreading processor according to an embodiment of the present invention.

1, an apparatus 100 for performing a memory synchronization control algorithm in a multithreading processor according to an embodiment of the present invention (hereinafter, referred to as a 'memory synchronization control apparatus') includes a recognition unit 110 and a control unit 120).

The memory synchronization control apparatus 100 according to an embodiment of the present invention is an apparatus having a function capable of performing a computing task utilizing a multi-thread, and includes a computer, a notebook, a smart phone, a tablet ) Computers, and the present invention is not limited to any particular terminal as long as it is a device having a central processing unit and a system memory capable of executing a multithreaded processor.

The recognition unit 110 of the memory synchronization control apparatus 100 recognizes the generation and disappearance of the thread and delivers the thread to the control unit 120 to be described later.

A thread is a unit of execution in which only execution control is separated in a process which means a program being executed. It is a basic unit using a processor and represents a single control flow that can execute an instruction singly. The generation of a thread recognized by the recognition unit 110 of the memory synchronization control apparatus 100 according to an exemplary embodiment of the present invention is performed by using one or more threads created in one process and each thread And the extinction of the thread also includes all of the above-mentioned threads.

The control unit 120 performs operations such as executing a program or a set of instructions stored in the system memory in response to the generation and destruction of the thread received from the recognition unit 110, thereby obtaining a synchronization variable for the memory pool and the memory pool, . It is also configured to allocate memory from the memory pool to the thread and return the allocated memory to the memory pool. A process and a method for performing the memory synchronization control of the controller 120 will be described later in detail with reference to FIGS. 3 and 4. FIG.

FIG. 2A illustrates a general memory synchronization structure in a multithreading processor, and FIG. 2B illustrates an embodiment of a memory synchronization structure in accordance with an embodiment of the present invention.

2A depicts a general memory synchronization architecture in a multithreaded processor, including a central processing unit 210, a process 220, and a system memory 230. As shown in FIG. In FIG. 2A, it is assumed that the central processing unit 210 is a quad-core processor having four cores.

As shown in FIG. 2A, when a central processing unit 210 corresponding to a CPU of a computing device is configured with a quad core having four cores, and each core generates one thread in the process 220, Each thread synchronizes with the system memory 230 through a synchronization variable generated in a data area 240 in which a global variable and a static variable in the system memory 230 are stored, And the memory of the heap area 250, which is an area, is allocated.

That is, according to the conventional method, when the central processing unit 210 having four multi-cores generates one thread through the process 220 and synchronizes with the system memory 230, Since synchronization is performed with one synchronization variable generated in the data area 240 of the thread 230, only one thread can access the system memory 230 at a certain moment, and in the remaining thread, Access to the system memory 230 is disabled until the memory access is released and the memory is allocated from the heap area 250. In addition, the more memory allocation and deallocation are made in multiple threads, the lower the performance due to the waiting time due to memory synchronization.

2B illustrates a memory synchronization structure in a multi-threading processor according to an embodiment of the present invention. As shown in FIG. 2A, the memory includes a central processing unit 210, a process 220, and a system memory 230 . That is, the memory synchronization control method in the multi-threading processor according to the present invention can be implemented using a conventional processor.

As shown in FIG. 2B, the memory synchronization structure according to an embodiment of the present invention corresponds to each thread generated through the process 220 in the data area 240 of the system memory 230, unlike FIG. 2A Synchronization variables are generated and synchronized with the generated memory pool in the heap area 250 of the system memory 230 via each synchronization variable to determine whether or not access to the system memory 230 in the other thread It is possible to access the system memory 230 without allocating memory from the memory pool. That is, by implementing synchronization for accessing each memory pool rather than synchronizing access to the system memory 230, the parallel processing of the central processing unit 210 and the process 220 is performed by minimizing the time required for the memory synchronization do.

3 is a flowchart of a method for controlling memory synchronization in a multi-threading processor according to an embodiment of the present invention. Will be described with reference to Fig. 1 for convenience of explanation.

First, when the recognition unit 110 recognizes generation of a thread, the control unit 120 allocates a system memory corresponding to generation of a thread to generate a memory pool (S300). At this time, as described above, the recognition unit 110 recognizes generation of a thread including all of the threads generated from one or more threads and a plurality of processes, and transmits the recognized thread to the controller.

When the memory pool is created, the controller 120 registers an identifier for the memory pool (S310). The identifier is a unique code that can distinguish each memory pool when a plurality of memory pools are created. By using a memory pool having an identifier so that allocation and return of the memory is performed for a specific area, Or a speed reduction due to a memory fragmentation phenomenon in which a usable area of the memory is divided into several pieces.

When an identifier for the memory pool is registered (S310), the controller 120 generates a synchronization variable for the memory pool and maps it to the thread (S320). Such a mapping can be performed through an identifier registered in a thread, and a dedicated memory pool can be allocated for each thread when a thread is created through mapping. In addition, when a plurality of memory pools are created corresponding to a plurality of threads, by creating and managing synchronization variables for each of the memory pools, it is possible to prevent a plurality of threads from simultaneously accessing one memory pool, Synchronization between each memory pool and the thread can be performed.

When the mapping between the memory pool and the thread is completed, the controller 120 allocates memory to the thread from the memory pool (S330). At this time, the control unit 120 performs synchronization between the thread and the memory pool through setting and releasing the lock on the synchronization variable of the memory pool, and records the identifier of the memory pool in the allocated memory, You can return memory to the pool again. The memory allocation of such a memory pool will be described later in detail in FIG. 4A.

When the operation of the thread is completed and the thread disappears, the controller 120 returns the memory allocated to the thread to the memory pool (S340). At this time, the controller 120 allocates It can return memory to the memory pool it receives. The return of such a memory will be described later in detail in Fig. 4B.

When the return of the memory to the memory pool is completed, the controller 120 releases the system memory for the memory pool (S350) and deletes the synchronization variable for the current thread (S360). In this case, the memory allocated to the threads from the memory pool and the memory pool refers to the memory of the heap area required for performing the operation of the process among the areas of the system memory, and the creation and deletion of the synchronization variables are performed in the data area of the system memory.

FIG. 4A is a flowchart illustrating a method of allocating memory to a thread from a memory pool in a memory synchronization control method in a multithreading processor according to an embodiment of the present invention. Referring to FIG. Will be described with reference to Fig. 1 for convenience of explanation.

When the task of allocating memory from the memory pool to the thread is started, the controller 120 fixes the synchronization variable for the memory pool (S331). Thus, by fixing the synchronization variables, it is possible to allocate a dedicated memory pool for each thread, and prevent multiple threads from simultaneously accessing one memory pool.

If the synchronization variable for the memory pool is fixed, the controller 120 allocates the memory of the memory pool to the thread (S332), and records the identifier for the memory pool in the allocated memory (S333). If an identifier for a memory pool is written to the allocated memory, and then the memory is returned, the empty space of the memory or the usable area of the memory is divided into several pieces The speed reduction due to the fragmentation phenomenon can be prevented.

When the assignment of the memory and the recording of the identifier for the memory pool are performed, the memory allocation operation from the memory pool to the thread is completed by releasing the lock of the synchronization variable for the memory pool (S334).

FIG. 4B is a flowchart illustrating a method of controlling a memory synchronization in a multithreading processor according to an exemplary embodiment of the present invention. Referring to FIG. Will be described with reference to Fig. 1 for convenience of explanation.

If the recognition unit 110 recognizes the termination of the thread, the control unit 120 starts to return the memory allocated to the thread to the memory pool. First, the memory unit 120 detects an identifier for the memory pool from the allocated memory (S341 ). The control unit 120 detects an identifier to return the allocated memory to the memory pool to which the memory is allocated (S341), and fixes the synchronization variable for the memory pool (S342). In order to prevent the thread from accessing the memory during the process of returning the memory, the synchronization variable is fixed. If the synchronization variable is fixed, the memory is returned to the memory pool to which the memory is allocated (S343) The operation of returning the allocated memory to the memory pool is completed by releasing the lock of the synchronization variable for the memory pool (S344).

The synchronization process between the thread and the memory pool described above with reference to FIGS. 3 to 5 can be performed simultaneously or in parallel with respect to a plurality of threads by generating a memory pool corresponding to the generated thread, The waiting time required for the memory synchronization can be reduced.

Each block of the accompanying block diagrams and combinations of steps of the flowchart may be performed by computer program instructions. These computer program instructions may be loaded into a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus so that the instructions, which may be executed by a processor of a computer or other programmable data processing apparatus, And means for performing the functions described in each step are created. These computer program instructions may also be stored in a computer usable or computer readable memory capable of directing a computer or other programmable data processing apparatus to implement the functionality in a particular manner so that the computer usable or computer readable memory It is also possible for the instructions stored in the block diagram to produce a manufacturing item containing instruction means for performing the functions described in each block or flowchart of the block diagram. Computer program instructions may also be stored on a computer or other programmable data processing equipment so that a series of operating steps may be performed on a computer or other programmable data processing equipment to create a computer- It is also possible that the instructions that perform the processing equipment provide the steps for executing the functions described in each block of the block diagram and at each step of the flowchart.

In this specification, each block may represent a portion of a module, segment, or code that includes one or more executable instructions for executing the specified logical function (s). It should also be noted that in some alternative implementations, the functions mentioned in the blocks may occur out of order. For example, two blocks shown in succession may actually be executed substantially concurrently, or the blocks may sometimes be performed in reverse order according to the corresponding function.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software module may reside in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, which is capable of reading information from, and writing information to, the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and the storage medium may reside within an application specific integrated circuit (ASIC). The ASIC may reside within the user terminal. Alternatively, the processor and the storage medium may reside as discrete components in a user terminal.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the present invention is not limited to the disclosed exemplary embodiments, but various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the scope of the present invention but to limit the scope of the technical idea of the present invention. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

100: Memory synchronization control device
110:
120:
210: central processing unit
220: Process
230: System memory
240: data area
250: Heap area

Claims (9)

Generating an allocated memory pool from system memory in response to creation of a thread;
Registering an identifier capable of identifying the memory pool;
Generating a synchronization variable for the memory pool and mapping the thread to the synchronization variable;
Allocating memory to the thread from the memory pool;
Returning the allocated memory corresponding to the extinction of the thread to the memory pool;
Releasing system memory for the memory pool; And
And deleting the synchronization variable. ≪ Desc / Clms Page number 19 > The method according to claim 1,
Wherein allocating memory from the memory pool to the thread comprises:
Fixing the synchronization variable for the memory pool;
Allocating a memory of the memory pool to the thread, and writing the identifier to the memory; And
Unlocking the synchronization variable for the memory pool. ≪ Desc / Clms Page number 22 > The method according to claim 1,
Wherein releasing the memory pool further comprises:
Detecting the identifier from the memory;
Fixing the synchronization variable for the memory pool having the identifier;
Returning the memory to the memory pool; and
Unlocking the synchronization variable for the memory pool. ≪ Desc / Clms Page number 22 > The method according to claim 1,
Wherein the threads are a plurality of threads. 24. A computer-readable medium comprising a set of instructions,
Wherein the set of instructions cause the computing device to, when executed by the computing device,
Generating a memory pool allocated from the system memory in response to thread creation,
Registers an identifier capable of identifying the memory pool,
Generating a synchronization variable for the memory pool, mapping the thread to the thread,
Allocating memory from the memory pool to the thread,
Returning the allocated memory to the memory pool in response to the extinction of the thread,
Releasing system memory for the memory pool,
And to delete the synchronization variable. 6. The method of claim 5,
The set of instructions causing the thread to allocate memory from the memory pool,
Fixing the synchronization variable for the memory pool,
Allocating a memory of the memory pool to the thread, writing the identifier to the memory,
The set of instructions causing the memory pool to freeze the synchronization variable for the memory pool. 6. The method of claim 5,
The set of instructions causing the memory pool to be released comprises:
Detecting the identifier from the memory,
Fixing the synchronization variable for the memory pool having the identifier,
Returning the memory to the memory pool,
The set of instructions causing the memory pool to freeze the synchronization variable for the memory pool. 6. The method of claim 5,
The computer-readable medium of claim 1, wherein the threads are plural. A memory pool allocated from the system memory in response to generation of a thread, an identifier for identifying the memory pool, a synchronization variable for the memory pool, mapping the thread to the memory, A controller for allocating a memory to the thread from the pool, returning the memory allocated in response to the termination of the thread to the memory pool, releasing the system memory for the memory pool, and deleting the synchronization variable; And
And a recognition unit for recognizing generation and disappearance of the thread and transmitting the thread to the control unit.

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