KR20140138441A - Shift register and method for driving the same - Google Patents

Abstract

The present invention relates to a shift register capable of reducing power consumption and a driving method thereof, and more particularly, to a shift register having a plurality of stages for sequentially outputting scan pulses using at least one start pulse and a plurality of clock pulses; Each of the stages includes a first carry signal of the front stage provided at least one stage before and a node which controls the voltages of the first node and the second node in response to a second carry signal of a stage after the stage, A control unit; And an output buffer unit for outputting the scan pulse according to a voltage state of the first and second nodes; The node control unit connects the first node provided in the stage to the first node of the subsequent stage provided at least at the second stage and precharges the first node of the stage at the second stage and the subsequent stage .

Description

[0001] SHIFT REGISTER AND METHOD FOR DRIVING THE SAME [0002]

The present invention relates to a shift register capable of reducing power consumption and a driving method thereof.

2. Description of the Related Art In recent years, flat panel displays have been widely used as display devices due to their excellent image quality, light weight, thinness, and low power. Flat panel displays include liquid crystal displays (OLED) and organic light emitting diode (OLED) displays. Most of them are commercially available in TVs, notebooks, MP3 players, mobile phones, and the like.

The flat panel display device includes a display panel for displaying an image, a gate driver for supplying a scan pulse to gate lines of the display panel, a data driver for supplying a video signal (data voltage) to the data lines of the display panel, And a timing controller for controlling the gate driver and the data driver.

1, the gate driver and the data driver include a plurality of stages ST1 to STn for shifting and outputting scan pulses or sampling signals Vout 1 to Vout n according to a control signal provided from a timing controller And a shift register configured. Each stage ST1 to STn of the shift register controls the voltage state of the first node (aka, Q node) and the second node (aka, QB node) to drive an output buffer circuit composed of a pull- And outputs scan pulses or sampling signals Vout 1 to Vout n.

As shown in Fig. 2, each of the stages ST1 to STn has a first period in which the first node is precharged in response to the carry signal provided from the previous stage, A second period during which the first node is bootstrapped in response to the signal, and a third period during which the first node is spontaneously discharged.

In the conventional shift register, after each stage charges the first node and outputs the scan pulse or the sampling signals (Vout 1 to Vout n), the voltage of the first node is naturally discharged, and the power consumption is wasteful .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a shift register capable of reducing the power consumption of a flat panel display device and a driving method thereof.

According to an aspect of the present invention, there is provided a shift register including a plurality of stages for sequentially outputting scan pulses using at least one start pulse and a plurality of clock pulses; Each of the stages includes a first carry signal of the front stage provided at least one stage before and a node which controls the voltages of the first node and the second node in response to a second carry signal of a stage after the stage, A control unit; And an output buffer unit for outputting the scan pulse according to a voltage state of the first and second nodes; The node control unit connects the first node provided in the stage to the first node of the subsequent stage provided at least at the second stage and precharges the first node of the stage at the second stage and the subsequent stage .

Wherein the node control unit charges the first node to a high potential voltage in response to the first carry signal and simultaneously discharges the voltage of the second node to a low potential voltage and in response to the second carry signal, The voltage of the node is charged to the high potential voltage and the voltage of the first node is discharged to the low potential voltage.

The node control unit provided in each of the stages may include a charge sharing switching element that connects the corresponding stage and the first node provided in each of the subsequent stages provided in the at least second stage in response to the charge sharing signal .

Wherein the plurality of clock pulses include first through eighth clock pulses having different phases and are sequentially and repeatedly input to the plurality of stages; th stage and k + 4th stage are connected to each other through the charge sharing switching element.

Wherein the charge sharing signal comprises: a first charge sharing signal for controlling a charge sharing switching element provided in each of nth (n is a natural number) to an (n + 3) th stages; A second charge sharing signal for controlling a charge sharing switching element provided in each of the (n + 4) th to (n + 7) th stages; And the first and second charge sharing signals are alternately outputted.

According to another aspect of the present invention, there is provided a method of driving a shift register including at least one start pulse and a plurality of stages sequentially outputting scan pulses using a plurality of clock pulses, A driving method of a shift register, comprising: a first carry signal of a preceding stage provided at least one stage before and a second carry signal of a stage after at least one stage; ; And outputting the scan pulse according to a voltage state of the first and second nodes; Wherein the step of controlling the voltage of the first node includes connecting the first node provided in the stage to the first node of the subsequent stage provided at least after the second stage, And precharging one node.

Wherein controlling the voltages at the first and second nodes comprises charging the first node to a high potential in response to the first carry signal and simultaneously discharging the voltage at the second node to a low potential voltage ; And discharging the voltage of the first node to the low potential voltage while charging the voltage of the second node to the high potential voltage in response to the second carry signal.

Wherein the step of controlling the voltage of the first node comprises the steps of: connecting the corresponding stage in response to the charge sharing signal to a first node provided in each of the stages, And a control unit.

Further comprising the step of sequentially and repeatedly inputting the first to eighth clock pulses having different phases to the plurality of stages; th stage and k + 4th stage are connected to each other through the charge sharing switching element.

Wherein the charge sharing signal comprises: a first charge sharing signal for controlling a charge sharing switching element provided in each of nth (n is a natural number) to an (n + 3) th stages; A second charge sharing signal for controlling a charge sharing switching element provided in each of the (n + 4) th to (n + 7) th stages; And the first and second charge sharing signals are alternately outputted.

The present invention reduces the power consumption by supplying excess charges charged in the first node (Q node) to each stage in at least the second stage.

1 is a schematic configuration diagram of a shift register.
2 is a drive waveform diagram of the first node.
3 is a configuration diagram of a flat panel display including a shift register according to an embodiment of the present invention.
4 is a configuration diagram of a gate shift register according to an embodiment of the present invention.
5 is a configuration diagram of a gate shift register according to an embodiment of the present invention.
6 is a configuration diagram of the k-th stage shown in Figs. 4 and 5. Fig.
7 is a driving waveform diagram of the gate shift register shown in FIG. 4 and FIG. 5. FIG.
Fig. 8 is a driving waveform diagram of the third and seventh stages ST3 and ST7 shown in Figs. 4 and 5. Fig.

Hereinafter, a shift register according to an embodiment of the present invention and a driving method thereof will be described in detail with reference to the accompanying drawings.

For reference, the present invention relates to a shift register provided in the gate driver 4 or the data driver 6, but a gate shift register will be described below as an example.

3 is a configuration diagram of a flat panel display including a shift register according to an embodiment of the present invention.

The flat panel display device shown in Fig. 3 includes a display panel 2, a gate driver 4, a data driver 6, and a timing controller 8.

The display panel 2 includes a plurality of gate lines GL and a plurality of data lines DL intersecting with each other and a plurality of pixels P are provided at intersections of the display lines GL and DL. Each pixel P displays an image according to a video signal (data voltage) supplied from the data line DL in response to a scan pulse Vout supplied from the gate line GL.

The gate driver 4 is a GIP (gate in panel) type gate driver and is formed in a non-display area of the display panel 2. [ The gate driver 4 includes a gate shift register for supplying a plurality of gate lines GL with a scan pulse Vout in accordance with a plurality of gate control signals GCS provided from the timing controller 8. [ In particular, the present invention reduces the power consumption by supplying excess charges charged in the first node (Q) to at least two stages in each stage of the gate shift register. Such shift registers will be described later in detail with reference to Figs. 4 to 8. Fig.

The data driver 6 converts digital image data RGB input from the timing controller 8 into data voltages using a reference gamma voltage in accordance with a plurality of data control signals DCS provided from the timing controller 8, And supplies the converted data voltage to the plurality of data lines DL. To this end, the data driver 6 includes a data shift register for outputting a sampling signal, a latch for latching image data, and a digital-analog converter.

The timing controller 8 arranges image data (RGB) input from the outside in accordance with the size and resolution of the display panel 2 and supplies the image data to the data driver 6. The timing controller 8 uses a plurality of gates and a plurality of gates and a plurality of gates using external synchronous signals such as a dot clock DCLK, a data enable signal DE, a horizontal synchronous signal Hsync and a vertical synchronous signal Vsync. And supplies the data control signals GCS and DCS to the gate driver 4 and the data driver 6, respectively.

The plurality of gate control signals GCS include a plurality of clock pulses CLK having different phases and a gate start pulse Vst for instructing the gate driver 4 to start driving.

The plurality of clock pulses CLK includes two or more clock pulses CLK having different phases. That is, the clock pulse CLK of the present invention may be a clock pulse CLK of 2-phase, 4-phase, 6-phase, 8-phase or the like. Hereinafter, it is assumed that the clock pulse CLK of the present invention includes 8-phase clock pulses CLK1 to CLK8 (see FIG. 7).

The gate start pulse Vst has a gate high voltage (VGH) state only once at the beginning of each frame. The gate start pulse Vst is output at least one depending on how many clock pulses CLK are several clock pulses CLK. Hereinafter, the gate start pulse Vst of the present invention will be described as including the first and second gate start pulses Vst1 and Vst2.

4 and 5 are block diagrams of a gate shift register according to an embodiment of the present invention. 6 is a configuration diagram of the k-th stage shown in Figs. 4 and 5. Fig. 7 is a driving waveform diagram of the gate shift register shown in FIG. 4 and FIG. 5. FIG.

Referring to FIG. 4, the gate shift register includes first through n-th stages ST1 through STn to sequentially output a plurality of scan pulses Vout 1 through Vout n. The gate shift register sequentially outputs scan pulses Vout 1 to Vout n from the first stage ST1 to the n-th stage STn in response to the first and second gate start pulses Vst1 and Vst2.

Each of the stages ST1 to STn receives one of the first to eighth clock pulses CLK1 to CLK8, and receives different clock pulses CLK. Each of the stages ST1 to STn receives a high potential voltage VDD and a low potential voltage VSS. The high potential voltage VDD is set to a voltage higher than the low potential voltage VSS where the high potential voltage VDD is the gate high voltage VGH and the low potential voltage VSS is the gate low voltage VGL have.

Each stage ST1 to STn has two input terminals and one output terminal, and outputs scan pulses Vout 1 to Vout n through an output terminal. The scan pulses Vout 1 to Vout n are applied to the gate line GL of the display panel 2 and serve as carry signals Carry 1 and Carry 2 transferred to the front stage and the rear stage. The front stage based on k (1 < k < n) stages STk is referred to as "the first stage ST1 to the k- 1 stage (STk-1) ". Stage is referred to as a " k + 1 stage (STk + 1) to an n-th stage STn " Indicate which one.

Each stage ST1 to STn operates in response to the first carry signal Carry1 of the front stage and the second carry signal Carry2 of the rear stage. However, the first and second stages ST1 and ST2 receive the first and second gate start pulses Vst1 and Vst2, respectively, instead of the first carry signal Carry1. A carry signal from a dummy stage (not shown) is input to the n-1 and n-th stages STn-1 and STn instead of the second carry signal Carry2.

On the other hand, as described above, in the present invention, each stage provided in the gate shift register supplies the excess charge charged in the first node (Q) to the stage at least to the second stage, thereby saving power consumption. To this end, the charge-sharing signal CS provided from the timing controller 8 is input to the plurality of stages ST1 to STn. The charge sharing signal CS includes a first charge sharing signal CS for controlling a charge sharing TFT Tcs (see FIG. 6) provided in each of the nth (n is a natural number) to an (n + 3) And a second charge sharing signal CS2 for controlling a charge sharing TFT Tcs provided in each of the +4 th to (n + 7) th stages. The first and second charge sharing signals CS1 and CS2 are alternately outputted as shown in FIG.

A plurality of stages ST1 to STn as described above have the same circuit configuration and operation method, and a k-th stage STk will be described below as an example.

Referring to FIG. 6, the k-th stage STk includes a node control unit 10 and an output buffer unit 12.

The node controller 10 includes a plurality of TFTs (not shown) and at least one capacitor (not shown) for controlling the voltages of the first and second nodes Q and QB in response to the first and second carry signals Carry1 and Carry2 (Not shown). The node controller 10 charges the first node Q to the high potential voltage VDD in response to the first carry signal Carry1 and simultaneously turns the voltage of the second node QB to the low potential voltage VSS Discharge. The node controller 10 responds to the second carry signal Carry2 to charge the voltage of the second node QB to the high potential voltage VDD and at the same time the voltage of the first node Q to the low potential voltage VSS ).

The output buffer unit 12 receives any one of the first to eighth clock pulses CLK1 to CLK8 provided from the timing controller 8, for example, the first clock pulse CLK1. The output buffer unit 12 applies the first clock pulse CLK1 to the output terminal when the voltage of the first node Q is charged to the high potential voltage VDD. When the voltage of the second node QB is charged to the high potential voltage VDD, the output buffer unit 12 discharges the voltage of the output terminal to the low potential voltage VSS. To this end, the output buffer unit 12 includes a pull-up TFT connected to the first node (Q) and a pull-down TFT connected to the second node (QB). The pull-up TFT is turned on or off according to the voltage state of the first node (Q), and applies the first clock pulse (CLK1) to the output terminal at the turn-on time. The pull-down TFT is turned on or off according to the voltage state of the second node QB, and applies the low-potential voltage VSS (VGL) to the output terminal at the turn-on time.

The node controller 10 connects the first node Q provided in the corresponding stage to the first node Q of the subsequent stage provided at least at the second stage, And precharges the first node (Q). To this end, in response to the charge sharing signal CS provided from the timing controller 8, the node control unit 10 transmits the first node Q provided in the stage to the first stage And a charge sharing TFT (Tcs) for connecting to the node (Q). For example, the first node Q of the k-th stage STk is connected to the first node Q of the k + 4 stage STk + 4 through the charge sharing TFT Tcs.

Hereinafter, with reference to FIG. 8, the precharge operation of the node control unit 10 will be described by way of examples of the third and seventh stages (ST3 and ST7).

Fig. 8 is a driving waveform diagram of the third and seventh stages ST3 and ST7 shown in Figs. 4 and 5. Fig.

the third stage ST3 in a1 period charges the first node Q3 to the high potential voltage VDD in response to the first carry signal Carry1 provided from the first stage ST1, QB to a low potential voltage VSS.

Subsequently, in the a2 period, the third stage ST3 is bootstrapped at the first node Q3 as the third clock pulse CLK3 is applied at the gate high voltage (VGH) state.

Subsequently, in a3 period, the third stage ST3 charges the voltage of the second node QB to the high-potential voltage VDD in response to the second carry signal Carry2 provided from the fifth stage ST5 And discharges the voltage of the first node Q3 to the low potential voltage VSS. At this time, as the first charge sharing signal CS1 is applied to the third stage ST3 in the state of the gate high voltage VGH, the charge sharing TFT Tcs of the third stage ST is turned on. Then, the charge charged in the first node Q3 of the third stage ST3 is supplied to the first node Q7 of the seventh stage ST7 through the charge-sharing TFT Tcs. Thus, the first node Q7 of the seventh stage ST7 is precharged.

On the other hand, from the viewpoint of the seventh stage ST7, the b1 period corresponds to the a3 period, and the first node Q7 of the seventh stage ST7 is precharged due to the voltage supplied from the third stage ST3. do.

Subsequently, in the b2 period, the seventh stage ST7 charges the first node Q7 to the high potential voltage VDD in response to the first carry signal Carry1 provided from the fifth stage ST5, And discharges the voltage of the node QB to the low potential voltage VSS.

Then, in the b3 period, the seventh stage ST7 is bootstrapped at the first node Q7 as the seventh clock pulse CLK7 is applied at the gate high voltage (VGH) state.

Subsequently, in the period b4, the seventh stage ST7 charges the voltage of the second node QB to the high-potential voltage VDD in response to the second carry signal Carry2 provided from the ninth stage ST9 And discharges the voltage of the first node (Q7) to the low potential voltage (VSS). At this time, as the second charge sharing signal CS2 is applied in the gate high voltage (VGH) state in the seventh stage ST3, the charge sharing TFT Tcs of the seventh stage ST7 is turned on. Then, the charge charged to the first node Q7 of the seventh stage ST7 is supplied to the first node Q11 of the eleventh stage ST11 through the charge-sharing TFT Tcs.

As described above, the present invention reduces the power consumption by supplying the surplus charge charged in the first node Q to each stage at least to the second stage.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

Carry1: first carry signal Carry2: second carry signal
Tcs: charge-sharing TFT CS: charge-sharing signal

Claims (10)

A plurality of stages for sequentially outputting scan pulses using at least one start pulse and a plurality of clock pulses;
Each of the stages
A node controller for controlling a voltage of the first node and a voltage of the second node in response to a first carry signal of the front stage provided at least one stage before and a second carry signal of the stage after the stage at least one stage;
And an output buffer unit for outputting the scan pulse according to a voltage state of the first and second nodes;
The node control unit connects the first node provided in the stage to the first node of the subsequent stage provided at least at the second stage and precharges the first node of the stage at the second stage and the subsequent stage Features a shift register. The method according to claim 1,
The node control unit
The first node is charged with a high potential voltage in response to the first carry signal and the voltage of the second node is discharged to a low potential voltage,
And charges the voltage of the second node to the high potential voltage in response to the second carry signal, and discharges the voltage of the first node to the low potential voltage. The method of claim 2,
The node control unit provided in each stage
And a charge sharing switching element for connecting the corresponding stage in response to the charge sharing signal to a first node provided in each of the subsequent stages provided in the at least second stage. The method of claim 3,
Wherein the plurality of clock pulses include first through eighth clock pulses having different phases and are sequentially and repeatedly input to the plurality of stages;
th stage and the (k + 4) th stage are connected to each other through the charge sharing switching element. The method of claim 4,
The charge sharing signal
A first charge sharing signal for controlling a charge sharing switching element provided in each of nth (n is a natural number) to (n + 3) stages;
A second charge sharing signal for controlling a charge sharing switching element provided in each of the (n + 4) th to (n + 7) th stages;
Wherein the first and second charge sharing signals are alternately output to each other. A driving method of a shift register having at least one start pulse and a plurality of stages for sequentially outputting scan pulses using a plurality of clock pulses,
Controlling a voltage of a first node and a second node in response to a first carry signal of a front stage provided at least one stage before and a second carry signal of a stage after the stage at least one stage;
And outputting the scan pulse according to a voltage state of the first and second nodes;
Wherein controlling the voltage of the first node comprises:
And connecting the first node provided in the stage to the first node of the subsequent stage provided at least at the second stage and precharging the first node of the stage at the second stage and the subsequent stages And a driving method of the shift register. The method of claim 6,
Wherein controlling the voltages at the first and second nodes comprises:
Charging the first node to a high potential in response to the first carry signal and discharging the voltage of the second node to a low potential;
And discharging the voltage of the first node to the low potential voltage while charging the voltage of the second node to the high potential voltage in response to the second carry signal. Way. The method of claim 7,
Wherein controlling the voltage of the first node comprises:
Wherein the charge sharing switching element includes a step of connecting between the corresponding stage and a first node provided in each of the stages provided at the at least second stage in response to the charge sharing signal, Way. The method of claim 8,
Further comprising the step of sequentially and repeatedly inputting the first to eighth clock pulses having different phases to the plurality of stages;
th stage and the (k + 4) th stage are connected to each other through the charge sharing switching element. The method of claim 9,
The charge sharing signal
A first charge sharing signal for controlling a charge sharing switching element provided in each of nth (n is a natural number) to (n + 3) stages;
A second charge sharing signal for controlling a charge sharing switching element provided in each of the (n + 4) th to (n + 7) th stages;
Wherein the first and second charge sharing signals are alternately output to each other.

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