KR20130050077A - Stacked Packages and Methods for Manufacturing the Same - Google Patents

Abstract

The stack package is stacked on the first package substrate having the first semiconductor chip, the first package substrate, and electrically connects the second package substrate having the second semiconductor chip, the first package substrate, and the second package substrate. A conductive member, a partition structure provided on an upper surface of an outer portion of the second package substrate, and a molding member covering a second semiconductor chip on an upper surface of the second package substrate, the forming region defined by the partition structure. By forming a barrier rib structure on the outer portion of the second package substrate to prevent warpage, and to form a molding member using a silicon encapsulant that is hardened at low temperature, thermal deformation may be minimized.

Description

STACKED PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE}

The present invention relates to a stack package and a method of manufacturing the same. More specifically, the present invention relates to a stack package in which a plurality of semiconductor packages are stacked and a method of manufacturing the same.

In order to implement a high density stacked semiconductor package, a package on package (POP) technology is being developed in which another package is stacked on a package in which a plurality of semiconductor chips are stacked.

The POP type semiconductor package may have a stack package structure in which a second semiconductor package is stacked on a first semiconductor package, and each of the semiconductor packages may include semiconductor chips mounted on each semiconductor substrate.

However, the semiconductor packages may have different thermal and mechanical properties, and stress may be generated by stacking the semiconductor packages having different properties. The stress may cause problems such as poor contact of the stack package, thereby lowering the reliability of the final product.

One object of the present invention is to provide a stack package having excellent thermal and mechanical properties.

Another object of the present invention is to provide a method for producing a stack package having excellent thermal and mechanical properties.

According to at least one example embodiment of the inventive concepts, a stack package includes a first package substrate having a first semiconductor chip, and a second stacked structure on the first package substrate. A package substrate, a conductive member electrically connecting the first package substrate and the second package substrate, a partition structure provided on an upper surface of an outer portion of the second package substrate, and the second semiconductor on an upper surface of the second package substrate. And a molding member covering the chip, the forming member being defined by the barrier rib structure.

In example embodiments, the barrier rib structure may have a higher modulus and a lower coefficient of thermal expansion than the second package substrate.

In example embodiments, the molding member may include a silicon encapsulant.

In example embodiments, the stack package may be disposed on the second conductive pads spaced apart from the second semiconductor chip and disposed on an upper surface of the second package substrate, and on an upper surface of the second package substrate and a lower portion of the barrier rib structure. The display device may further include an insulation pattern partially covering the second conductive pads.

In example embodiments, the stack package may further include a conductive via penetrating the barrier rib structure and the insulating pattern to contact the second conductive pad.

In example embodiments, the stack package may further include a semiconductor package stacked on the second package substrate through the conductive via.

In example embodiments, the stack package may further include first conductive pads spaced apart from the first semiconductor chip on an upper surface of the first package substrate, wherein the first semiconductor chip is formed through the conductive wire. It may be electrically connected to the first conductive pad.

In example embodiments, the first semiconductor chip may be bonded to the first package substrate through conductive bumps.

According to a method of manufacturing a stack package according to embodiments of the present invention for achieving another object of the present invention, to form a first package substrate including a first semiconductor chip. A second package substrate including a second semiconductor chip is formed. A barrier rib structure surrounding the second semiconductor chip is formed at an outer portion of the second package substrate. A molding member is formed on the second package substrate to cover the second semiconductor chip and to be defined by the barrier rib structure. The first package substrate and the second package substrate are stacked.

In example embodiments, the barrier rib structure may be formed using a material having a higher modulus and a lower coefficient of thermal expansion than the second package substrate. In addition, the molding member may be formed using a silicon encapsulant.

According to embodiments of the present invention, a silicon encapsulant is used instead of an epoxy molding compound (EMC) which is commonly used as a molding member of a semiconductor package. In the case of using the silicon encapsulant, a molding process may be performed even at low temperature, thereby minimizing thermal deformation of the semiconductor package. In addition, by forming a barrier rib structure at an edge portion of the semiconductor package in which warpage due to thermal deformation occurs frequently, the warpage may be prevented and the flow of the silicon encapsulant may be prevented.

1A-1C are cross-sectional views illustrating a stack package in accordance with example embodiments.
2 is a cross-sectional view illustrating a stack package according to other exemplary embodiments.
3 to 9 are cross-sectional views illustrating a method of manufacturing a stack package according to example embodiments.
10 to 12 are cross-sectional views illustrating a method of manufacturing a stack package according to example embodiments.
13 to 15 are cross-sectional views illustrating a method of manufacturing a stack package according to other exemplary embodiments.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the drawings of the present invention, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

In the present invention, the terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In the present invention, it is to be understood that each layer (film), region, electrode, pattern or structure may be formed on, over, or under the object, substrate, layer, Means that each layer (film), region, electrode, pattern or structure is directly formed or positioned below a substrate, each layer (film), region, or pattern, , Other regions, other electrodes, other patterns, or other structures may additionally be formed on the object or substrate.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, But should not be construed as limited to the embodiments set forth in the claims.

That is, the present invention may be modified in various ways and may have various forms. Specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Stack package

1A-1C are cross-sectional views illustrating a stack package in accordance with example embodiments.

Referring to FIG. 1A, a stack package 100 according to example embodiments has a structure in which a first semiconductor package 110 and a second semiconductor package 150 are stacked.

The first semiconductor package 110 includes a first package substrate 112, a first semiconductor chip 114, a first molding member 118, and first and second pads 124 and 126. The first semiconductor package 110 may be a package disposed under the stack package 100, and may include a logic element for controlling a memory device of the semiconductor package disposed above.

The first package substrate 112 includes a first surface 112a corresponding to the top surface and a second surface 112b corresponding to the bottom surface and opposite to the first surface 110a. In example embodiments, the first package substrate 112 may be a printed circuit board (PCB). In addition, the first package substrate 112 may be a multilayer circuit board having various wirings, via holes, and the like therein.

The first semiconductor chip 114 may be disposed in the center of the upper portion of the first package substrate 112. In example embodiments, the first semiconductor chip 114 may include an LSI logic chip. Although not shown, a plurality of first semiconductor chips 114 may be sequentially stacked.

The first semiconductor chip 114 may be electrically connected to the first package substrate 112 through the conductive bumps 116. In other words, the conductive bumps 116 are disposed between the first semiconductor chip 114 and the first package substrate 112. Conductive structures (not shown), such as an electrode, may be provided on the first surface 112a of the first package substrate 112 in contact with the conductive bumps 116.

The first molding member 118 is formed on the first surface 112a of the first package substrate 112 to cover the first semiconductor chip 118 and the conductive bumps 116. The first molding member 118 may include an epoxy molding compound (EMC). The first molding member 118 is formed at the center of the first package substrate 112 to cover the first semiconductor chip 114, and the first package member 112 of the first package substrate 112 having the first pads 124 formed thereon. It may not extend to the side.

As illustrated in FIG. 1A, the first molding member 118 may have a flat top surface, and the top surface of the first semiconductor chip 114 may be exposed through the top surface of the first molding member 118. Alternatively, the first molding member 118 may be formed to completely cover the top surface of the first semiconductor chip 114.

A plurality of first pads 124 may be provided on the top surface 112a of the first package substrate 112. The first pads 124 may be disposed on a side portion or an outer portion of the first package substrate 112 to surround the first semiconductor chip 114. Electrical signals, for example, fast signals such as a power signal, a data signal, a clock signal, and the like may be transmitted through the first pads 124.

Second pads 126 may be provided on the second surface 112b of the first package substrate 112, and first conductive balls 130 may be provided to contact the second pads 126, respectively. For example, the first conductive balls 130 may be solder balls. In example embodiments, the first conductive balls 130 may be provided as external connection terminals.

The first semiconductor package 110 described with reference to FIG. 1A is exemplary and may be variously changed.

For example, referring to FIG. 1B, the first semiconductor chip 114 may be electrically connected to the first package substrate 112 through the conductive wire 130 and the pad 132 instead of the conductive bumps 116. have.

In addition, referring to FIG. 1C, the first molding member 118a may expose a region where the second conductive balls 140 and the first pads 124 are disposed, and may expose the first surface of the first package substrate 112. 112a) may be covered as a whole.

Hereinafter, the case where the first semiconductor package 110 has the structure of FIG. 1A will be described as an example.

The second semiconductor package 150 is stacked on the first semiconductor package 110. For example, the first and second semiconductor packages 110 and 150 may be electrically connected to each other through the second conductive balls 140.

The second semiconductor package 150 may include a second package substrate 160, a second semiconductor chip 164, a second molding member 180, a partition structure 170, and third and fourth pads 162 and 168. And conductive members such as conductive wire 166.

The second package substrate 160 includes a third surface 160a corresponding to the top surface and a fourth surface 160b corresponding to the bottom surface and facing the third surface 160a. In example embodiments, the second package substrate 160 may be a multilayer circuit board having various wirings, via holes, and the like therein.

Third pads 162 are provided on the fourth surface 160b of the second package substrate 160. The third and first pads 162 and 124 are electrically connected to each other via the second conductive balls 140. That is, fast signals such as electrical signals, for example, power signals, data signals, clock signals, and the like may be transmitted through the third pads 162.

The second conductive balls 140 may be formed of solder balls, and are disposed on the side portions or the outer portions of the first and second package substrates 112 and 160.

The second semiconductor chip 164 is provided on the third surface 160a of the center portion of the second package substrate 160. In some embodiments, the plurality of second semiconductor chips 164 may be sequentially stacked. The second semiconductor chip 164 may include, for example, a plurality of memory elements. The memory device may include a volatile memory device or a nonvolatile memory device. Examples of the volatile memory device include DRAM, SRAM, and the like, and examples of the nonvolatile memory device include EPROM, EEPROM, and Flash EEPROM. A plurality of bonding pads (not shown) may be provided on the second semiconductor chip 164.

Four pads 168 are provided on the third surface 160a of the second package substrate 160. The fourth pads 168 may be spaced apart from the second semiconductor chip 164 and arranged in a shape surrounding the second semiconductor chip 164.

The bonding pad and the fourth pad of the second semiconductor chip 164 may be electrically connected to each other through the conductive wire 166. The conductive wire 166 may include a metal material such as gold and aluminum.

The partition structure 170 is provided on the third surface 160a of the outer portion of the second semiconductor chip 164. That is, the barrier rib structure 170 may have a shape surrounding the outer periphery of the second semiconductor chip 164.

According to example embodiments, the barrier rib structure 170 may have a high modulus to prevent warpage of an outer portion of the second semiconductor package 150 or the second package substrate 160 where thermal stress continues to occur frequently. It may comprise a polymeric or metallic material having a modulus and having a low coefficient of thermal expansion (CTE). That is, the barrier rib structure 170 may include a material having a higher modulus and a lower CTE than the first and / or second package substrates 112 and 160.

According to exemplary embodiments, a separate adhesive member (not shown) is provided on the third surface 160a of the outer portion of the second package substrate 160, and the partition structure 170 is formed through the adhesive member. 2 may be attached on the package substrate 160.

As the barrier rib structure 170 is formed, an opening 175 is defined by the barrier rib structure 170 and exposes the third surface 160a of the second package substrate 160 and the second semiconductor chip 164. Can be defined.

The third surface of the second package substrate 160 such that the second molding member 180 filling the inside of the opening 175 covers the second semiconductor chip 164, the conductive wire 166, and the fourth pad 168. 160a).

In example embodiments, the second molding member 180 may include a silicon encapsulant. The silicone encapsulant has a flowability and is easily cured at a low temperature as compared to EMC used as a conventional molding member. Therefore, the bending stress of the package substrates 160 and 112 may be minimized by reducing the thermal stress generated during the molding process performed at a high temperature. On the other hand, since the partition structure 170 is provided at the outer portion of the second package substrate 160, the silicon encapsulant may be prevented from flowing or spreading to the side, and due to thermal stress occurring at the outer portion The warpage phenomenon can be prevented. As a result, the reliability of the stack package may be prevented due to poor contact of the second conductive balls 140 generated by the warpage phenomenon.

2 is a cross-sectional view illustrating a stack package according to other exemplary embodiments. Detailed description of components and / or members substantially the same as or similar to the stack package shown in FIG. 1A will be omitted.

Referring to FIG. 2, an insulating pattern 172 may be provided under the partition structure 174. The insulating pattern 172 may include a solder resist material such as an insulating polymer material. A separate adhesive member may be disposed between the barrier rib structure 174 and the insulating pattern 172.

The fourth pad 168a is provided on the third surface 160a of the second package substrate 160 and may be partially covered by the insulating pattern 172. In example embodiments, the plurality of fourth pads 168a may be spaced apart from the second semiconductor chip 164 to surround the second semiconductor chip 164. The fourth pad 168a may be electrically connected to the bonding pad of the second semiconductor chip 164 by the conductive wire 166a.

In an embodiment, a conductive structure (not shown), such as wires, contacts, or vias, may be provided in the barrier rib structure 174 and the insulating pattern 172. For example, a via (not shown) that penetrates the barrier rib structure 174 and the insulating pattern 172 to contact the fourth pad 168a may be provided. In this case, an additional semiconductor package may be further stacked on the second semiconductor package 150 using the via.

Manufacturing method of stack package

3 to 9 are cross-sectional views illustrating a method of manufacturing a stack package according to example embodiments. Specifically, cross-sectional views illustrating a method of manufacturing the stack package illustrated in FIG. 1A are illustrated.

Referring to FIG. 3, a first package substrate 112 for mounting the first semiconductor chip 114 is prepared. The first package substrate 112 may be a single layer or multilayer printed circuit board having various wirings, via holes, or the like therein.

First pads 124 are formed on the first surface 112a of the first package substrate 112. In addition, second pads 126 are formed on the second surface 112b of the first package substrate 112.

First conductive balls 130 are formed on the surface of the second pads 126. The first conductive balls 130 may be formed using solder. A first temporary adhesive 142 is applied on the second surface 112b of the first package substrate 112 to cover the first conductive balls 130 and to protect the first conductive balls 130. The carrier substrate 144 may be attached onto the first temporary adhesive 142.

A plurality of conductive bumps 116 are disposed on the first surface 112a of the central portion of the first package substrate 112. The conductive bumps 116 may be disposed to be surrounded by the first pads 124.

The first semiconductor chip 114 is disposed on the conductive bumps 116. Thereafter, the first semiconductor chip 114 and the first package substrate 112 may be bonded using the conductive bumps 116 through the reflow process. Accordingly, the first semiconductor chip 114 and the first package substrate 112 may be electrically connected to each other.

Referring to FIG. 4, the first sealing member 118 covering the first semiconductor chip 114 is formed on the first surface 112a of the first package substrate 112. According to exemplary embodiments, the first sealing member 118 may be formed using EMC. The first sealing member 118 may be formed to expose the top surface of the first semiconductor chip 114. Alternatively, the first sealing member 118 may be formed to completely cover the top surface of the first semiconductor chip 114. By forming the first sealing member 118, the first semiconductor chip 114 may be protected from the outside.

The first semiconductor package 110 may be manufactured by performing the above-described processes.

Referring to FIG. 5, a second package substrate 160 for mounting the second semiconductor chip 164 is provided. The second package substrate 160 may be a single layer or multilayer printed circuit board having various wirings, via holes, or the like therein.

Fourth pads 168 are formed on the third surface 160a of the second package substrate 160. In addition, third pads 162 are formed on the fourth surface 160b of the second package substrate 160.

Second conductive balls 140 are formed on the surface of the third pads 162. The second conductive balls 140 may be formed using solder. A second temporary adhesive 146 covering the second conductive balls 140 on the fourth surface 160b of the second package substrate 160, and a second to protect the second conductive balls 140. The carrier substrate 148 may be attached onto the second temporary adhesive 146.

The second semiconductor chip 164 is disposed on the third surface 160a of the center portion of the second package substrate 160. The second semiconductor chip 164 may be formed using a second package substrate (not shown) using an adhesive layer (not shown). 160 may be attached. In example embodiments, the plurality of second semiconductor chips 164 may be stacked and disposed, and bonding pads (not shown) may be formed on the second semiconductor chip 164. The second semiconductor chip 164 may have a shape surrounded by the fourth pads 168.

Referring to FIG. 6, the bonding pads and the fourth pads 168 formed on the second semiconductor chip 164 may be electrically connected using the conductive wire 166.

Next, the partition wall structure 170 is formed on the third surface 160a of the outer portion of the first package substrate 160. In example embodiments, the barrier rib structure 170 may be formed using a metal or polymer material having higher modulus and lower CTE than the first and / or second package substrates 112 and 160. The barrier rib structure 170 forms a separate adhesive member (not shown) on the third surface 160a of the outer portion of the second package substrate 160 and is formed on the second package substrate 160 through the adhesive member. Can be attached. As the barrier rib structure 170 is formed, an opening 175 is defined by the barrier rib structure 170 and exposes the third surface 160a of the second package substrate 160 and the second semiconductor chip 164. Can be defined.

Referring to FIG. 7, the second sealing member 180 filling the opening 175 on the third surface 160a of the second package substrate 160 and covering the second semiconductor chip 164 and the conductive wire 166. To form. In example embodiments, the second molding member 180 may be formed using a silicon encapsulant. Since the silicon encapsulant is easily cured even at a low temperature, thermal deformation of the second package substrate 160 and the second semiconductor chip 164 may be prevented by performing the molding process at a low temperature.

The second semiconductor package 150 may be manufactured by performing the above-described processes.

Referring to FIG. 8, by removing the second temporary adhesive 146 and the second carrier substrate 148 attached to the fourth surface 160b of the second package substrate 160, the second conductive balls 140 may be removed. Expose Thereafter, the second semiconductor package 150 is disposed on the first semiconductor package 110 so that the second conductive balls 140 face the first pads 124, respectively.

Referring to FIG. 9, the second conductive balls 140 are bonded to the first pads 124 by performing a reflow process on the second conductive balls 140. Therefore, the first pads 124 of the first semiconductor package 110 and the third pads 162 of the second semiconductor package 150 are electrically connected to each other. Thereafter, the first temporary adhesive 142 and the first carrier substrate 144 attached on the second surface 112b of the first package substrate 112 may be removed to expose the first conductive balls 130. have. Accordingly, the stack package 100 in which the first and second semiconductor packages 110 and 150 are stacked may be manufactured.

Meanwhile, in the process of manufacturing the first semiconductor package 110, pads 132 are formed on the first surface 112a of the first package substrate 112 instead of the conductive bumps 116 and the conductive wire 130 is formed. The first semiconductor package 110 as shown in FIG. 1B may be manufactured by electrically connecting the bonding pads and the conductive pads 132 provided on the first semiconductor chip 114 to each other.

Thereafter, the stack package illustrated in FIG. 1B may be manufactured by performing processes substantially the same as or similar to those described with reference to FIGS. 5 to 9.

10 to 12 are cross-sectional views illustrating a method of manufacturing a stack package according to example embodiments. Specifically, cross-sectional views illustrating a method of manufacturing the stack package shown in FIG. 1C are illustrated.

Referring to FIG. 10, the processes substantially the same as or similar to those described with reference to FIG. 3 are performed. Specifically, the conductive bump 116 and the first semiconductor on the first surface 112a of the first package substrate 112 provided with the first and second pads 124, 1246 and the first conductive balls 130. The chip 114 is disposed and the first semiconductor chip 114 and the first package substrate 112 are bonded through a reflow process.

Referring to FIG. 11, a preliminary first molding member 119 is formed on the first surface 112a of the first package substrate 112 to cover the first semiconductor chip 114. In example embodiments, the preliminary first molding member 119 may be formed to expose the top surface of the first semiconductor chip 114, or may completely fill the first semiconductor chip 114.

Referring to FIG. 12, the first molding member 118a is formed by removing a portion of the preliminary first molding member 119 to form holes 120 exposing the top surface of the first pad 124. do. The holes 120 may be formed through a laser irradiation process.

Subsequently, the stack package illustrated in FIG. 1C may be manufactured by performing processes substantially the same as or similar to those described with reference to FIGS. 5 to 9. In this case, the second conductive balls 140 may be bonded to the first pads 124 while filling the holes 120.

13 to 15 are cross-sectional views illustrating a method of manufacturing a stack package according to other exemplary embodiments. Specifically, cross-sectional views illustrating a method of manufacturing the stack package shown in FIG. 2.

First, the first semiconductor package 110 is manufactured by performing processes substantially the same as or similar to those described with reference to FIGS. 3 and 4.

Referring to FIG. 13, a process substantially the same as or similar to those described with reference to FIG. 5 is performed. Specifically, the second semiconductor chip 164 is disposed on the third surface 160a of the center of the second package substrate 160 on which the third and fourth pads 162 and 168a and the second conductive balls 140 are formed. It adheres using an adhesive layer (not shown) etc.

However, the fourth pad 168a illustrated in FIG. 13 may be disposed closer to the outer portion of the second package substrate 160 than the fourth pad 168 illustrated in FIG. 5.

Referring to FIG. 14, an insulating pattern 172 partially covering the fourth pad 168a is formed on the third surface 160a of the outer portion of the second package substrate 160. The insulating pattern 172 may be formed using a solder resist material such as an insulating polymer material. In example embodiments, the insulating pattern 172 may have a shape surrounding the second semiconductor chip 164.

Referring to FIG. 14, the portion of the fourth pad 168a exposed by the insulating pattern 172 and the bonding pad (not shown) on the second semiconductor chip 164 may be electrically connected using the conductive wire 166a. Connect

The partition structure 174 is formed on the insulating pattern 172. The partition structure 174 may be formed using a metal or polymer material having a higher modulus and a lower CTE than the first and / or second package substrates 112 and 160. The partition structure 174 may form a separate adhesive member (not shown) on the insulating pattern 172 and may be attached to the insulating pattern 172 through the adhesive member. As the barrier rib structure 174 is formed, the barrier rib structure 174 and the insulating pattern 172 are defined to expose the third surface 160a and the second semiconductor chip 164 of the second package substrate 160. The opening 175a may be defined.

After forming the barrier rib structure 174, the second sealing member filling the opening 175a on the third surface 160a of the second package substrate 160 and covering the second semiconductor chip 164 and the conductive wire 166a. Form 180. In example embodiments, the second molding member 180 may be formed using a silicon encapsulant. Accordingly, the second semiconductor package 150 may be manufactured according to example embodiments.

Subsequently, a stack package in which the first and second semiconductor packages 110 and 150 as shown in FIG. 2 are stacked may be manufactured by performing a process substantially the same as or similar to those described with reference to FIGS. 8 and 9. Can be.

In an embodiment, a conductive structure (not shown) such as wires, contacts, and vias may be further formed in the barrier rib structure 174 and the insulating pattern 172. For example, a via (not shown) that penetrates the barrier rib structure 174 and the insulating pattern 172 to contact the fourth pad 168a may be formed. In this case, an additional semiconductor package may be further stacked on the second semiconductor package 150 using the via.

According to embodiments of the present invention, it is possible to obtain a highly reliable stack package with reduced defects such as warpage and poor contact. The stack package may be utilized to provide a highly integrated semiconductor package provided in a mobile system, a communication system, a personal computer, a large computer, and the like.

Although described with reference to the preferred embodiments of the present invention as described above, those skilled in the art that various modifications and changes within the scope of the present invention without departing from the spirit and scope of the invention described in the claims It will be appreciated that it can be changed.

100: stack package 110: first semiconductor package
112: first package substrate 112a: first surface
112b: second surface 114: first semiconductor chip
116: conductive bumps 118, 118a: first molding member
119: preliminary first molding member 124: first pad
126: second pad 130: first conductive balls
130: conductive wire 132: pad
140: second conductive balls 142: first temporary adhesive
144: first carrier substrate 146: second temporary adhesive
148: second carrier substrate 150: second semiconductor package
160: second package substrate 160a: third surface
160b: fourth side 162: third pad
164: second semiconductor chip 166, 166a: conductive wire
168, 168a: fourth pad 170, 174: partition structure
172: insulation pattern 175, 175a: opening
180: second molding member

Claims (10)

A first package substrate having a first semiconductor chip;
A second package substrate stacked on the first package substrate and having a second semiconductor chip;
A conductive member electrically connecting the first package substrate and the second package substrate;
A partition structure provided on an upper surface of an outer portion of the second package substrate; And
And a molding member covering the second semiconductor chip on an upper surface of the second package substrate, the molding member defining a region formed by the barrier rib structure. The stack package of claim 1, wherein the partition structure has a higher modulus and a lower coefficient of thermal expansion than the second package substrate. The stack package of claim 1, wherein the molding member comprises a silicon encapsulant. The method of claim 1,
Second conductive pads spaced apart from the second semiconductor chip and disposed on an upper surface of the second package substrate; And
The stack package further comprising an insulating pattern disposed on an upper surface of the second package substrate and a lower portion of the barrier rib structure and partially covering the second conductive pads. The stack package of claim 4, further comprising a conductive via penetrating the partition structure and the insulating pattern to contact the second conductive pad. The stack package of claim 5, further comprising a semiconductor package stacked on the second package substrate via the conductive via. The semiconductor device of claim 1, further comprising: first conductive pads spaced apart from the first semiconductor chip on an upper surface of the first package substrate.
And the first semiconductor chip is electrically connected to the first conductive pad through a conductive wire. The stack package of claim 1, wherein the first semiconductor chip is bonded to the first package substrate via conductive bumps. Forming a first package substrate comprising a first semiconductor chip;
Forming a second package substrate including a second semiconductor chip;
Forming a barrier rib structure surrounding the second semiconductor chip at an outer portion of the second package substrate;
Forming a molding member covering the second semiconductor chip on the second package substrate and defined by the barrier rib structure; And
Stacking the first package substrate and the second package substrate. The method of claim 9, wherein the barrier rib structure is formed using a material having a higher modulus and a lower coefficient of thermal expansion than the second package substrate.
The molding member is a manufacturing method of a stack package, characterized in that formed using a silicon encapsulant.

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