KR20130020067A - Display device and method of fabricating the same - Google Patents

Abstract

The display device of the present invention and a method of manufacturing the same have a dual link structure for a narrow bezel, and by forming a gate layer as a double layer including a conductive film that does not react to dry etching. A first substrate for preventing damage to the gate wiring by dry etching when forming the link portion contact hole, the first substrate divided into a pixel portion and a driver; A thin film transistor formed on the pixel portion of the first substrate; First link wirings formed on a driving unit of the first substrate and a gate line extending from the pixel unit; A second link wiring formed in a state where a gate insulating film is interposed on a first substrate on which the gate line and the first link wiring are formed; A protective film formed on the first substrate on which the second link wiring is formed; And a second substrate bonded to the first substrate, wherein the first link wiring and the gate line have a double layer or more structure in which a conductive film that does not respond to dry etching is formed on an upper layer.

Description

DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a method of manufacturing the same, and more particularly, to a display device using a dual link structure and a method of manufacturing the same to implement a narrow bezel.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as liquid crystal display (LCD), organic light emitting display (OLED), and plasma display panel (PDP) is increasing.

Such a display device is used for various purposes in an industrial field such as a computer or a mobile phone such as a notebook in a home appliance field such as a television or a video.

Hereinafter, the display device will be described in detail with reference to the accompanying drawings.

1 is a plan view schematically illustrating a general display device.

FIG. 2 is a plan view showing an enlarged portion of the display device shown in FIG. 1 and shows an enlarged portion E. FIG.

Referring to the drawings, some of the aforementioned display devices 10, for example, a liquid crystal display or an organic light emitting display device, may include a pixel unit 20 and a plurality of sub pixels (not shown) arranged in a matrix form. It consists of a driver for driving the pixel.

The driver includes a timing driver (not shown), a data driver 30, and the like. In this case, the data driver 30 is formed on a panel of the display device 10, and the timing driver is formed on a flexible circuit board (not shown) connected to the panel.

For reference, reference numeral 18 denotes a common line.

In the conventional display device 10 configured as described above, in order to apply a gate signal to each gate line (not shown) of a plurality of subpixels, as many link wires 26 as the corresponding gate lines are required. As a result, in the general display device 10, as the resolution increases, the link wiring 26 increases by the required number of gate lines, and the bezel width W of the display device 10 increases. A way to do this will have to be sought.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device and a method of manufacturing the same, which implement a narrow bezel by applying a dual link structure.

Another object of the present invention is to provide a display device and a method of manufacturing the same to prevent damage to the gate wiring by dry etching when forming a link contact hole.

Other objects and features of the present invention will be described in the configuration and claims of the invention which will be described later.

In order to achieve the above object, the display device of the present invention comprises a first substrate divided into a pixel portion and a driver; A thin film transistor formed on the pixel portion of the first substrate; First link wirings formed on a driving unit of the first substrate and a gate line extending from the pixel unit; A second link wiring formed in a state where a gate insulating film is interposed on a first substrate on which the gate line and the first link wiring are formed; A protective film formed on the first substrate on which the second link wiring is formed; And a second substrate bonded to the first substrate, wherein the first link wiring and the gate line have a double layer or more structure in which a conductive film that does not respond to dry etching is formed on an upper layer.

In this case, the method may further include a first contact hole and a third contact hole exposing the surfaces of the first link wire and the gate line, and a second contact hole exposing side surfaces of the second link wire, respectively.

In this case, a first connection electrode electrically connected to the first link wire and the gate line through the first contact hole and the third contact hole, respectively, and the second link through the second contact hole and the third contact hole, respectively. And a second connection electrode electrically connected to the wiring and the gate line.

The first link wiring and the second link wiring are alternately formed according to the order of the gate lines, the first link wiring is formed in the gate wiring layer, and the second link wiring is formed in the data wiring layer and the first neighboring first. The distance between the second link wires is reduced.

In this case, an odd-numbered gate line may be connected to the first link line, and an even-numbered gate line may be connected to the second link line.

The conductive film that does not respond to the dry etching is characterized in that it comprises ITO, aluminum-neodymium.

The second link wire may be in side contact with the second connection electrode, and the first link wire and the gate line may be in surface contact with the first connection electrode.

The gate line may include an upper gate line formed of a conductive film that does not respond to the dry etching, and a lower gate line formed of a low resistance conductive film.

The first link wiring may include an upper first link wiring made of a conductive film that does not respond to the dry etching, and a lower first link wiring made of a low resistance conductive film.

The upper first link line and the upper gate line may serve as an etch stop layer to prevent damage to the first link line and the gate line due to the dry etching.

A method of manufacturing a display device of the present invention includes the steps of providing a first substrate and a second substrate divided into a pixel portion and a driver; Forming a thin film transistor in a pixel portion of the first substrate; Forming a first link line and a gate line extending from the pixel portion in the driving portion of the first substrate; Forming a second link interconnection on a first substrate on which the gate line and the first link interconnection are formed; Forming a protective film on the first substrate on which the second link wiring is formed; And bonding the first substrate and the second substrate, wherein the first link wiring and the gate line are formed to have a structure in which a conductive film that does not respond to dry etching has a structure of two or more layers formed on an upper layer. .

In this case, the passivation layer and the gate insulating layer may be dry-etched to form first contact holes and third contact holes exposing surfaces of the first link wires and the gate lines, respectively, and to expose side surfaces of the second link wires. And forming a second contact hole.

In this case, a first connection electrode electrically connected to the first link wire and the gate line is formed through the first contact hole and the third contact hole, respectively, and the second contact hole and the third contact hole are respectively formed. And forming a second connection electrode electrically connected to the second link wire and the gate line.

The first link wiring and the second link wiring are alternately formed according to the order of the gate lines, the first link wiring is formed in the gate wiring layer, and the second link wiring is formed in the data wiring layer and the first neighboring first. The distance between the second link wires is reduced.

The conductive film that does not respond to the dry etching is characterized in that it comprises ITO, aluminum-neodymium.

As described above, the display device and the manufacturing method thereof according to the present invention, in the dual link structure for the narrow bezel, when forming the link portion contact hole by forming the gate wiring in a double layer including a conductive film that does not respond to dry etching Damage to the gate wiring due to dry etching can be prevented. As a result, the degradation of the upper transparent conductive film is suppressed, thereby providing an effect of reducing defects.

1 is a plan view schematically illustrating a general display device;
FIG. 2 is an enlarged plan view of a portion of the display device illustrated in FIG. 1. FIG.
3 is a plan view schematically illustrating a display device according to a first exemplary embodiment of the present invention.
4 is an enlarged plan view of a portion of a display device according to a first exemplary embodiment of the present invention illustrated in FIG. 3.
FIG. 5 is a view schematically showing a cross section taken along the line A-A 'in the display device according to the first embodiment of the present invention shown in FIG.
Figure 6 is a photograph showing the damage of the gate wiring by dry etching.
7 is a plan view schematically illustrating a display device according to a second exemplary embodiment of the present invention.
FIG. 8 is an enlarged plan view of a portion of a display device according to a second exemplary embodiment of the present invention illustrated in FIG. 7.
FIG. 9 is a view schematically illustrating a cross section taken along line BB ′ in the display device according to the second exemplary embodiment of the present invention illustrated in FIG. 8.
10A through 10E are cross-sectional views sequentially illustrating a manufacturing process of a display device according to a second exemplary embodiment of the present invention illustrated in FIG. 9.

Hereinafter, exemplary embodiments of a display device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view schematically illustrating a display device according to a first exemplary embodiment of the present invention.

4 is an enlarged plan view showing a part of the display device according to the first exemplary embodiment of the present invention shown in FIG. 3, and shows a part of the link portion E ′ in an enlarged manner.

FIG. 5 is a view schematically illustrating a cross section taken along line AA ′ in the display device according to the first exemplary embodiment of the present invention illustrated in FIG. 4.

Referring to the drawings, the display device 100 according to the first embodiment of the present invention includes a pixel unit 120 in which a plurality of sub pixels (not shown) arranged in a matrix form and a driving unit driving the sub pixels are arranged. It consists of.

The driver includes a timing driver (not shown) and a data driver 130. In this case, the data driver 130 may be formed on a panel of the display device 100, and the timing driver may be formed on a flexible circuit board (not shown) connected to the panel. However, the present invention is not limited thereto.

For reference, reference numeral 118 denotes a common line.

In this case, the display device 100 includes, for example, a flat panel display device such as a liquid crystal display device or an organic light emitting display device.

When the liquid crystal display device is used as the display device 100 as an example, although not shown in detail, the panel of the display device 100 may include a color filter substrate as a first substrate and an array substrate 110 as a second substrate. The liquid crystal layer may be formed between the color filter substrate and the array substrate 110.

In this case, the color filter substrate may include a black matrix that distinguishes between a color filter composed of red, green, and blue subcolor filters and the subcolor filter, and blocks light passing through the liquid crystal layer, and the color filter and the black matrix. It consists of an overcoat layer formed on top.

A gate line and a data line are formed in the array substrate 110 to be arranged in a vertical direction, and define a pixel region. A thin film transistor as a switching element is formed in an intersection region of the gate line and the data line, that is, a TFT region.

In this case, the thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode. In addition, the thin film transistor may be configured to form a conductive channel between the source electrode and the drain electrode by a gate insulating film for insulating the gate electrode and a source / drain electrode and a gate voltage supplied to the gate electrode. Layer.

The display device 100 according to the first exemplary embodiment of the present invention configured as described above includes a plurality of link lines 126a and 126b corresponding to the gate lines in order to apply gate signals to the gate lines of the plurality of subpixels. This is necessary.

In this case, the display device 100 according to the first exemplary embodiment of the present invention uses the dual link structure in which link wirings 126a and 126b are formed using data wirings as well as gate wirings. The link wirings 126a and 126b may be designed to have a link portion having a smaller width than that of the conventional one, thereby reducing the bezel width W ′ of the display device 100. That is, in the case of the first embodiment of the present invention, the first link wiring 126a and the second link are formed on different layers, specifically, the gate wiring layer and the data wiring layer, as compared with the conventional case in which the link wiring is formed on the same layer. As the wiring 126b is formed, the distance between neighboring link wirings 126a and 126b can be reduced, so that the same number of link wirings 126a and 126b can be designed in a link portion having a smaller width than before.

In this case, the display device 100 according to the first exemplary embodiment of the present invention applies a dual link structure to a gate line 116 (herein, the gate line 126b) formed on the data line layer. 116 denotes a link part gate line in which the gate line of the pixel part extends toward the driving part). The link part contact holes 140b and 140c are required. That is, the second link wire 126b formed on the data wiring layer is electrically connected to the second connection electrode 145b at the upper portion through the second link portion contact hole 140b, and the second connection electrode 145b. ) Is electrically connected to the lower gate line 116 through the third link portion contact hole 140c so that the second link wiring 126b formed in the data wiring layer is connected to the corresponding gate line 116. do.

In this case, the first link line 126a formed on the gate wiring layer is also electrically connected to the first connection electrode 145a at the upper portion through the first link portion contact hole 140a in the same manner, and the first connection line 126a is electrically connected to the first connection line 126a. The electrode 145a is electrically connected to the lower gate line 116 through the third link portion contact hole 140c, so that the gate line 116 corresponding to the first link line 126a formed in the gate wiring layer is formed. ) Will be connected.

The first link wiring 126a and the second link wiring 126b are alternately formed according to the order of the gate line 116. In this case, for example, the odd-numbered gate line 116 is the first link wiring. The even-numbered gate line 116 may be connected to the second link line 126b. However, the present invention is not limited thereto.

The first and second connection electrodes 145a and 145b may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first link portion contact hole 140a, the second link portion contact hole 140b, and the third link portion contact hole 140c may include a first link wiring 126a, a second link wiring 126b, and The gate line 116 may be formed, and in this case, the first link line 126a and the gate line 116, and the second link line 126b and the gate line 116 may be formed at upper portions thereof. Side contact is made with the first connection electrode 145a and the second connection electrode 145b.

Meanwhile, in the first embodiment of the present invention, the first link wiring 126a and the gate line of the gate wiring layer in the dry etching process of forming the link portion contact holes 140a, 140b, and 140c. 116 may be damaged and the contact resistance with the first and second connection electrodes 145a and 145b may increase. That is, the gate insulating layer 115a and the protective layer 115b are dry-etched to form the link portion contact holes 140a, 140b, and 140c in the jumping region. In this case, the protective layer 115b is formed by the etching process under the same conditions. In the case of the first link wiring 126a and the gate line 116 which must be etched to the gate insulating layer 115a, the first link wiring 126a and the gate line 116 of the contact portion are formed by the dry etching. Some remain to roughen the morphology of the first link interconnection 126a and the gate line 116 without being completely removed (see FIG. 6). Accordingly, ITO disconnection may occur when ITO deposition for the first and second connection electrodes 145a and 145b occurs, or contact resistance may increase, thereby causing a defect.

Accordingly, in the display device according to the second embodiment of the present invention, the gate wiring, that is, the first link wiring and the gate line are formed by a double layer including a conductive layer that does not respond to dry etching. It is characterized in that to prevent damage to the wiring, which will be described in detail with reference to the drawings.

7 is a plan view schematically illustrating a display device according to a second exemplary embodiment of the present invention.

8 is an enlarged plan view showing a part of the display device according to the second exemplary embodiment of the present invention illustrated in FIG. 7, and shows an enlarged part of the link portion E ″.

FIG. 9 is a view schematically illustrating a cross section taken along line BB ′ in the display device according to the second exemplary embodiment of the present invention illustrated in FIG. 8.

Referring to the drawings, the display device 200 according to the second exemplary embodiment of the present invention includes a pixel unit 220 in which a plurality of subpixels (not shown) arranged in a matrix form and a driving unit driving the subpixels. It consists of.

The driver includes a timing driver (not shown), a data driver 230, a level shifter (not shown), and the like. In this case, the data driver 230 is formed on a panel of the display device 200, and the timing driver is formed on a flexible circuit board (not shown) connected to the panel or an external system board connected to the flexible circuit board. Can be. However, the present invention is not limited thereto, and the timing driver may be formed together in the data driver 230.

The driver is mounted on the panel in the form of an integrated circuit (IC), and the flexible circuit board is attached to the panel. In this case, the panel and the flexible circuit board may be attached by an anisotropy conductive film (ACF).

For reference, reference numeral 218 denotes a common line.

In this case, the display device 200 includes, for example, a flat panel display device such as a liquid crystal display device or an organic light emitting display device.

When the liquid crystal display device is used as the display device 200 as an example, although not shown in detail, the panel of the display device 200 has a color filter substrate as a first substrate and an array substrate 210 as a second substrate. The liquid crystal layer may be formed between the color filter substrate and the array substrate 210.

In this case, the color filter substrate may include a black matrix that distinguishes between a color filter composed of red, green, and blue subcolor filters and the subcolor filter, and blocks light passing through the liquid crystal layer, and the color filter and the black matrix. It consists of an overcoat layer formed on top.

A gate line and a data line are formed in the array substrate 210 to be arranged in a vertical direction, and define a pixel region. A thin film transistor as a switching element is formed in an intersection region of the gate line and the data line, that is, a TFT region.

In this case, the thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode. The thin film transistor may further include a gate insulating layer for insulation between the gate electrode and a source / drain electrode, and an active layer forming a conductive channel between the source electrode and the drain electrode by a gate voltage supplied to the gate electrode. .

The display device 200 according to the second exemplary embodiment of the present invention configured as described above has a plurality of link lines 226a and 226a 'corresponding to the gate lines in order to apply gate signals to the gate lines of the plurality of subpixels. 226b).

In this case, the display device 200 according to the second exemplary embodiment of the present invention uses the data wiring as well as the gate wiring to connect the link wirings 226a, 226a ', and 226b as in the first embodiment of the present invention. It is characterized by applying the formed dual link structure. As described above, in the second embodiment of the present invention, the first link wirings 226a and 226a 'and the second link wiring 226b are formed in the gate wiring layer and the data wiring layer, respectively, so that neighboring link wirings 226a and 226b are formed. Since the distance between the terminals can be reduced, the same number of link wirings 226a, 226a ', and 226b can be designed in a link portion having a smaller width than before.

In particular, in the case of the second embodiment of the present invention, the first link wirings 226a and 226a 'and the gate lines 216 and 216' (where the gate lines 216 and 216 'are provided with the gate line toward the driving unit). A gate wiring including an extended link gate gate line) is formed as a double layer including a conductive film that does not respond to dry etching, for example, ITO, aluminum-neodymium (AlNd), or the like. It is possible to prevent damage to the first link wirings 226a and 226a 'and the gate lines 216 and 216' due to dry etching when forming the 240a and 240b. The first link wires 226a and 226a 'and the gate lines 216 and 216' are upper layers, respectively, and an upper first link wire 226a 'made of a conductive material that does not react to dry etching such as ITO and AlNd. A lower resistive opaque conductive material, such as aluminum (Al), copper (Cu), chromium (Cr), molybdenum (Mo), etc., as the upper gate line 216 'and the lower layer, respectively One link wiring 226a and a lower gate line 216 may be formed. However, the present invention is not limited thereto, and the first link wirings 226a and 226a 'and the gate lines 216 and 216' may have a double layer or more structure in which a conductive film that does not respond to dry etching is formed on the uppermost layer. Can be.

As such, when the first link wirings 226a and 226a 'and the gate lines 216 and 216' are configured with at least a double layer including ITO, the gate insulating layer 215a and the protective layer 215b may be dry-etched. The ITO of the upper layer serves as an etch stopper to prevent damage to the gate wiring by the dry etching, that is, the first link wirings 226a and 226a 'and the gate lines 216 and 216'. do.

For reference, it was found that ITO deterioration of the jumping area did not occur when the test was conducted for 1000 hours at a temperature of 60 ° C. and a humidity of 90%.

As the first embodiment of the present invention described above, the display device 200 according to the second embodiment of the present invention employs a dual link structure, so that the second link wiring 226b formed on the data wiring layer is formed by the gate line ( Link portion contact holes 240b and 240c for connecting to the 216 and 216 'are required. That is, the second link wire 226b formed on the data wiring layer is electrically connected to the second connection electrode 245b at the upper portion through the second link portion contact hole 240b, and the second connection electrode 245b. ) Is electrically connected to the lower gate lines 216 and 216 'through the third link portion contact hole 240c, so that the second link wiring 226b formed in the data wiring layer corresponds to the gate line 216, 216 ').

In this case, the first link wires 226a and 226a 'formed on the gate wiring layer are electrically connected to the upper first connection electrode 245a through the first link part contact hole 240a in the same manner. As the first connection electrode 245a is electrically connected to the lower gate lines 216 and 216 'through the third link portion contact hole 240c, the first link wiring 226a formed in the gate wiring layer is formed. It is connected to the corresponding gate line (216, 216 ').

The first link wires 226a and 226a 'and the second link wires 226b are alternately formed in the order of the gate lines 216 and 216'. In this case, for example, the odd-numbered gate lines 216, 216 'may be connected to the first link lines 226a and 226a', and even-numbered gate lines 216 and 216 'may be connected to the second link line 226b. However, the present invention is not limited thereto.

The first and second connection electrodes 245a and 245b may be formed of a transparent conductive material such as ITO or IZO. The second link contact hole 240b may be formed to penetrate the second link wiring 226b, and in this case, the second link wiring 226b may have a second connection electrode 245b thereon. And side contact. In contrast, the first link portion contact hole 240a and the third link portion contact hole 240c are formed to expose the upper first link wiring 226a 'and the upper gate line 216', respectively. The upper first link line 226a 'and the upper gate line 216' are in surface contact with the first connection electrode 245a thereon.

That is, in the present invention, the first link wiring of the contact portion between the first and second connection electrodes 245a and 245b of the link portion, the first link wirings 226a and 226a ', and the gate lines 216 and 216'. 226a, 226a ') and gate lines 216, 216' by improving the surface of the first and second connection electrodes 245a and 245b and the first link wirings 226a and 226a 'and the gate lines 216 and 216. By facilitating the connection between '), the resistance of the contact portion can be reduced. Therefore, the degradation of the first and second connection electrodes 245a and 245b due to the increase in contact resistance can be prevented, thereby preventing the failure.

In this case, when the upper first link wire 226a 'and the upper gate line 216' are formed of the same ITO as the first and second connection electrodes 245a and 245b, the first link part contact hole is formed. Due to the coupling between ITO in the 240a and the third link portion contact hole 240c, the contact resistance may be reduced.

Hereinafter, a method of manufacturing the display device configured as described above will be described in detail with reference to the drawings.

10A to 10E are cross-sectional views sequentially illustrating a manufacturing process of a display device according to a second exemplary embodiment of the present invention as shown in FIG. 9, wherein the array substrate for the liquid crystal display device of the TFT portion of the link portion and the pixel portion in the driving portion is manufactured. The process is shown as an example.

As shown in FIG. 10A, gate electrodes 221 and 221 ′ and a pixel portion gate line (not shown) are formed on the pixel portion of the array substrate 210 made of a transparent insulating material such as glass, and the array substrate ( First link wirings (not shown) and link unit gate lines 216 and 216 'are formed in the driving unit of the 210.

In this case, the pixel portion gate line extends toward the driving portion to form the link portion gate lines 216 and 216 ', and is represented by the same gate lines 216 and 216' for convenience of description.

In this case, the gate electrodes 221 and 221 ', the gate lines 216 and 216', and the first link wiring are formed by depositing a first conductive film and a second conductive film on the entire surface of the array substrate 210 and then photolithography. It is formed by selectively patterning through a process (first mask process).

The gate electrodes 221 and 221 'include a lower gate electrode 221 made of the first conductive film and an upper gate electrode 221' made of the second conductive film, and the gate lines 216 and 216 '. ) May include a lower gate line 216 made of the first conductive layer and an upper gate line 216 'made of the second conductive layer. In addition, although not shown in the drawings, the first link wiring may include a lower first link wiring made of the first conductive film and an upper first link wiring made of the second conductive film.

Here, a low resistance opaque conductive material such as aluminum, copper, chromium, molybdenum, or the like may be used as the first conductive layer, and a conductive material that does not react to dry etching such as ITO or AlNd may be used as the second conductive layer. . The first conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Next, as shown in FIG. 10B, the gate insulating layer 215a and the amorphous layer are formed on the entire surface of the array substrate 210 on which the gate electrodes 221 and 221 ', the gate lines 216 and 216', and the first link wiring are formed. A silicon thin film and an n + amorphous silicon thin film are formed.

Thereafter, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively removed through a photolithography process (second mask process) to form an active layer 224 made of the amorphous silicon thin film in the TFT region of the array substrate 210. do.

In this case, an n + amorphous silicon thin film pattern 225 is formed on the active layer 224 and patterned in substantially the same shape as the active layer 224.

Next, as shown in FIG. 10C, a third conductive layer is formed on the entire surface of the array substrate 210 on which the active layer 224 and the n + amorphous silicon thin film pattern 225 are formed. In this case, the third conductive layer may be made of a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy to form a source / drain electrode, a data line, and a second link wiring. The third conductive layer may have a multilayer structure in which two or more low resistance conductive materials are stacked.

Thereafter, the n + amorphous silicon thin film and the third conductive film are selectively removed through a photolithography process (a third mask process), so that the source electrode 222 and the drain electrode formed of the third conductive film on the active layer 224. 223 is formed.

In this case, a data line (not shown) made of the third conductive layer is formed in the data line region of the array substrate 210 through the third mask process, and at the same time, the third conductive portion is formed in the driving unit of the array substrate 210. A second link wiring 226b made of a film is formed.

The first link wire and the second link wire 226b are alternately formed according to the order of the gate lines 216 and 216 ', and in this case, for example, the odd-numbered gate lines 216 and 216' The even-numbered gate lines 216 and 216 'may be connected to the second link line 226b.

In this case, an ohmic contact layer formed of the n + amorphous silicon thin film on the active layer 224 and ohmic-contacted between the source / drain region of the active layer 224 and the source / drain electrodes 222 and 223. 225n is formed.

Next, as shown in FIG. 10D, a passivation layer 215b is formed on the entire surface of the array substrate 210 on which the source / drain electrodes 222 and 223, the data line, and the second link wiring 226b are formed.

In addition, the protective layer 215b and the gate insulating layer 215a are selectively removed through a photolithography process (a fourth mask process), so that the upper first link wiring and the upper gate line 216 are formed in the driving unit of the array substrate 210. A second contact hole 240b exposing a part of the second link wire 226b while forming a first contact hole 240a and a third contact hole 240c respectively exposing a part of the surface of Will form.

In addition, a fourth contact hole 240d exposing a part of the drain electrode 223 is formed in the pixel portion of the array substrate 210 through the fourth mask process.

In this case, the passivation layer 215b and the gate insulating layer 215a are removed by dry etching using plasma, and the second link wire 226b of the driving unit is etched by the dry etching, thereby lowering the lower array substrate 210. While the second contact hole 240b exposing the surface of the second contact hole 240b is formed, the upper first link wire and the upper gate line 216 'of the driving part are made of a conductive material that does not respond to dry etching such as ITO or AlNd. The first contact hole 240a and the third contact hole 240c exposing the surfaces of the upper first link wire and the upper gate line 216 ′ are not formed, respectively.

As such, the upper first link wiring and the upper gate line 216 'act as an etch stop layer to prevent damage to the gate wiring by dry etching, that is, the first link wiring and the gate lines 216 and 216'. It becomes possible.

Next, as shown in FIG. 10E, after forming a fourth conductive film made of a transparent conductive material on the entire surface of the array substrate 210 on which the protective film 215b is formed, a photolithography process (a fifth mask process) is performed. By selectively patterning, the pixel electrode 228 electrically connected to the drain electrode 223 through the fourth contact hole 240d is formed in the pixel portion of the array substrate 210.

In this case, by selectively patterning the fourth conductive layer using the fifth mask process, the first link wiring and the gate line are respectively formed through the first contact hole 240a and the third contact hole 240c in the link portion. First connection electrodes (not shown) electrically connected to the second and second contact holes 240a and 240c, respectively; and the second link wires 226b, respectively. ) And a second connection electrode 245b electrically connected to the gate lines 216 and 216 '.

The array substrates of the first and second embodiments of the present invention configured as described above are bonded to the color filter substrate by a sealant formed on the outside of the image display area, wherein the thin film transistor, the gate line, A black matrix is formed to prevent light leakage from the data line, and a color filter is formed to realize red, green, and blue colors.

At this time, the color filter substrate and the array substrate are bonded together through a covalent key formed on the color filter substrate or the array substrate.

The present invention can be used not only in liquid crystal display devices, but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

100,200: display device 110,210: array substrate
116,216,216 ': Gate line 120,220: Pixel part
126a, 226a, 226a ': first link wiring 126b, 226b: second link wiring
140a and 240a: first contact hole 140b and 240b: second contact hole
140c and 240c: third contact hole 145a and 245a: first connection electrode
145b and 245b: second connection electrode

Claims (15)

Providing a first substrate and a second substrate divided into a pixel portion and a driver;
Forming a thin film transistor in a pixel portion of the first substrate;
Forming a first link line and a gate line extending from the pixel portion in the driving portion of the first substrate;
Forming a second link interconnection on a first substrate on which the gate line and the first link interconnection are formed;
Forming a protective film on the first substrate on which the second link wiring is formed; And
Bonding the first substrate and the second substrate to each other, wherein the first link wiring and the gate line are formed such that a conductive film that does not respond to dry etching has a structure of two or more layers formed on an upper layer. Method of manufacturing the device. The semiconductor device of claim 1, wherein the passivation layer and the gate insulation layer are dry-etched to form first contact holes and third contact holes that expose surfaces of the first link wires and the gate lines, respectively. And forming a second contact hole for exposing the light. The method of claim 2, wherein a first connection electrode is formed to be electrically connected to the first link line and the gate line through the first contact hole and the third contact hole, respectively. And forming a second connection electrode electrically connected to the second link wiring and the gate line through holes, respectively. The method of claim 1, wherein the first link wiring and the second link wiring are alternately formed in the order of the gate lines, wherein the first link wiring is formed in the gate wiring layer and the second link wiring is formed in the data wiring layer. And reducing the gap between adjacent first and second link wires. The method of claim 1, wherein the conductive film that does not respond to dry etching comprises ITO and aluminum-neodymium. A first substrate divided into a pixel portion and a driver;
A thin film transistor formed on the pixel portion of the first substrate;
First link wirings formed on a driving unit of the first substrate and a gate line extending from the pixel unit;
A second link wiring formed in a state where a gate insulating film is interposed on a first substrate on which the gate line and the first link wiring are formed;
A protective film formed on the first substrate on which the second link wiring is formed; And
And a second substrate bonded to the first substrate, wherein the first link wiring and the gate line have a double layer or more structure having a conductive layer formed on an upper layer that does not react to dry etching. 7. The method of claim 6, further comprising a first contact hole and a third contact hole exposing the surfaces of the first link wiring and the gate line, respectively, and a second contact hole exposing side surfaces of the second link wiring. Display device characterized in that. 8. The display device of claim 7, wherein the first connection electrode and the second contact hole and the third contact hole are respectively electrically connected to the first link line and the gate line through the first contact hole and the third contact hole, respectively. And a second connection electrode electrically connected to the second link line and the gate line. 7. The method of claim 6, wherein the first link wiring and the second link wiring are alternately formed in the order of the gate lines, wherein the first link wiring is formed in the gate wiring layer, and the second link wiring is formed in the data wiring layer. And reducing the gap between adjacent first and second link wires. The display device of claim 9, wherein an odd-numbered gate line is connected to the first link line and an even-numbered gate line is connected to the second link line. The display device of claim 6, wherein the conductive film that does not respond to dry etching comprises ITO and aluminum-neodymium. The display device of claim 6, wherein the second link wire has side contacts with the second connection electrode, and the first link wire and gate line have surface contacts with the first connection electrode. The display device of claim 6, wherein the gate line comprises an upper gate line formed of a conductive film that does not respond to the dry etching, and a lower gate line formed of a low resistance conductive film. The display device of claim 6, wherein the first link wiring comprises an upper first link wiring made of a conductive film that does not respond to the dry etching, and a lower first link wiring made of a low resistance conductive film. The display device of claim 6, wherein the upper first link line and the upper gate line act as an etch stop layer to prevent damage to the first link line and the gate line due to the dry etching.

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