KR20130011006A - Power semiconductor device - Google Patents

Abstract

Embodiments of the present invention relate to a power semiconductor, and a problem to be solved is to provide a power semiconductor device having improved breakdown voltage characteristics and on-resistance characteristics.
To this end, the present invention is a semiconductor substrate of the first conductivity type; An active region formed on the semiconductor substrate and including first regions of a first conductivity type and second regions of a second conductivity type; A plurality of impurity regions having a predetermined depth from the upper surface of the active region and spaced apart from each other, each of the impurity regions each including a first conductivity type source region and a second conductivity type well region; And a gate region formed on the active region and the source region, wherein the first regions and the second regions alternately surround each other with a circumferential direction around one axis perpendicular to the semiconductor substrate. In general, a power semiconductor device repeatedly disposed is provided.

Description

POWER SEMICONDUCTOR DEVICE

Embodiments of the present invention relate to a power semiconductor device.

In general, high power semiconductor devices should have high breakdown voltage and low on-resistance in direct current, and high switching speed (ie, low switching loss) in alternating current. In addition, since the high power semiconductor device requires a higher breakdown voltage value as the rated voltage increases, this requires increasing the thickness and the resistivity of the epitaxial region, which inevitably increases the on-resistance value of the epitaxial region. Therefore, there is a trade-off relationship between the low on-resistance value and the high breakdown voltage value in the high power semiconductor device, and this should be taken into consideration when designing the high power semiconductor device.

On the other hand, the high power semiconductor device has a vertical structure in which electrodes are disposed on two mutually opposing planes. When the vertical semiconductor device is turned on, the drift current flows along the vertical direction. In addition, when the device is turned off, the depletion regions created by the application of the reverse bias voltage are enlarged in the vertical direction.

In order for the vertical semiconductor device to have a high breakdown voltage, it is necessary to use a material having a high resistivity as a material of the drift region between the opposing electrodes, and also increase the thickness of the drift region. In this case, however, the on-resistance value of the device also increases. Increasing the on-resistance of the device adversely affects the device's operating characteristics such as increased conduction loss and reduced switching speed.

In order to solve such a problem, a semiconductor device having a new junction structure has recently been developed. Such a semiconductor device has a structure including an alternating conductivity type drift layer composed of N active regions and P active regions that are alternately arranged. Such an alternating conductivity type drift layer is used as a current path in the on state of the device and depleted in the off state of the device. The horizontal cross-sections of the N active region and the P active region have a stripe shape. In the depletion state of the device, an imbalance between the N charge amount and the P charge amount (field concentration) occurs at the edges of the stripe N active area and the P active area. It is more severe than other parts, resulting in poor breakdown voltage characteristics.

The present invention provides a power semiconductor device having improved breakdown voltage characteristics and on-resistance characteristics.

A power semiconductor device according to an embodiment of the present invention, the first conductive semiconductor substrate; An active region formed on the semiconductor substrate and including first regions of a first conductivity type and second regions of a second conductivity type; A plurality of impurity regions having a predetermined depth from the upper surface of the active region and spaced apart from each other, each of the impurity regions including a source region of a first conductivity type and a well region of a second conductivity type; And a gate region formed on the active region and the source region, wherein the first regions and the second regions alternately surround each other with a circumferential direction around one axis perpendicular to the semiconductor substrate. Repeatedly arranged.

In addition, a central portion may be formed in the active region along one axis perpendicular to the semiconductor substrate, and the central portion may include the first region or the second region.

In addition, the first and second regions may be closed, and may be cylindrical, polygonal, or a combination thereof.

The well region may be formed to have a predetermined depth therein from an upper surface of the active region, and the source region may have a predetermined depth therein from an upper surface of the well region, and may be spaced apart from each other in the well region. Can be formed.

In addition, horizontal sections of the well region and the source region may be closed, and may be circular, polygonal, or a combination thereof.

In addition, the horizontal cross section of the gate area may be a closed shape, and may be circular, polygonal, or a combination thereof.

According to another embodiment of the present invention, a power semiconductor device includes: a semiconductor substrate of a first conductivity type; An active region formed on the semiconductor substrate and including a plurality of first sub active regions and a second sub active region; A plurality of impurity regions having a predetermined depth from the upper surface of the active region and spaced apart from each other, each of the impurity regions including a source region of a first conductivity type and a well region of a second conductivity type; And a gate region formed over the active region and the source region, wherein the plurality of first sub-active regions and the second sub-active regions are formed of first regions of a first conductivity type and a second conductivity type. Each of the first sub-active regions, the first regions and the second regions being alternately repeated in the circumferential direction surrounding the outside of each other about one axis perpendicular to the semiconductor substrate The second sub-active area is alternately formed by surrounding the outside of each other in the circumferential direction with the first and second areas having the plurality of first sub-active areas as one central axis. It is arranged repeatedly.

In addition, the first and second regions may be closed, and may be cylindrical, polygonal, or a combination thereof.

The well region may be formed to have a predetermined depth therein from an upper surface of the active region, and the source region may have a predetermined depth therein from an upper surface of the well region, and may be spaced apart from each other in the well region. Can be formed.

In addition, horizontal sections of the well region and the source region may be closed, and may be circular, polygonal, or a combination thereof.

In addition, the horizontal cross section of the gate area may be a closed shape, and may be circular, polygonal, or a combination thereof.

In addition, central portions may be formed in the plurality of first sub-active regions along one axis perpendicular to the semiconductor substrate, and the central portions may include the first region or the second region.

According to the present invention, it is possible to provide a power semiconductor device having improved breakdown voltage characteristics and on-resistance characteristics.

1A is a view showing a vertical cross section of a power semiconductor device according to an embodiment of the present invention.
FIG. 1B is a diagram illustrating a horizontal cross section of the active region cut along the line AA ′ of FIG. 1A.
1C-1F are cross-sectional views of yet another form of active region in accordance with one embodiment of the present invention.
2A is a view showing a vertical cross section of a power semiconductor device according to another embodiment of the present invention.
FIG. 2B is a diagram illustrating a horizontal cross section of the active region cut along the line BB ′ of FIG. 2A.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

First, a power semiconductor device according to an embodiment of the present invention will be described in detail.

1A is a diagram illustrating a vertical cross section of a power semiconductor device 100 according to an embodiment of the present invention. FIG. 1B is a diagram illustrating a horizontal cross section of the active region 120 taken along the line AA ′ of FIG. 1A. 1C to 1F are cross-sectional views of yet another form of active regions 120 ′, 120 ″, 120 ′ ′, 120 ′ according to one embodiment of the present invention.

1A and 1B, a power semiconductor device 100 according to an embodiment of the present invention includes a semiconductor substrate 110, an active region 120, an impurity region 130, and a gate region 140. do.

The first conductivity type described below may mean an n type, and the second conductivity type may mean a p type, and vice versa. However, in the exemplary embodiment of the present application, the first conductivity type is assumed to be n-type and the second conductivity type is assumed to be described.

For example, the semiconductor substrate 110 may be a drain region as an n + type semiconductor substrate. That is, the semiconductor substrate 110 may be an n + type semiconductor wafer formed by implanting impurities such as phosphorus (P) or arsenic (As).

The active region 120 refers to a drift region and is formed on the n + type semiconductor substrate 110 to have a predetermined thickness and concentration.

The active region 120 may include n-type first regions N2, N4, and N6 and p-type second regions P1, P3, and P5. A junction structure is achieved.

Hereinafter, for better understanding, the n-type first regions N2, N4, and N6 are referred to as N2 fillers, N4 fillers, and N6 fillers, and the p-type second regions P1, P3, and P5 are P1. The filler, P3 filler, and P5 filler will be described. 1A and 1B, three N pillars and three P pillars are illustrated, but this is only an example, and the active region 120 may include more N pillars and P pillars.

The N2, N4, and N6 fillers and the P1, P3, and P5 fillers may have a shape surrounding the outside of each other around the one axis C1 perpendicular to the n-type semiconductor substrate 110 in the circumferential direction. That is, the N and P regions may be alternately arranged in a form of enclosing each other in the outward direction from the center of the one axis C1.

In more detail, as shown in FIG. 1B, a P1 filler is formed in the center of the active region 120, an N2 filler is formed around the outside of the P1 filler in a circumferential direction, and the N2 filler is formed. The outer side of the P3 filler may be formed to surround. In this manner, the active region 120 has N pillars and P pillars having a central axis C1 in the form of 'N6-P5-N4-P3-N2-P1-N2-P3-N4-P5-N6'. It can be arranged alternately and repeatedly while sharing the center.

A central portion may be formed in the active region 120 along one axis C1 perpendicular to the semiconductor substrate. The central portion may be in the form of a pail filled with a center, and may be formed of N or P fillers. When the center of this type is a P filler, the N-pillar of the filler that surrounds the outer side, and when the center is an N-pillar, the filler that surrounds the outer side becomes a P-pillar, in this way different types of filler The central portion may be alternately and repeatedly arranged while sharing the central portion.

N and P pillars except the filler forming the center of the active region 120 is a closed shape, the horizontal cross-section of the N and P pillars may be rectangular, as shown in Figure 1b, in Figures 1c and 1d It may be oval or circular as shown, and may be polygons of various shapes as shown in FIGS. 1E and 1F. Therefore, the N and P fillers may be cylindrical, polygonal or a combination thereof.

The impurity region 130 includes a p-type well region 131 and an n-type source region 133.

The p-type well region 131 may be formed to have a predetermined depth from the upper surfaces of the P1, P3, and P5 pillars. In addition, the p-type well region 131 may be formed at regular intervals in the horizontal direction in the active region 120.

In addition, the p-type well region 131 may be formed along the shapes of the P1, P3, and P5 pillars, respectively. For example, the horizontal cross section may be formed in a closed shape, and may be formed in a circle, a polygon, or a combination thereof.

The source region 133 may be formed to have a predetermined depth from an upper surface of the p-type well region 131. In addition, the source region 133 may be formed at regular intervals in the horizontal direction in the P-type well region 131.

In addition, the source region 133 may be formed along the shape of the p-type well region 131, respectively. For example, the horizontal cross section may be formed in a closed shape, and may be formed in a circle, a polygon, or a combination thereof.

The gate region 140 refers to a gate electrode, and is formed on the N2, N4, and N6 pillars, and both sides thereof overlap the portions of the source regions 133 formed in the adjacent p-type well regions 131, respectively. Can be. The gate electrode 140 may be conventional doped polysilicon, but the material is not limited thereto.

The gate electrode 140 may be formed through the insulating layer 141. The insulating layer 141 may electrically insulate between the gate electrode 140 and the source region 131 and between the gate electrode 140 and the source electrode 150. The gate insulating layer 141 may be a conventional silicon oxide layer, but the material is not limited thereto.

In addition, the gate electrode 140 may be formed in the form of N2, N4, N6 pillars, respectively. For example, the horizontal cross section may be formed in a closed form, and may be formed in a circle, polygon, or a combination thereof. In this case, since the gate electrode 140 is spaced apart from each other at regular intervals in a horizontal direction, a separate gate connection line may be additionally formed. The gate connection line may be formed to be electrically connected while crossing the gate electrodes 140.

The source electrode 150 may be positioned above the power semiconductor device 100 and may be electrically connected to the source region 133. For example, the source electrode 150 may be formed to cover an upper portion of the power semiconductor device 100 on which the gate electrode 140 is formed, and at this time, the source electrode 150 may be electrically connected to a portion of the source region 133 that is exposed. Can be contacted. The source electrode 150 is electrically insulated from the gate electrode 140 by the insulating layer 141. The source electrode 150 may be a conventional aluminum or aluminum alloy, but the material is not limited thereto.

Meanwhile, a drain electrode 160 may be formed under the semiconductor substrate 110. The drain electrode 160 is formed of any one selected from ordinary gold, silver, palladium, nickel, solder, an alloy thereof, or an equivalent thereof, but the material is not limited thereto.

In the embodiment of the power semiconductor device 100 described above, the vertical MOSFET structure including the gate electrode 140, the source electrode 150, and the drain electrode 160 has been described.

However, one embodiment of the present invention is not limited to the vertical MOSFET structure and can be applied to various power semiconductor devices. For example, the present invention may be applied to a general Insulated Gate Bipolar Transistor (IGBT) composed of a base region, an emitter region, and a collector region.

Next, a power semiconductor device according to another embodiment of the present invention will be described in detail.

2A is a view showing a vertical cross section of a power semiconductor device according to another embodiment of the present invention. FIG. 2B is a diagram illustrating a horizontal cross section of the active region cut along the line BB ′ of FIG. 2A.

2A and 2B, a power semiconductor device 200 according to an embodiment of the present invention includes a semiconductor substrate 210, an active region 220, an impurity region 230, and a gate region 240. do.

The first conductivity type described below may mean an n type, and the second conductivity type may mean a p type, and vice versa. However, in the exemplary embodiment of the present application, the first conductivity type is assumed to be n-type and the second conductivity type is assumed to be described.

The semiconductor substrate 210 may be, for example, a drain region as an n + type semiconductor substrate. That is, the semiconductor substrate 210 may be an n + type semiconductor wafer formed by implanting impurities such as phosphorus (P) or arsenic (As). A drain electrode 260 may be formed below the semiconductor substrate 210.

The active region 220 refers to a drift region and is formed on the n + type semiconductor substrate 210 to have a predetermined thickness and concentration.

The active region 220 includes a plurality of first sub-active regions 220A and a second sub-active region 220B. The plurality of first sub-active regions 220A and the second sub-active regions 220B may include n-type first regions and p-type second regions, respectively. For example, as illustrated in FIG. 2A, the plurality of first sub-active regions 220A may include N1 and N2 regions of the first regions, and may include P1 and P2 regions of the second regions. The second sub-active region 220B may include N4 and N6 regions of the first regions and P3 and P5 regions of the second regions. The active region 220 is based on the junction structure of the N region and the P region.

Hereinafter, for better understanding, the n-type first regions N1, N2, N4, and N6 shown in FIGS. 2A and 2B are referred to as N1 fillers, N2 fillers, N4 fillers, and N6 fillers. The regions P1, P2, P3, and P5 will be described as P1 fillers, P2 fillers, P3 fillers, and P5 fillers. 2A and 2B, four N pillars and four P pillars are illustrated, but this is only an example, and the active region 220 may include more N pillars and P pillars.

The first sub-active area 220A may be configured in plural, and in the present embodiment, it is assumed that two first sub-active areas 220A are configured as an example. The two first sub-active regions 220A may include a plurality of N-pillars and P-pillars, and in this embodiment, one N-filler and one P-pillar are configured in one second sub-active region 220A. It is assumed to be an example.

One of the two first sub-active regions 220A may include an N1 filler and a P1 filler, and the other region may include an N2 filler and a P2 filler.

In more detail, as illustrated in FIG. 2B, a P1 filler may be formed in the center of the first sub-active region 220A, and an N1 filler may be formed that surrounds the outer side of the P1 pillar in a circumferential direction. . In addition, a P2 pillar may be formed at the center of the first sub-active region 220A, and an N2 pillar may be formed around the outer side of the P2 pillar in a circumferential direction. Although each of the first sub-active regions 220A of FIGS. 2A and 2B is illustrated as being composed of one N-pillar and P-pillar, more N-pillars as in the form of the active region 120 of the above-described embodiment are illustrated. And P-pillars can be placed alternately and repeatedly, sharing their cores. However, in the present exemplary embodiment, the plurality of first sub-active regions 220A configured as the basic units of the active region 120 of the above-described exemplary embodiment is configured.

The plurality of first sub-active regions 220A may be spaced apart from each other in a horizontal direction, and a portion of the pillars disposed at the outermost sides of the adjacent first sub-active regions 220A may overlap each other. When the first sub active region 220A is formed to be spaced apart from each other, a part of the second sub active region 220A may be interposed in the space.

A central portion may be formed in the first sub-active region 220A along the central axes C1 and C2 perpendicular to the semiconductor substrate. The central portion may be in the form of a pail filled with a center, and may be formed of N or P fillers. When the center of this type is a P filler, the N-pillar of the filler that surrounds the outer side, and when the center is an N-pillar, the filler that surrounds the outer side becomes a P-pillar, in this way different types of filler The central portion may be alternately and repeatedly arranged while sharing the central portion.

The N and P pillars except for the filler forming the center of the first sub-active region 220A are closed, and the horizontal cross section of the N and P pillars may be a quadrangle as illustrated in FIG. It is not limiting. For example, it may be elliptical or circular as shown in FIGS. 1C and 1D, and may be polygons of various shapes as shown in FIGS. 1E and 1F. Accordingly, the N and P fillers may be cylindrical, polygonal, or a combination thereof.

The second sub-active region 220B may be composed of N4, N6, P3, and P5 fillers, and the N4, N6, P3, and P5 fillers are formed to surround the plurality of first sub-active regions 220A. Can be. More specifically, as shown in FIG. 2B, when the filler disposed at the outermost of the first sub-active regions 220A is the N-pillar, the outer circumference of each of the first sub-active regions 220A is circumferentially. The P3 filler may be formed to enclose in a direction, and an N4 filler may be formed outside the P3 pillar. In this manner, the second sub-active region 220B may be formed by forming two N pillars and P pillars in the form of 'N6-P5-N4-P3-220A-P3-220A-P3-N4-P5-N6'. One sub-active region 220A may be alternately and repeatedly arranged as one central portion.

As described above, the plurality of first sub-active regions 220A may be spaced apart from each other in the horizontal direction, and a portion of the fillers disposed at the outermost sides of the adjacent first sub-active regions 220A may overlap each other. Do. When the first sub-active area 220A is formed to be spaced apart from each other, a portion of the second sub-active area 220A, that is, a P3 filler is interposed between the spaces, so that one side of each of the first sub-active areas 220A is formed. It is surrounded by this P3 filler.

The N and P pillars formed in the second sub-active region 220B are closed, and the horizontal cross-section of the N and P pillars may be quadrangular as shown in FIG. 2B, but the present invention is not limited thereto. . For example, it may be elliptical or circular as shown in FIGS. 1C and 1D, and may be polygons of various shapes as shown in FIGS. 1E and 1F. Accordingly, the N and P fillers may be cylindrical, polygonal, or a combination thereof.

The impurity region 230 includes a p-type well region 231 and an n-type source region 233.

The p-type well region 231 may be formed to have a predetermined depth from the upper surfaces of the P1, P3, and P5 pillars. In addition, the p-type well region 231 may be formed at regular intervals in the horizontal direction in the active region 220.

In addition, the p-type well region 231 may be formed along the shapes of the P1, P3, and P5 pillars, respectively. For example, the horizontal cross section may be formed in a closed shape, and may be formed in a circle, a polygon, or a combination thereof.

The source region 233 may be formed to have a predetermined depth from an upper surface of the p-type well region 231 therein. In addition, the source region 233 may be formed at regular intervals in the horizontal direction in the P-type well region 231.

In addition, the source region 233 may be formed along the shape of the p-type well region 231, respectively. For example, the horizontal cross section may be formed in a closed shape, and may be formed in a circle, a polygon, or a combination thereof.

The gate region 240 refers to a gate electrode, and is formed on the N2, N4, and N6 pillars, and both sides thereof overlap the portions of the source regions 233 formed in the adjacent p-type well regions 231, respectively. Can be. The gate electrode 240 may be conventional doped polysilicon, but the material is not limited thereto.

The gate electrode 240 may be formed through the insulating layer 141. The insulating layer 141 may electrically insulate between the gate electrode 240 and the source region 231, and between the gate electrode 240 and the source electrode 250. The gate insulating film 241 may be a conventional silicon oxide film, but the material is not limited thereto.

In addition, the gate electrode 240 may be formed in the form of N2, N4, N6 pillars, respectively. For example, the horizontal cross section may be formed in a closed form, and may be formed in a circle, polygon, or a combination thereof. In this case, since the gate electrode 240 is spaced apart from each other at regular intervals in the horizontal direction, a separate gate connection line may be additionally formed. The gate connection line may be formed to be electrically connected while crossing the gate electrodes 240.

The source electrode 250 may be positioned above the power semiconductor device 200 and may be electrically connected to the source region 233. For example, the source electrode 250 may be formed to cover the upper portion of the power semiconductor device 200 on which the gate electrode 240 is formed, and at this time, the source electrode 250 may be electrically connected to some exposed areas of the source region 233. Can be contacted. The source electrode 250 is electrically insulated from the gate electrode 240 by the insulating layer 141. The source electrode 250 may be conventional aluminum or aluminum alloy, but the material is not limited thereto.

Meanwhile, a drain electrode 260 may be formed under the semiconductor substrate 210. The drain electrode 260 is formed of any one selected from ordinary gold, silver, palladium, nickel, solder, an alloy thereof, or an equivalent thereof, but the material is not limited thereto.

In the embodiment of the power semiconductor device 200 described above, the vertical MOSFET structure including the gate electrode 240, the source electrode 250, and the drain electrode 260 has been described.

However, one embodiment of the present invention is not limited to the vertical MOSFET structure and can be applied to various power semiconductor devices. For example, the present invention may be applied to a general Insulated Gate Bipolar Transistor (IGBT) composed of a base region, an emitter region, and a collector region.

According to an embodiment of the present invention, the active region of the PN junction structure is formed in a columnar structure in which the N region and the P region surround each other, whereby edge portions in the N and P regions of the existing stripe shape are formed. Removed. Accordingly, a high breakdown voltage can be obtained by mitigating electric field concentration occurring at the edge portion of the P-N junction structure having a stripe shape.

In addition, since the stripe is formed in a closed form, the area of the active region along the portion connecting between the N-N regions and the P-P region is increased. As the area of the active region increases, the on-resistance of the power semiconductor device decreases.

What has been described above is only one embodiment for implementing the power semiconductor device according to the present invention, and the present invention is not limited to the above-described embodiment, and as claimed in the following claims, the gist of the present invention Without departing from the scope of the present invention, any person having ordinary skill in the art will have the technical spirit of the present invention to the extent that various modifications can be made.

100, 200: power semiconductor device
110, 210: semiconductor substrate:
120, 220: active area
130, 230: impurity regions
140, 240: gate area
150, 250: source electrode
160, 260: drain electrode

Claims (12)

A semiconductor substrate of a first conductivity type;
An active region formed on the semiconductor substrate and including first regions of a first conductivity type and second regions of a second conductivity type;
A plurality of impurity regions having a predetermined depth from the upper surface of the active region and spaced apart from each other, each of the impurity regions each including a first conductivity type source region and a second conductivity type well region; And
A gate region formed on the active region and the source region,
And the first regions and the second regions are alternately arranged in a circumferential direction surrounding the outside of each other with respect to one axis perpendicular to the semiconductor substrate. The method of claim 1,
A central portion is formed in the active region along one axis perpendicular to the semiconductor substrate.
The center portion is the power semiconductor device, characterized in that consisting of the first region or the second region. The method of claim 1,
And the first and second regions are closed, cylindrical, polygonal, or a combination thereof. The method of claim 1,
The well region is formed to have a predetermined depth therein from an upper surface of the active region,
And the source region having a predetermined depth therein from an upper surface of the well region and spaced apart from each other in the well region. The method of claim 4, wherein
The horizontal cross-section of the well region and the source region is a closed shape, the power semiconductor device, characterized in that the circular, polygonal or a combination thereof. The method of claim 1,
The horizontal cross section of the gate region is a closed shape, the power semiconductor device, characterized in that the circular, polygonal or a combination thereof. A semiconductor substrate of a first conductivity type;
An active region formed on the semiconductor substrate and including a plurality of first sub active regions and a second sub active region;
A plurality of impurity regions having a predetermined depth from the upper surface of the active region and spaced apart from each other, each of the impurity regions including a source region of a first conductivity type and a well region of a second conductivity type; And
A gate region formed on the active region and the source region,
The plurality of first sub-active regions and the second sub-active regions each include first regions of a first conductivity type and second regions of a second conductivity type,
Each of the first sub-active regions is formed by alternately repeating the first regions and the second regions to surround the outer side of each other in a circumferential direction with respect to one axis perpendicular to the semiconductor substrate,
The second sub-active region is formed by alternately repeating the first regions and the second regions by surrounding the outside of each other in a circumferential direction with the plurality of first sub-active regions as one central axis. A power semiconductor device, characterized in that. The method of claim 7, wherein
And the first and second regions are closed, cylindrical, polygonal, or a combination thereof. The method of claim 7, wherein
The well region is formed to have a predetermined depth therein from an upper surface of the active region,
And the source region having a predetermined depth therein from an upper surface of the well region and spaced apart from each other in the well region. The method of claim 9,
The horizontal cross-section of the well region and the source region is a closed shape, the power semiconductor device, characterized in that the circular, polygonal or a combination thereof. The method of claim 7, wherein
The horizontal cross section of the gate region is a closed shape, the power semiconductor device, characterized in that the circular, polygonal or a combination thereof. The method of claim 7, wherein
Central portions are formed in the plurality of first sub-active regions along one axis perpendicular to the semiconductor substrate,
The center portion is the power semiconductor device, characterized in that consisting of the first region or the second region.

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