KR20120127251A - Semiconductor device and method for driving semiconductor device - Google Patents

Abstract

A memory device capable of suppressing power consumption and a signal processing circuit using the memory device are provided.
In a storage element using a phase inversion element for inverting and outputting the phase of an input signal, such as an inverter or a clocked inverter, a capacitor for holding data, and controlling the accumulation and emission of charge in the capacitor To form a switching element. For example, one electrode of the capacitor is connected to the input or output of the phase inversion element, and the other electrode is connected to the switching element. The storage element is used for a storage device such as a register or a cache memory included in the signal processing circuit.

Description

Semiconductor device and driving method of semiconductor device {SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE}

The present invention relates to a memory element and a signal processing circuit using a semiconductor device.

Conventionally, transistors using amorphous silicon, polysilicon, microcrystalline silicon and the like have been used in display devices such as liquid crystal displays, but a technique of using them for semiconductor integrated circuits has been proposed (see Patent Document 1, for example).

In recent years, as a new semiconductor material having a high degree of mobility similar to that obtained by polysilicon or microcrystalline silicon and uniform device characteristics equivalent to that obtained by amorphous silicon, a metal exhibiting semiconductor characteristics called an oxide semiconductor. Attention is focused on oxides.

Metal oxides are used for various purposes. For example, indium oxide, which is a well-known metal oxide, is used as a transparent electrode material in liquid crystal display devices and the like. Examples of the metal oxide exhibiting semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, and the like, and transistors using a metal oxide exhibiting such semiconductor characteristics in a channel formation region have been known (Patent Documents). 2 to Patent Document 4).

U.S. Pat.No.7772053 US Patent Application Publication No. 2007/0072439 US Patent Application Publication No. 2011/0193078 United States Patent Application Publication No. 2011/0176357

By the way, signal processing circuits such as a central processing unit (CPU) have a variety of configurations depending on their use, but in general, in addition to the main memory for storing data and programs, registers, cache memories, etc. Various semiconductor memory devices (hereinafter simply referred to as memory devices) are formed. The register is responsible for temporarily holding data for arithmetic processing, program execution, and the like. In addition, a cache memory is formed in a CPU for the purpose of speeding up arithmetic processing by reducing access to the main memory between the computing device and the main memory.

Storage devices such as registers and cache memories need to write data at a higher speed than main memory. Therefore, flip-flops are typically used as registers and SRAMs are used as cache memories.

2A illustrates one of the memory elements constituting the register. The memory element 200 shown in FIG. 2A includes an inverter 201, an inverter 202, a switching element 203, and a switching element 204. The input of the signal IN to the input terminal of the inverter 201 is controlled by the switching element 203. The electric potential of the output terminal of the inverter 201 is given to the circuit of a later stage as a signal OUT. The output terminal of the inverter 201 is connected to the input terminal of the inverter 202, and the output terminal of the inverter 202 is connected to the input terminal of the inverter 201 via the switching element 204. .

The potential of the signal IN input via the switching element 203 is maintained in the memory element 200 by turning off the switching element 203 and turning on the switching element 204.

A more specific circuit configuration of the memory element 200 shown in FIG. 2A is shown in FIG. 2B. The storage element 200 shown in FIG. 2B has an inverter 201, an inverter 202, a switching element 203, and a switching element 204, and the connection structure of these circuit elements is the same as that of FIG. 2A.

The inverter 201 includes a P-channel transistor 207 and an N-channel transistor 208 in which gate electrodes are connected to each other. The P-channel transistor 207 and the N-channel transistor 208 between the node VDD to which the high-level power supply potential is given in the active state and the node VSS to which the low-level power supply potential is given. ) Are connected in series. Similarly, the inverter 202 includes a P-channel transistor 209 and an N-channel transistor 210 in which gate electrodes are connected to each other. The P-channel transistor 209 and the N-channel transistor 210 are connected in series between VDD and VSS.

Inverter 201 shown in FIG. 2B has one side turned off and the other turned on depending on the height of the potential given to the gate electrode of P-channel transistor 207 and the gate electrode of N-channel transistor 208. It works. Thus, the current between VDD and VSS will ideally be zero. However, since some off current flows through the transistor which should be off in reality, it does not become completely zero. Since the same phenomenon occurs with respect to the inverter 202, the power consumption is generated in the memory element 200 even in a state where only data is retained.

For example, in the case of an inverter fabricated using bulk silicon, depending on the size of the transistor, an off current of about 0.1 pA occurs at room temperature with the voltage between VDD and VSS about 1V. Since two inverters of the inverter 201 and the inverter 202 are formed in the memory elements shown in FIGS. 2A and 2B, an off current of about 0.2 pA is generated. In the case of a resistor having about 10 ⁷ memory elements, the off current is 2 µA in the entire register.

In addition, with the progress of miniaturization, since the gate insulator is also thinned, the gate current is also negligible. In addition, the power consumption of the resistor is increasing as the circuit line width is reduced.

In recent years, in order to compensate for the decrease in the speed caused by the decrease in the power supply voltage, the threshold value of the transistor is lowered. As a result, the off current may be increased by about three additional digits per inverter. .

As a result, the power consumption of the resistor is increasing as the circuit line width is reduced. Then, heat generation due to power consumption leads to an increase in the temperature of the IC chip, which leads to a vicious cycle of increasing power consumption.

The SRAM also has a configuration in which an inverter is used as in the above resistor, and power is consumed by the off current of the transistor. Therefore, as in the case of the above-described storage element (register), the cache memory using the SRAM also consumes power even in a state where data is not written.

Thus, one method has been proposed to temporarily stop the supply of the power supply potential to the storage device in a period in which data input / output is not performed in order to suppress power consumption. In the register and the cache memory, a volatile memory device which loses data when the supply potential of the power supply is cut off is used. In this method, a nonvolatile memory device is arranged around the memory device, and the data is stored in the nonvolatile memory device. It is temporarily moving to memory. However, these nonvolatile memory devices have a complicated manufacturing process because magnetic elements and ferroelectrics are mainly used.

In addition, when the power supply is stopped for a long time in the CPU, data loss can be prevented by moving the data in the storage device to an external storage device such as a hard disk or a flash memory before the power supply is stopped. However, it takes time to return data from these external storage devices to registers, cache memory, and main memory. Therefore, backup of data by an external storage device such as a hard disk or a flash memory is not suitable for a short time (for example, 100 µsec to 1 minute) power supply for the purpose of reducing power consumption.

In view of the above problems, the present invention is intended to provide a signal processing circuit capable of suppressing power consumption and a driving method of the signal processing circuit without requiring a complicated manufacturing process. In particular, it is an object of the present invention to provide a signal processing circuit capable of suppressing power consumption by a short power supply stop and a driving method of the signal processing circuit.

In a storage element using a logic element (hereinafter referred to as a phase inversion element) that inverts and outputs the phase of an input signal, such as an inverter or a clocked inverter, a capacitor for holding data, and the capacitor A capacitance switching element is formed which controls the accumulation and release of charge. One electrode of the capacitor is connected to the input or output of the phase inversion element, and the other electrode is connected to either the source or the drain of the capacitor switching element.

The capacitor switching element may include a compound semiconductor (preferably a wide band gap compound semiconductor) such as amorphous silicon, polysilicon, microcrystalline silicon, or an oxide semiconductor in the channel formation region.

Since the capacitance switching element preferably has a high off resistance, a transistor having a channel length of 10 times or more, preferably 20 times or more, more preferably 50 times or more, or 1 μm or more of the minimum processing line width may be used. . At this time, the channel length of the transistor may be 10 times or more, preferably 20 times or more, more preferably 50 times or more of the channel width.

The storage element is used for a storage device such as a register, a cache memory, a main memory, and the like, which the signal processing circuit has. In a transistor using an oxide semiconductor, by using such a long channel transistor, deterioration of the off characteristic due to the short channel effect, in particular, can also be suppressed.

In addition, in this specification, a wide band gap compound semiconductor means the compound semiconductor which has a band gap of 2 electron volts or more. As wide band gap compound semiconductors other than an oxide semiconductor, sulfides, such as zinc sulfide, and nitrides, such as gallium nitride, are mentioned. In any case, it is desirable to make the concentration of donor or acceptor very low by making high purity.

The capacitance switching element is preferably formed so as to overlap above the phase inversion element, and the oxide semiconductor layer used for the capacitance switching element has a curved shape or a shape having at least one concave portion. Alternatively, the channel length can be realized by forming in a limited area of the region on the plurality of phase inversion elements.

In addition, one capacitance switching element may be formed so that it may overlap on some phase inversion element, and one capacitance switching element may be formed so that it may overlap on one phase inversion element. For example, a plurality of linear and switching elements having a channel length of 10 times or more of the channel width may be formed on the plurality of phase inversion elements.

Specifically, a circuit such as a resistor or an SRAM has a circuit (flip-flop circuit, etc.) in which two phase inversion elements (inverter, etc.) are combined, but the area occupied by the circuit is 50F ² (F is the minimum processing line width). or more, typically is ² to 100F 150F ^2. For example, when the area occupied by the circuit in which the two inverters are combined is 50F ² , and the capacitance switching element using the oxide semiconductor is formed in the half area 25F ² , the channel width is F. The channel length can be 25F. If F is 40 nm, the channel length is 1 m.

In addition, it is preferable that the capacitor element is also formed to overlap the phase inversion element, and may be formed in the same layer as the capacitor switching element, or may be formed in a different layer. If formed on the same layer, it is necessary to form the region for the capacitive switching element and the region for the capacitive element, but the manufacturing process can be simplified. On the other hand, if formed in different layers, an extra manufacturing process is required, but it is possible to increase the degree of integration or increase the area used for the capacitor, so that the dielectric of the capacitor is different from the gate insulator of the capacitor for switching. It is also possible to further improve the capacity.

What is necessary is just to determine the ON resistance of a switching element, and the capacitance of a capacitance element according to the speed | rate of the switching operation | movement required. For the purpose of stopping and restoring the power supply, the time required for switching is sufficient to be 100 μs. Depending on the application, 100 milliseconds or more may be sufficient. In addition, what is necessary is just to determine the off resistance of a switching element, and the capacitance of a capacitance element according to the space | interval of switching operation | movement required. In addition, the gate capacitance of the switching element may be larger than that of the capacitor.

In addition to the storage device, the signal processing circuit includes various logic circuits such as a calculation circuit for exchanging data with the storage device. The supply of the power supply voltage to the storage device may be stopped, and the supply of the power supply voltage to the arithmetic circuit which exchanges data with the storage device may be stopped.

Specifically, the memory element has at least two phase inversion elements, a capacitor element, and a capacitor switching element for controlling the accumulation and release of charge in the capacitor. A signal containing data input to the storage element is given to an input terminal of the first phase inversion element. The output terminal of the first phase inversion element is connected to the input terminal of the second phase inversion element. The output terminal of the second phase inversion element is connected to the input terminal of the first phase inversion element. The potential of the output terminal of the first phase inversion element or the input terminal of the second phase inversion element is output as a signal to a storage element or another circuit of a later stage.

The phase inversion element has a configuration in which at least one P-channel transistor and at least one N-channel transistor having gate electrodes connected to each other are connected in series between VDD and VSS.

One electrode of the capacitor is connected to a node to which the potential of the signal is given so that the data of the signal input to the storage element can be stored as needed, and the other electrode is connected to the capacitor switching element.

In a state where a power supply voltage is given between VDD and VSS, when a signal including data is input to an input terminal of the first phase inversion element, the data is held by the first phase inversion element and the second phase inversion element. do. Before the application of the power supply voltage is stopped, the capacitive switching element is turned on and the data of the signal is stored in the capacitive element. With the above configuration, even when the application of the power supply voltage to the phase inversion element is stopped, it is possible to hold the data in the memory element.

The channel formation region of the transistor used in the capacitor switching element includes amorphous silicon, polysilicon, microcrystalline silicon, or a compound semiconductor, for example, a highly purified oxide semiconductor, and has a sufficient channel length. Since it is long, it has the characteristic that the off current is remarkably low.

As the transistor used for the phase inversion element, a semiconductor such as silicon, gallium arsenide, gallium, or germanium, which is amorphous, microcrystalline, polycrystalline, or single crystal, can be used. The transistor may be produced using a thin film semiconductor, or may be produced using a bulk semiconductor wafer.

In addition, the oxide semiconductor preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain In and Zn. Moreover, as a stabilizer for reducing the dispersion | variation in the electrical characteristics of the transistor using the said oxide semiconductor, it is preferable to have gallium (Ga) besides these. Further, it is preferable to have tin (Sn) as a stabilizer. Further, it is preferable to have hafnium (Hf) as a stabilizer. Further, it is preferable to have aluminum (Al) as a stabilizer.

In addition, as other stabilizers, lanthanoids, lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb) Or any one or more of dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

For example, indium oxide, tin oxide, zinc oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg which are oxides of binary metals as oxide semiconductors Oxide, In-Mg oxide, In-Ga oxide, In-Ga-Zn oxide (also referred to as IGZO), an oxide of a ternary metal, Sn-Ga-Zn oxide, and Al-Ga-Zn oxide , Sn-Al-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In -Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy -Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, quaternary metal oxide Phosphorus In-Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide , In-Hf-Al-Zn-based oxides can be used The.

Here, for example, an In—Ga—Zn-based oxide means an oxide having In, Ga, and Zn as main components, and the ratio of In, Ga, and Zn does not matter. In addition, metallic elements other than In, Ga, and Zn may be contained. The oxide semiconductor may contain silicon, sulfur, nitrogen, or the like.

Alternatively, an oxide semiconductor may be one represented by the chemical formula InMO ₃ (ZnO) _m (m> 0). Here, M represents one or a plurality of metal elements selected from Sn, Ga, Al, Hf and Co.

For example, In: Ga: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3) or In: Ga: Zn = 2: 2: 1 (= 2/5: 2/5 In-Ga-Zn-based oxides having an atomic ratio of: 1/5) and oxides in the vicinity of the composition can be used. Or In: Sn: Zn = 1: 1: 1 (= 1/3: 1/3: 1/3), In: Sn: Zn = 2: 1: 3 (= 1/3: 1/6: 1 / 2) or an In-Sn-Zn-based oxide having an atomic ratio of In: Sn: Zn = 2: 1: 5 (= 1/4: 1/8: 5/8) or an oxide near its composition may be used. .

However, the present invention is not limited to these, and those having an appropriate composition may be used in accordance with required semiconductor characteristics (mobility, threshold value, deviation, and the like). Moreover, in order to acquire the required semiconductor characteristic, it is preferable to make carrier density, impurity concentration, defect density, atomic ratio of a metal element and oxygen, bond distance between atoms, density, etc. into an appropriate thing.

For example, in In—Sn—Zn-based oxides, high mobility can be obtained relatively easily. However, even in an In—Ga—Zn-based oxide, mobility can be increased by reducing the defect density in the bulk.

Further, for example, an oxide having an atomic ratio of In, Ga, and Zn of In: Ga: Zn = a: b: c (a + b + c = 1) has an atomic ratio of In: Ga: Zn = A: In the vicinity of the oxide of B: C (A + B + C = 1), a, b, and c are

To satisfy. As r, it is good to set it as 0.05, for example. The same applies to other oxides.

The oxide semiconductor may be single crystal or non-single crystal. In the latter case, it may be amorphous or polycrystalline. Moreover, the structure containing the part which has crystallinity in amorphous, or an amorphous may be sufficient.

Since the oxide semiconductor in the amorphous state can obtain a flat surface relatively easily, the interfacial scattering when a transistor is fabricated using this can be reduced, and relatively high mobility can be obtained relatively easily.

In addition, in oxide semiconductors having crystallinity, defects in bulk can be further reduced, and when the surface flatness is increased, mobility of oxide semiconductors in an amorphous state can be obtained. In order to increase the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface, specifically, the average surface roughness Ra is formed on the surface of 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less. Do it.

An oxide semiconductor is a metal oxide exhibiting semiconductor characteristics of relatively high mobility (1 cm 2 / Vs or more, preferably 10 cm 2 / Vs or more). In addition, an oxide semiconductor (purified OS) in which impurities such as moisture or hydrogen, which becomes an electron donor (donor), and oxygen deficiency are reduced and highly purified are I-type (intrinsic semiconductor, in this specification, carrier concentration is 1 × 10 ¹² / A semiconductor having a cm 3 or less is called an I type) or a semiconductor very close to the I type (substantially I type).

Regarding the hydrogen concentration, specifically, the value of the hydrogen concentration contained in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is 5 × 10 ¹⁹ / cm 3 or less, preferably 5 × Impurities such as water or hydrogen contained in the oxide semiconductor are removed so as to be 10 ¹⁸ / cm 3 or less, more preferably 5 x 10 ¹⁷ / cm 3 or less, and more preferably 1 x 10 ¹⁶ / cm 3 or less. In addition, the amount of oxygen deficiency is also reduced as much as possible. In this way, the removal of the undesirable thing in the intrinsic semiconductor is called high purity.

With this arrangement, the carrier density of the oxide semiconductor film which can be measured by Hall effect measurement is less than 1 × 10 ¹⁴ / cm 3, preferably less than 1 × 10 ¹² / cm 3, more preferably 1 × 10 below the measurement limit. It can be made less than ¹¹ / cm 3. That is, the carrier density of the oxide semiconductor film can be very close to zero.

The band gap of the oxide semiconductor to be used is 2 electron volts or more and 4 electron volts or less, preferably 2.5 electron volts or more and 4 electron volts or less, and more preferably 3 electron volts or more and 4 electron volts or less. As described above, by using an oxide semiconductor film having a wide band gap, sufficiently reducing impurities such as moisture or hydrogen, and oxygen deficiency, and high purity, the off current of the transistor can be lowered.

Here, the analysis of the hydrogen concentration in the oxide semiconductor film and the conductive film is mentioned. Hydrogen concentration measurement in the oxide semiconductor film and in the conductive film is performed by SIMS. It is known that SIMS is difficult to accurately obtain data in the vicinity of a sample surface or in the vicinity of a laminated interface with a film having a different material.

Therefore, when analyzing the distribution of the thickness direction of the hydrogen concentration in a film | membrane by SIMS, the average value in the area | region where there is no extreme fluctuation in a value and a substantially constant value is obtained in the range in which the target film exists is hydrogen. It is adopted as a concentration.

In addition, when the thickness of the film to be measured is small, it may not be possible to find an area where an almost constant value is obtained under the influence of the hydrogen concentration in the adjacent film. In this case, the maximum or minimum value of the hydrogen concentration in the region where the film exists is employed as the hydrogen concentration in the film. In the region where the film is present, when the peak of the peak having a peak and the valley of the peak having no peak exist, the value of the inflection point is employed as the hydrogen concentration.

In addition, it has been found that the oxide semiconductor film formed by sputtering or the like contains a large amount of moisture or hydrogen as impurities. Moisture or hydrogen is an impurity in oxide semiconductors because it is easy to form donor levels.

Thus, in one embodiment of the present invention, in order to reduce impurities such as water or hydrogen in the oxide semiconductor film, the oxide semiconductor film is subjected to a reduced pressure atmosphere, an inert gas atmosphere such as nitrogen or a rare gas, an oxygen gas atmosphere, or Ultra-dry air (moisture when measured using a CRDS (cavity ring-down laser spectroscopy) dew point meter is 20 ppm or less (-55 ° C in terms of dew point), preferably 1 ppm or less, more preferably 10 ppm or less ) The heat treatment is performed in an atmosphere.

It is preferable to perform the said heat processing in the temperature range of 300 degreeC or more and 850 degrees C or less, Preferably it is 550 degreeC or more and 750 degrees C or less. In addition, this heat processing shall not exceed the heat resistance temperature of the board | substrate to be used. The effect of desorption by heat treatment of water or hydrogen was confirmed by TDS (Thermal Desorption Spectrometry).

The heat treatment uses a heat treatment in a furnace or a rapid thermal annealing method (RTA method). The RTA method includes a method using a lamp light source and a method of performing a heat treatment for a short time by moving a substrate in a heated gas. When the RTA method is used, the time required for heat treatment can be made shorter than 0.1 hour.

Specifically, the transistor using the oxide semiconductor film highly purified by the above heat treatment or the like as the active layer exhibits a very low off current (very high off resistance). Specifically, for example, even when an element having a channel width W of 1 × 10 ⁶ μm (the channel length L is 1 μm) is turned off when the drain voltage (voltage between the source electrode and the drain electrode) is 1V. The current (drain current when the voltage between the gate electrode and the source electrode is 0 V or less) can be equal to or less than the measurement limit of the semiconductor parameter analyzer, that is, 1 x 10 ^-13 A or less.

In this case, off current density (off current per channel width of 1 micrometer) is 100 zA / micrometer or less. If the transistor is a long channel and a narrow channel as described above, the off current is 1 zA or less. Therefore, the transistor using the highly purified oxide semiconductor film as the active layer has a significantly lower off current than the transistor using silicon having crystallinity.

Since the leakage of charge from the capacitor can be prevented by using the transistor having the above structure as a capacitor switching element for controlling the discharge of the charge accumulated in the capacitor, even when no power supply voltage is applied, It is possible to maintain the data without losing it. In the period in which the data is held in the capacitor, it is not necessary to supply the power supply voltage to the phase inversion element, so that waste of power consumption due to the off current of the transistor used in the phase inversion element can be reduced. In addition, it becomes possible to reduce the power consumption of the memory device and further the entire signal processing circuit using the memory device.

Further, the off current of the capacitive switching element is determined by the capacitance of the capacitive element and the time to hold the data. For example, when a transistor using a highly purified oxide semiconductor is used as the capacitance switching element, the off current can be 1 zA or less at a drain voltage of 1 V as described above. For example, when the capacitance of the capacitor is 1fF, data can be held for one or more days.

On the other hand, a very long time may not be required as the data retention time. For example, in the case where data is to be retained for only 1 second, when the capacitance of the capacitor is 1fF, the off current may be 0.1fA or less.

For example, in amorphous silicon, polysilicon, microcrystalline silicon and the like, a low off current of 1zA or less, like a highly purified oxide semiconductor, cannot be realized, but it is long channel and narrow channel, or as described in Patent Document 1. By making the semiconductor layer thin, the off current can be made 0.1fA or less.

In addition, since the off current is proportional to the mobility of the semiconductor, the lower the mobility, the lower the off current. Therefore, the off current is lower in amorphous silicon than in polysilicon. On the other hand, a transistor using a low mobility semiconductor is inferior in switching characteristics, but this is rarely a problem in one embodiment of the present invention. This will be described later.

By using the storage element having the above structure in a storage device such as a register or a cache memory included in the signal processing circuit, the loss of data in the storage device due to the power failure can be prevented. Therefore, in one or a plurality of logic circuits constituting the entire signal processing circuit or the signal processing circuit, the power supply can be stopped even for a short time, so that the signal processing circuit and the power consumption can be suppressed. A driving method of the signal processing circuit can be provided.

The operation of stopping and restoring the power supply may be very slow compared to the clock of the logic circuit. In other words, the time required for switching is sufficient to be 100 μsec, and in some cases, 1 m sec or more. This is because the process of transferring data held in the flip-flop circuit of each memory element to the capacitive element or vice versa can be performed simultaneously in all the memory elements. In such low-speed operation, even a long channel and narrow channel transistor are sufficient. In addition, the mobility of the semiconductor may be 1 cm 2 / Vs or more.

In general, between the on current I _on and the off current I _off of a transistor, the time τ _on required for switching and the time τ _off for holding data,

There is a relationship. Therefore, when on current I _on is 10 ⁸ times the off current I _off , τ _off is about 10 ⁶ of τ _on .

For example, if 1 μsec is required as the time required for the capacitive switching element to acquire charge in the capacitive element, the capacitive element and the capacitive switching element can hold data for 1 second. If the data holding period exceeds 1 second, the held data may be returned to the phase inversion element and amplified, and then the operation (refresh) to be acquired to the capacitive element may be repeated every second. .

In the case of the capacitor, the larger the capacitance is less likely to cause an error when the data is returned to the flip-flop circuit. On the other hand, when the capacitance is large, the response speed of the circuit composed of the capacitor and the capacitor switching element is reduced. However, as described above, the operation of stopping and restoring the power supply may be very slow compared to the clock of the logic circuit, and the like, so that if the capacitance is 1 pF or less, it does not interfere at all.

In addition, as shown in DRAM, in general, when the capacitance of the capacitor is increased, it becomes difficult to form the capacitor. However, in one embodiment of the present invention, since the capacitor may be formed on a phase inversion element having an area of 50F ² or more, it is sufficiently easy to compare with a DRAM in which the capacitor is formed in an area of 8F ² or less. A planar type capacitor which is not required may be used.

In addition, since the transistor used as the capacitor switching element is a long channel and a narrow channel, the off current of the transistor can be reduced, and the influence of the parasitic capacitance of the wiring is small, so that the capacitance of the capacitor is used in DRAM. It may be smaller than (about 30 fF).

In addition, when charge is rapidly moved when transferring charge from the phase inversion element to the capacitor, the stability of the phase inversion element may be impaired, and data held in the phase inversion element may be destroyed. At this time, incorrect data is held in the capacitor.

In order to avoid such a problem, what is necessary is just to lower the on-current of a capacitive switching element to some extent. As described above, a long channel and narrow channel transistor or a transistor having a mobility of 10 cm 2 / Vs or less is suitable for this purpose.

According to one embodiment of the present invention, data can be retracted and retained by a capacitive element and the power supply of the memory element can be stopped. Therefore, the threshold value of the transistor used for the phase inversion element in the memory element may be lowered. That is, it becomes a high speed and power saving type memory element.

Moreover, in the said structure, it has a structure in which one electrode of a capacitor | capacitance element is connected to a phase inversion element, and a switching element for capacitance is connected to the other electrode. This configuration has a feature that the gate potential when the capacitive switching element is turned on does not reach the phase inversion element. For this reason, the capacitance switching element is a long channel, and therefore, even if the gate capacitance thereof is larger than that of the capacitance element, the node of the phase inversion element does not fluctuate in the potential of the gate of the capacitance switching element. For example, the gate capacitance of the capacitor switching element may be five times or more the capacitance of the capacitor.

1A and 1B are circuit diagrams of a memory element.
2A and 2B are circuit diagrams of a conventional memory element.
3A to 3C are circuit diagrams of a memory element.
4A to 4D are examples of the operation of the memory element.
5A to 5C are examples of the operation of the memory element.
6A to 6C are examples of the operation of the memory element.
7A to 7D are top views illustrating the structure of the memory element.
8A and 8B are cross-sectional views illustrating the structure of the memory element.
9A and 9B are block diagrams of a signal processing circuit and a CPU using a memory element.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail using drawing. However, this invention is not limited to the following description, It is easily understood by those skilled in the art that the form and detail can be changed in various ways, without deviating from the meaning and range of this invention. Therefore, this invention is not interpreted limited to the description content of embodiment shown below.

In addition, in this specification, a connection means an electrical connection and a current, a voltage, or an electric potential corresponds to the state which can supply or can transmit. Therefore, the connected state does not necessarily refer to a directly connected state, but is a state in which a current, a voltage, or a potential is indirectly connected through a circuit element such as a wiring or a resistor such that a current, a voltage, or a potential can be supplied or transmitted. Also included in that category.

In addition, even if the components are shown as if they are connected to each other on the circuit diagram, in practice, one conductive film, for example, a part of the wiring also functions as an electrode, functions of a plurality of components. Sometimes you just have it together. In this specification, a connection includes even if such one electrically conductive film also has the function of a some component, in the category.

The source and drain electrodes of the transistor change their names according to the polarity of the transistor and the level of the potential given to each electrode. In general, in an N-channel transistor, an electrode to which a low potential is given is called a source electrode, and an electrode to which a high potential is given is called a drain electrode. In the P-channel transistor, an electrode to which a low potential is given is called a drain electrode, and an electrode to which a high potential is given is called a source electrode.

In the present specification, for convenience, it is assumed that the source electrode and the drain electrode are fixed, and there is a case where the connection relationship between the transistors is described.

In this specification, the state in which the transistors are connected in series means a state in which only one of the source electrode and the drain electrode of the first transistor is connected to only one of the source electrode and the drain electrode of the second transistor. it means. In the state where the transistors are connected in parallel, one of the source and drain electrodes of the first transistor is connected to one of the source and drain electrodes of the second transistor, and the source and drain of the first transistor are connected. It means the state in which the other side of the electrode is connected to the other side of the source electrode and the drain electrode of a 2nd transistor.

In addition, integrated circuits such as microprocessors, image processing circuits, digital signal processors (DSPs), and large scale integrated circuits (LSIs) including microcontrollers are included in the scope of the signal processing circuit of the present invention, but are not limited thereto. .

(Embodiment 1)

The storage device of one embodiment of the present invention has one or more memory elements capable of storing one bit of data. In FIG. 1A, an example of the circuit diagram of the memory element which the memory device of this invention has is shown. The memory element 100 shown in FIG. 1A includes a first phase inversion element 101 and a second phase inversion element 102, a switching element 103, and a switching element (inverting and outputting a phase of an input signal). 104, the capacitor 105, and the capacitor switching element 106 for at least.

The signal IN including the data input to the storage element 100 is given to the input terminal of the first phase inversion element 101 via the switching element 103. The output terminal of the first phase inversion element 101 is connected to the input terminal of the second phase inversion element 102. The output terminal of the second phase inversion element 102 is connected to the input terminal of the first phase inversion element 101 via the switching element 104.

The potential of the output terminal of the first phase inversion element 101 or the input terminal of the second phase inversion element 102 is output as a signal OUT to a storage element at a later stage or another circuit. Here, the node of the input terminal of the first phase inversion element 101 is the first node N1, and the node of the output terminal of the first phase inversion element 101 is the second node N2.

In addition, although the example which uses an inverter as the 1st phase inversion element 101 and the 2nd phase inversion element 102 is shown in FIG. 1A, the 1st phase inversion element 101 or the 2nd phase inversion element 102 is shown. In addition to the inverter, a clocked inverter may be used.

The capacitive element 105 includes a first node to which the potential of the input terminal of the memory element 100, that is, the signal IN, is stored so that data of the signal IN input to the memory element 100 can be stored as needed. N1). Specifically, the capacitor 105 is a capacitor having a dielectric between a pair of electrodes, one of which is connected to the first node N1, and the other of which is one of the capacitor switching elements 106. Is connected to the electrode. A node to which the capacitor 105 and the capacitor switching element 106 connect is referred to as a third node N3.

The other electrode of the capacitor switching element 106 is connected to a node to which the potential VCC is given.

In the capacitor switching element 106, a transistor having a highly purified oxide semiconductor in a channel formation region is used.

In addition, the memory element 100 may further have other circuit elements, such as a diode, a resistance element, an inductor, and a capacitor, as needed.

Next, an example of a more specific circuit diagram of the memory element shown in FIG. 1A is shown in FIG. 1B. The storage element 100 shown in FIG. 1B includes a first phase inversion element 101, a second phase inversion element 102, a switching element 103, a switching element 104, and a capacitor 105. ) And a capacitor switching element 106, and the connection structure of these circuit elements is the same as that of FIG. 1A.

In FIG. 1B, the first phase inversion element 101 includes a P-channel transistor 107 in which gate electrodes are connected to each other, and an N-channel transistor 108 in series between VDD and VSS. Has a configuration. Specifically, the source electrode of the P-channel transistor 107 is connected to VSS, and the source electrode of the N-channel transistor 108 is connected to VDD. In addition, the drain electrode of the P-channel transistor 107 and the drain electrode of the N-channel transistor 108 are connected, and the potentials of the two drain electrodes are connected to the output terminal of the first phase inversion element 101. Can be regarded as a potential. The potential of the gate electrode of the P-channel transistor 107 and the gate electrode of the N-channel transistor 108 can be regarded as the potential of the input terminal of the first phase inversion element 101.

In addition, in FIG. 1B, the second phase inversion element 102 is configured such that a P-channel transistor 109 and an N-channel transistor 110 having gate electrodes connected to each other are connected in series between VDD and VSS. Has Specifically, the source electrode of the P-channel transistor 109 is connected to VDD, and the source electrode of the N-channel transistor 110 is connected to VSS. The drain electrode of the P-channel transistor 109 and the drain electrode of the N-channel transistor 110 are connected, and the potentials of the two drain electrodes are the potentials of the output terminals of the second phase inversion element 102. Can be regarded as. The potential of the gate electrode of the P-channel transistor 109 and the gate electrode of the N-channel transistor 110 can be regarded as the potential of the input terminal of the second phase inversion element 102.

In addition, in FIG. 1B, the case where one transistor is used as the switching element 103 is illustrated, and switching of the said transistor is controlled by the signal Sig1 supplied to the gate electrode. Moreover, the case where one transistor is used as the switching element 104 is illustrated, and switching of the said transistor is controlled by the signal Sig2 supplied to the gate electrode.

In addition, although FIG. 1B shows the structure which the switching element 103 and the switching element 104 each have only one transistor, this invention is not limited to this structure. In one embodiment of the present invention, the switching element 103 or the switching element 104 may have a plurality of transistors.

When the switching element 103 or the switching element 104 has a plurality of transistors functioning as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or a combination of series and parallel You may be connected.

In the case where a plurality of transistors are connected in parallel, these polarities may be different, for example, a so-called transfer gate structure in which an N-channel transistor and a P-channel transistor are connected in parallel.

In Fig. 1B, a transistor having an oxide semiconductor in the channel formation region is used as the switching element 106 for the capacitor. The switching of the transistor is controlled by a signal Sig3 applied to the gate electrode thereof. The transistor used for the capacitor switching element 106 has a highly purified oxide semiconductor in the channel formation region, and the channel length is 10 times or more, preferably 20 times or more, of the minimum processing line width, more preferably. Since is 50 times or more, or 1 micrometer or more, the off current is remarkably low as mentioned above.

In FIG. 1B, the capacitor switching element 106 has only one transistor, but the present invention is not limited to this configuration. In one embodiment of the present invention, the capacitor switching element 106 may have a plurality of transistors. When the capacitance switching element 106 has a plurality of transistors functioning as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in series and in parallel. .

In the present embodiment, at least, the transistor used as the switching element in the capacitor switching element 106 may have a highly purified oxide semiconductor in the channel formation region.

Transistors used in the first phase inversion element 101, the second phase inversion element 102, the switching element 103, or the switching element 104 may be formed of amorphous, microcrystalline, polycrystalline, or single crystals other than oxide semiconductors. Semiconductors such as silicon, gallium arsenide, gallium phosphide, indium phosphide, or germanium can be used. In addition, such a transistor may be manufactured using a thin film semiconductor film, or may be manufactured using a bulk (semiconductor wafer).

A circuit arrangement example of the memory element of this embodiment will be described with reference to FIGS. 7A to 7D. 7A shows the layout of one memory element 300 of a normal register. The memory element 300 corresponds to the memory element 100 of FIGS. 1A and 1B. An inverter or the like which is a main part of the memory element 300 may be formed using a known semiconductor technology. That is, an insulator (element isolation region), an n-type region, and a p-type region for element isolation are formed on the semiconductor wafer, and the first layer wiring serving as a gate layer and the second layer wiring formed thereon are formed thereon.

Part of the first layer wiring is the Sig1 wiring 302 for supplying the signal Sig1, and part of the first layer wiring is the Sig2 wiring 303 for supplying the signal Sig2. Part of the second layer wiring is the VDD wiring 301 connected to the node VDD, and part of the second layer wiring is the IN wiring 304 for inputting the signal IN. Fig. 7A also shows the position of the contact hole for connecting upward. In a circuit using a single crystal semiconductor wafer, the node VSS may be connected to the semiconductor wafer.

In addition, as shown in FIG. 7B, a third layer wiring is formed in the upper layer, a part of which is connected to a part of the second layer wiring through a contact hole, and an OUT wiring for outputting a signal OUT. (305). Part of the third layer wirings is the gate wiring 306 and the first capacitor electrode 307 of the transistor using the oxide semiconductor as the switching element.

The gate wiring 306 may be formed to overlap 80% or more, preferably 85% or more, and more preferably 90% or more of the oxide semiconductor region 308 formed thereafter. A part of the gate wiring 306 becomes a gate electrode of the capacitance switching element 106 of FIGS. 1A and 1B. In addition, the signal Sig3 is supplied to the gate wiring 306.

The first capacitive electrode 307 is connected to a part of the second layer wiring (either an input or an output of the inverter) via the contact hole. The first capacitor electrode 307 then becomes a part of the electrode of the element corresponding to the capacitor 105 in FIGS. 1A and 1B.

An oxide semiconductor layer (OS layer) is formed on the third layer wiring. As shown in FIG. 7C, a part of the oxide semiconductor layer has at least one concave portion, and is, for example, a U-shaped oxide semiconductor region 308. In addition, the oxide semiconductor region 308 having a J shape, L shape, V shape, or C shape may be used. Moreover, the shape which has two or more recessed parts (for example, M-shape, N-shape, S-shape, W-shape, Z-shape etc.), or another curved shape may be sufficient.

More generally, when the typical length of one memory element is defined as the square root of the occupied area of the memory element, the length from one end to the other end of the oxide semiconductor region 308 is greater than the above typical length, preferably the typical length. 2 times or more, More preferably, it is 5 times or more. Alternatively, the length of the outer circumference of the oxide semiconductor region 308 may be 2 times or more, preferably 4 times or more, more preferably 10 times or more of the typical length. Alternatively, the numerical value obtained by dividing the area of the oxide semiconductor region 308 by the length around it may be 0.1 times or less of the typical length.

By such a shape, the length from one end of the oxide semiconductor region 308 to the other end can be made longer than the long side of the memory element 300. For example, when the minimum processing line width is F, the length from one end to the other end is 10F or more, preferably 20F or more, more preferably 50F or more, and the oxide semiconductor region 308 having such a shape is used. The channel length of the formed transistor (corresponding to the capacitor switching element 106 in Figs. 1A and 1B) can be 10F or more, preferably 20F or more, and more preferably 50F or more. In the case of FIG. 7C, the length from one end to the other end of the oxide semiconductor region 308 is about 22F.

On the oxide semiconductor layer, as shown in FIG. 7D, a fourth layer wiring is formed. A part of the fourth layer wirings is a source wiring 309 and a second capacitor electrode 310. The source wiring 309 is in contact with one end of the oxide semiconductor region 308 and becomes a source electrode of a transistor formed in the oxide semiconductor region.

The second capacitive electrode 310 overlaps with a portion of the first capacitive electrode 307 to become part of the capacitive element 105 of FIGS. 1A and 1B. In the case of FIG. 7D, the electrode area (area of the portion where two electrodes overlap) of the capacitor is 18F ² . The second capacitor electrode 310 is in contact with the other end of the oxide semiconductor region 308 and becomes a drain electrode of a transistor formed in the oxide semiconductor region.

8A and 8B schematically show the cross-sectional structure of the memory element 300 along the dashed-dotted line X-Y in FIGS. 7A to 7D. In addition, when hatching is the same as FIG. 7A-7D, suppose that the same thing is shown also in FIG. 8A and 8B.

FIG. 8A shows the cross-sectional structure in the step of FIG. 7B. A circuit is formed on the surface of the semiconductor wafer by the isolation region 311, the n-type region, and the p-type region, and the first layer wiring and the second layer wiring. An interlayer insulator 312 is formed between the n-type region, the p-type region, the first layer wiring and the second layer wiring, and a contact plug 313 is formed when electrical connection is required between them. In the upper layer, the gate wiring 306 and the first capacitor electrode 307 are formed in the state of being filled with the buried insulator 314 by the third layer wiring.

FIG. 8B shows the cross-sectional structure in the step of FIG. 7D. On the structure described in FIG. 8A, a gate insulator 315, an oxide semiconductor layer (oxide semiconductor region 308, etc.) and a fourth layer wiring (source wiring 309 or second capacitor electrode 310) are also formed. Here, the thickness of the oxide semiconductor layer is 1 nm to 30 nm, preferably 1 nm to 10 nm, and the thickness of the gate insulator 315 may be 2 nm to 30 nm, preferably 5 nm to 10 nm.

Moreover, like patent document 3, you may comprise so that the material which contact | connects an oxide semiconductor layer and one suitable one or some some large work function may contact | connect. In this manner, the oxide semiconductor layer can be depleted, which is effective in increasing the off resistance.

In this embodiment, since the quality of an oxide semiconductor layer is important, what is necessary is just to use the highly purified oxide semiconductor (film). The detail of the manufacturing method of such an oxide semiconductor (film) is demonstrated in Embodiment 4. FIG.

Next, an example of the operation of the memory element shown in FIG. 1A will be described. In addition, the storage element may be operated by a method other than the following description.

First, at the time of data recording, the switching element 103 is turned on, the switching element 104 is turned off, and the capacitance switching element 106 is turned off. Then, an appropriate power supply voltage is applied between VDD and VSS.

Since the potential of the signal IN given to the memory element 100 is given to the input terminal of the first phase inversion element 101 via the switching element 103, the output terminal of the first phase inversion element 101 is provided. Is a potential at which the phase of the potential of the signal IN is inverted. Then, the switching element 104 is turned on and the input terminal of the first phase inversion element 101 and the output terminal of the second phase inversion element 102 are connected, whereby the first phase inversion element 101 and the second Data is recorded in the phase inversion element 102.

Subsequently, when the input data is held by the first phase inversion element 101 and the second phase inversion element 102, the switching element 104 is turned on and the capacitance switching element 106 is turned off. In the same manner, the switching element 103 is turned off. By turning off the switching element 103, the input data is held by the first phase inversion element 101 and the second phase inversion element 102. At this time, a power supply voltage is maintained between VDD and VSS.

The data held by the first phase inversion element 101 and the second phase inversion element 102 is reflected in the potential of the output terminal of the first phase inversion element 101. Therefore, by reading the potential, data can be read from the storage element 100.

In addition, in order to reduce the power consumption at the time of data retention, when holding the input data in the capacitance element 105, first, the switching element 103 is turned off and the switching element 104 is turned on. With this, the capacitive switching element 106 is turned on. Then, the amount of charge appropriate to the value of the data held by the first phase inversion element 101 and the second phase inversion element 102 is accumulated in the capacitor element 105, thereby reducing the amount of data to the capacitor element 105. Recording is done.

After the data is stored in the capacitor 105, the data stored in the capacitor 105 is retained by turning off the capacitor switching element 106. After the capacitive switching element 106 is turned off, both VDD and VSS are equipotential. In addition, after data is stored in the capacitor 105, the switching element 104 may be turned off.

The variation of the electric potential according to the above operation is demonstrated using FIG. 4A-FIG. 4D. Here, the potential of the node VDD when the first phase inversion element 101 and the second phase inversion element 102 are active is + 1V, and the potential of the node VSS is 0V. Initially, as shown in FIG. 4A, the first node N1 is + 1V or 0V, depending on the data. Although not shown, the potential of the second node N2 is in a phase inverted from that of the first node N1 and is 0V or + 1V. In addition, since the capacitance switching element 106 is off, the third node N3 is in a floating state. In addition, VCC is set to + 1V.

Next, as shown in FIG. 4B, when the capacitor switching element 106 is turned on, the potential of the third node N3 becomes + 1V. At this time, due to the potential difference between the first node N1 and the third node N3, charges corresponding thereto are accumulated between the electrodes of the capacitor 105. That is, data is recorded in the capacitive element 105.

Next, as shown in FIG. 4C, when the capacitance switching element 106 is turned off, the potential of the third node N3 remains at + 1V.

Next, as shown in FIG. 4D, when the potentials of the node VDD and the node VSS are both 0V, the first node N1 also becomes 0V. In addition, VCC is also set to 0V. Then, the potential of the third node N3 is 0V or + 1V depending on the recorded data. If the potential of the first node N1 at the time of writing is + 1V, the potential of the third node N3 at this stage is 0V, and if the potential of the first node N1 at the time of writing is 0V, at this stage The potential of the third node remains as + 1V.

In the case where the input data is held in the capacitor 105, it is not necessary to apply a potential difference between VDD and VSS, so that the P-channel transistors 107 and N of the first phase inversion element 101 have. The off current flowing between VDD and VSS is very close to 0 via the P-channel transistor 109 and the N-channel transistor 110 included in the channel transistor 108 or the second phase inversion element 102. can do. Therefore, the power consumption resulting from the off-current of the memory element at the time of data retention can be reduced significantly, and it becomes possible to suppress the power consumption of the whole signal processing circuit which used the memory | storage device and further the memory device low. .

In addition, since the transistor used for the capacitance switching element 106 uses a highly purified oxide semiconductor in the channel formation region, the off current density is 100 zA / µm or less, preferably 10 zA / µm or less. Preferably, it can be 1 zA / micrometer or less.

In the long channel and narrow channel transistor, the off current is 1 zA or less. As a result, the electric charges accumulated in the capacitor 105 are hardly discharged when the capacitor switching element 106 using the transistor is off, so that data is retained.

Next, the case where data stored in the capacitor 105 is read will be described with reference to FIGS. 5A to 5C. First, the switching element 103 is turned off. In addition, the first phase inversion element 101 and the second phase inversion element 102 are also in an inactive state. For example, a potential of +0.5 V may be given to both VDD and VSS.

The first node N1 and the second node N2 also have a potential of + 0.5V. At this time, the switching element 104 may be on or off. Since the potential of the first node N1 is + 0.5V, the potential of the third node N3 becomes either + 0.5V or + 1.5V depending on the recorded data. In addition, VCC is set to + 1V (see Fig. 5A).

Next, when the capacitance switching element 106 is turned on, the potential of the third node N3 becomes + 1V. At this time, the potential of one electrode of the capacitor 105 (the electrode on the side of the capacitor switching element 106) is changed, so that the potential of the other electrode is also changed. For example, if the potential of the third node N3 was initially + 0.5V, the potential of the third node N3 rises by turning on the capacitor switching element 106, so that the capacitor 105 The potential of the other electrode of the (ie, the first node N1) becomes a rising direction. On the contrary, if the potential of the third node N3 is initially +1.5 V, the potential of the third node N3 will fall, so that the potential of the other electrode of the capacitor 105 is in the direction of falling.

The degree of rise or fall of the potential is determined by the ratio of the capacitance of the capacitor 105 and the capacitance 111 containing the parasitic capacitance of the first node N1. Here, the capacitance 111 containing the parasitic capacitance is four times the capacitance of the capacitor 105. Then, the potential of the first node N1 becomes + 0.6V or + 0.4V. That is, if the potential of the first node N1 at the time of writing is + 1V, it is + 0.6V, and if the potential of the first node N1 at the time of writing is 0V, it becomes + 0.4V (see Fig. 5B).

At this time, since the capacitive switching element 106 is turned on, the gate capacitance of the capacitive switching element 106 is added to the circuit, and since the capacitive element 105 is present therebetween, no matter how large the capacitance is, There is no direct change of the potential of the first node N1 by the gate potential of the capacitor switching element 106.

That is, the potential of the first node N1 is determined without being affected by the gate capacitance or the gate potential of the capacitor switching element 106. For this reason, the capacitance of the capacitor 105 may be smaller than the gate capacitance of the capacitor switching element 106.

Thereafter, +1 V is applied to VDD and 0 V is applied to VSS, thereby applying a power supply voltage between VDD and VSS. In this process, it is preferable to turn on the switching element 104. As a result, the potential difference between the first node N1 and the second node N2 is amplified. That is, in FIG. 5B, when the potential of the first node N1 is + 0.6V, the potential of the first node N1 becomes + 1V and the potential of the second node N2 becomes 0V in this process. In addition, in FIG. 5B, when the potential of the first node N1 is + 0.4V, the potential of the first node N1 becomes 0V and the potential of the second node N2 becomes + 1V in this process. In other words, the state when data is recorded is restored (see Fig. 5C).

If the capacitance of the capacitor 105 is equal to or greater than the capacitance of the capacitor 111 containing the parasitic capacitance, the data can be restored more simply. For example, if the capacitance of the capacitor 105 is equal to the capacitance of the capacitor 111 containing the parasitic capacitance, the potential of the first node is +0.75 V or +0.25 V in the step of FIG. 5B. For this reason, for example, by applying a power supply voltage between VDD and VSS of the first phase inversion element 101 and the second phase inversion element 102 with the switching element 104 off, no malfunction occurs. You can also amplify the signal and restore the data.

In the above, although the example which used the thin-film transistor which used the highly purified oxide semiconductor was shown as the capacitance switching element 106, you may use the thin-film transistor which used amorphous silicon, polysilicon, microcrystalline silicon, etc.

In this case, since the off current is larger than the thin film transistor using the highly purified oxide semiconductor, the time for holding the data is shortened. However, by periodically outputting data to the first phase inversion element 101 and the second phase inversion element 102, and then repeating the operation of returning the data to the capacitor element 105 (refresh). , You can keep the data.

In addition, the refresh in this case can be performed simultaneously in all memory elements requiring refresh, unlike the refresh in the case of DRAM. For this reason, the time required for the entire memory element to be refreshed is very short compared to the case of DRAM. Of course, refreshing may be performed sequentially for each storage element of a required block.

(Embodiment 2)

In this embodiment, another example of the memory element of the memory device of the present invention will be described. In the memory device 100 shown in FIGS. 1A and 1B, one electrode of the capacitor 105 is connected to the first node N1, but may be connected to another part. For example, as with the memory element 100a shown in FIG. 3A, one electrode of the capacitor 105 may be connected to the second node N2, and the memory element 100b shown in FIG. Similarly, one electrode of the capacitor 105 may be connected between the switching element 104 and the second phase inversion element 102. That is, it is good to connect with either the input or the output of the 1st phase inversion element 101 and the 2nd phase inversion element 102. FIG.

The recording and reading of data in such a structure may also be performed in the same manner as described in the first embodiment. In either structure, the gate capacitance occurs when the capacitor switching element 106 is turned on, but the potential of the third node N3 is not changed by this. For this reason, the probability of malfunction when reading data can be reduced.

(Embodiment 3)

In this embodiment, another example of the memory element of the memory device of the present invention will be described. 3C shows a circuit diagram of the memory device of this embodiment as an example.

The storage element 100c illustrated in FIG. 3C includes a first phase inversion element 101 and a second phase inversion element 102, a switching element 103, and a switching element inverting and outputting a phase of an input signal. And at least 104, a first capacitor 105a, a first capacitor switching element 106a, a second capacitor 105b, and a second capacitor switching element 106b.

The signal IN including data input to the memory element 100c is given to the input terminal of the first phase inversion element 101 via the switching element 103. The output terminal of the first phase inversion element 101 is connected to the input terminal of the second phase inversion element 102. The output terminal of the second phase inversion element 102 is connected to the input terminal of the first phase inversion element 101 via the switching element 104. The potential of the output terminal of the first phase inversion element 101 or the input terminal of the second phase inversion element 102 is output as a signal OUT to a storage element at a later stage or another circuit.

One electrode of the first capacitor 105a has an input terminal of the memory element 100c, that is, the potential of the signal IN, so that data of the signal IN input to the memory element 100c can be stored as necessary. Is connected to the first node N1. The other electrode of the first capacitor 105a is connected to one electrode of the switching capacitor 106a for the first capacitor. The other electrode of the first capacitance switching element 106a is connected to a node to which the potential VCC is given.

One electrode of the second capacitor 105b has an output terminal of the memory element 100c, that is, the potential of the signal OUT so that data of the signal IN input to the memory element 100c can be stored as necessary. Is connected to the second node N2. The other electrode of the second capacitor 105b is also connected to one electrode of the second capacitor switching element 106b. The other electrode of the second capacitance switching element 106b is connected to a node to which the potential VCC is given. A node connected between the second capacitor 105b and the second capacitor switching element 106b is referred to as a fourth node N4.

In addition, although the example which uses an inverter as the 1st phase inversion element 101 and the 2nd phase inversion element 102 is shown in FIG. 3C, the 1st phase inversion element 101 or the 2nd phase inversion element 102 is shown. In addition to the inverter, a clocked inverter may be used. In addition, the nodes to which the first capacitor 105a and the second capacitor 105b are connected to the first phase inversion element 101 and the second phase inversion element 102 are not limited to the above, and the phases are mutually different. Two nodes opposite are fine.

The first capacitor switching element 106a and the second capacitor switching element 106b use a transistor having a highly purified oxide semiconductor in a channel formation region. The first capacitor switching element 106a and the second capacitor switching element 106b are the same as the capacitor switching element 106 of Embodiment 1, and the first phase inversion element 101 and the second phase inversion element 102 are similar. When the oxide semiconductor semiconductor is formed above the top surface) and the minimum processing line width is F, the channel length is 10F or more, preferably 20F or more, more preferably 50F or more, or 1 µm.

In addition, the memory element 100c may further have other circuit elements such as a diode, a resistor, an inductor, and a capacitor, as necessary.

Next, an example of the operation of the memory element shown in FIG. 3C will be described. In addition, the storage element may be operated by a method other than the following description. Hereinafter, the potential of the node VDD when the first phase inversion element 101 and the second phase inversion element 102 are active is + 1V, and the potential of the node VSS is 0V.

First, at the time of writing data, the switching element 103 is turned on, the switching element 104 is turned off, the first capacitance switching element 106a is turned off, and the second capacitance switching element 106b is turned off. . Then, a power supply voltage is applied between VDD and VSS. Since the potential of the signal IN given to the memory element 100c is given to the input terminal of the first phase inversion element 101 via the switching element 103, the output terminal of the first phase inversion element 101 is provided. Is the potential at which the phase of the potential of the signal IN is inverted. Then, the switching element 104 is turned on and the input terminal of the first phase inversion element 101 and the output terminal of the second phase inversion element 102 are connected, whereby the first phase inversion element 101 and the second Data is recorded in the phase inversion element 102.

Subsequently, when holding the input data by the first phase inversion element 101 and the second phase inversion element 102, the switching element 104 is turned on and the first capacitance switching element 106a is turned off. The switching element 103 is turned off while the second capacitance switching element 106b is turned off. By turning off the switching element 103, the input data is held by the first phase inversion element 101 and the second phase inversion element 102. At this time, the power supply voltage is maintained between VDD and VSS.

The data held by the first phase inversion element 101 and the second phase inversion element 102 is reflected in the potential of the output terminal of the first phase inversion element 101. Thus, by reading the potential, data can be read from the memory element 100c.

In addition, in order to reduce the power consumption at the time of data retention, when the holding of the input data is performed in the 1st capacitance element 105a and the 2nd capacitance element 105b, the switching element 103 is performed. Off, the switching element 104 is turned on, the 1st capacitance switching element 106a is turned on, and the 2nd capacitance switching element 106b is turned on.

Then, the value of data held in the first phase inversion element 101 and the second phase inversion element 102 via the first capacitance switching element 106a and the second capacitance switching element 106b. By charging an appropriate amount of charge in the first capacitor 105a and the second capacitor 105b, data is written to the first capacitor 105a and the second capacitor 105b. See Embodiment 1 or FIGS. 4A to 4D for details.

The polarity of the voltage between the pair of electrodes of the first capacitor 105a and the voltage of the pair of electrodes of the second capacitor 105b are reversed.

After data is stored in the first capacitor 105a, the data stored in the first capacitor 105a is retained by turning off the first capacitor switching element 106a. After the data is stored in the second capacitor 105b, the second capacitor switching element 106b is turned off to hold the data stored in the second capacitor 105b. After the first capacitive switching element 106a and the second capacitive switching element 106b are turned off, for example, 0 V is applied to VDD and VSS to be at an equipotential.

In this way, when the input data is held in the first capacitor 105a and the second capacitor 105b, it is not necessary to apply a power supply voltage between VDD and VSS. The off current flowing between VDD and VSS of the 101 or second phase inversion element 102 can be made very close to zero. Therefore, the power consumption resulting from the off-current of the memory element at the time of holding | maintenance can be reduced significantly, and it becomes possible to suppress the power consumption of the whole signal processing circuit which used a memory | storage device and also the memory device low.

In addition, since the transistor used for the 1st capacitance switching element 106a and the 2nd capacitance switching element 106b uses the highly purified oxide semiconductor for the channel formation area, the off-current density is 100zA / Μm or less, Preferably it is 10 zA / micrometer or less, More preferably, it can be 1 zA / micrometer or less.

In the long channel and narrow channel transistor, the off current is 1 zA or less. As a result, when the first capacitance switching element 106a using the transistor is off, the electric charge accumulated in the first capacitance element 105a hardly discharges, so that data is retained. Further, when the second capacitance switching element 106b using the transistor is off, the electric charge accumulated in the second capacitance element 105b is hardly discharged, so that data is retained.

Next, the case where data stored in the first capacitive element 105a and the second capacitive element 105b is read will be described with reference to FIGS. 6A to 6C. First, the switching element 103 is turned off. In addition, the first phase inversion element 101 and the second phase inversion element 102 are also in an inactive state. For example, a potential of 0 V may be provided to both VDD and VSS.

The first node N1 and the second node N2 also have a potential of 0V. At this time, the switching element 104 may be on or off. Since the potential of the first node N1 is 0V, the potential of the third node N3 becomes either 0V or + 1V depending on the recorded data. Further, the potential of the fourth node N4 is in a phase opposite to that of the third node, depending on the recorded data, and becomes either 0V or + 1V. VCC is set to + 1V (see Fig. 6A).

Next, when the first capacitance switching element 106a is turned on, the potential of the third node N3 becomes + 1V. At this time, when the potential of one electrode of the first capacitor 105a is changed, the potential of the other electrode is also changed. For example, if the potential of the third node N3 is initially 0 V, the potential of the third node N3 rises by turning on the first capacitance switching element 106a, so that the first capacitance element ( The potential of the other electrode (ie, the first node N1) of 105a is in a rising direction. On the contrary, if the potential of the third node N3 is initially + 1V, the potential of the third node N3 does not change, and the potential of the other electrode of the first capacitor 105a does not change.

By turning on the second capacitive switching element 106b, the same thing as the above also occurs in the second capacitive element 105b. As a result, if the potential of the fourth node N4 is initially + 1V, The potential of the two nodes N2 does not change, and if the potential of the fourth node N4 is 0V, the potential of the second node N2 is in a rising direction.

As described in the first embodiment, the degree of the potential rise is the capacitance of the first capacitor 105a, the capacitance containing the parasitic capacitance of the first node N1, and the capacitance of the second capacitor 105b. And the ratio containing the parasitic capacitance of the second node N2. Here, the capacitance containing the parasitic capacitance of the first node N1 is four times the capacitance of the first capacitor 105a, and the capacitance containing the parasitic capacitance of the second node N2 is the second capacitance element ( It is assumed that it is four times the capacity of 105b).

Then, the potential of the first node N1 is + 0.1V or 0V, and the potential of the second node N2 is 0V or + 0.1V. That is, if the potential of the first node N1 at the time of writing is + 1V (that is, the potential of the second node N2 at the time of writing is 0V), the potential of the first node N1 is + 0.1V, the second If the potential of the node N2 becomes 0V and the potential of the first node N1 at the time of writing is 0V (that is, the potential of the second node N2 at the time of writing is + 1V), the first node N1 The potential of is 0V and the potential of the second node N2 is + 0.1V (see Fig. 6B).

At this time, since the first capacitance switching element 106a or the second capacitance switching element 106b is turned on, the gate capacitance of the first capacitance switching element 106a or the second capacitance switching element 106b is turned on. In addition to this circuit, since the first capacitive element 105a and the second capacitive element 105b are present therebetween, no matter how large these capacities are, the first node N1 or the second node N2 is directly connected. The potential does not change with the potential of these gates.

That is, the potential of the first node N1 or the second node N2 without being affected by the gate capacitance of the first capacitance switching element 106a or the second capacitance switching element 106b or the potential of these gates. Is determined. For this reason, the capacitance of the first capacitor 105a or the second capacitor 105b may be smaller than the gate capacitance of the first capacitor switching element 106a or the second capacitor switching element 106b.

Thereafter, while the switching element 104 is turned on, the potential of VDD is raised to + 1V while the potential of VSS is maintained at 0V (see Fig. 6C). As a result, the potential difference between the first node N1 and the second node N2 is amplified. That is, in FIG. 6B, if the potential of the first node N1 is + 0.1V and the potential of the second node N2 is 0V, the potential of the first node N1 becomes + 1V in this process, and the second node The potential of (N2) becomes 0V. In addition, in FIG. 6B, if the potential of the first node N1 is 0V and the potential of the second node N2 is + 0.1V, the potential of the first node N1 becomes 0V in this process, and the second node ( The potential of N2) becomes + 1V. In other words, the state when data is recorded is restored.

In this embodiment, data can be restored without using the intermediate potential (+ 0.5V) required in the first embodiment. The matter disclosed in this embodiment can be implemented in appropriate combination with the matter disclosed by the other embodiment.

(Fourth Embodiment)

In this embodiment, the formation method of an oxide semiconductor film is demonstrated with reference to FIG. 8B. Initially, an oxide semiconductor film of a required thickness is formed on the gate insulator 315. The oxide semiconductor film can be formed by sputtering in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (for example argon) and oxygen mixed atmosphere. The oxide semiconductor as described above can be used for the oxide semiconductor film.

In addition, before forming the oxide semiconductor film by the sputtering method, it is preferable to perform reverse sputtering to introduce an argon gas to generate plasma to remove dust adhering to the surface of the buried insulator 314. Reverse sputtering is a method of modifying a surface by applying a voltage using an RF power supply to a substrate side in an argon atmosphere without applying a voltage to the target side, thereby forming a plasma in the vicinity of the substrate. In addition, you may use nitrogen, helium, etc. instead of an argon atmosphere. This step also has a surface planarization effect. Moreover, you may carry out in the atmosphere which added oxygen, nitrous oxide, etc. to argon atmosphere. Moreover, you may carry out in the atmosphere which added chlorine, carbon tetrafluorocarbon, etc. to argon atmosphere.

In this embodiment, an In-Ga-Zn oxide non-single crystal film having a thickness of 5 nm obtained by a sputtering method using a metal oxide target containing In (indium), Ga (gallium), and Zn (zinc) is an oxide semiconductor. Used as a film. As the target, for example, the composition ratio of atoms of each metal is In: Ga: Zn = 1: 1: 0.5, In: Ga: Zn = 1: 1: 1, or In: Ga: Zn = 1: 1: Two metal oxide targets can be used. In this embodiment, since it heat-treats later and intentionally crystallizes, it is preferable to use the metal oxide target which crystallization tends to occur. Moreover, the filling rate of the metal oxide target containing In, Ga, and Zn is 90% or more and 100% or less, Preferably they are 95% or more and 99.9% or less. By using the metal oxide target with a high filling rate, the impurity concentration in the oxide semiconductor film formed can be reduced, and the transistor of electrical characteristics or high reliability can be obtained.

The substrate is held in the process chamber in a reduced pressure state, a sputtering gas from which hydrogen and moisture are removed while introducing residual moisture in the process chamber is introduced, and an oxide semiconductor film is formed on the insulating surface with a metal oxide as a target. At the time of film formation, the substrate temperature may be 100 ° C or more and 600 ° C or less, preferably 200 ° C or more and 400 ° C or less. By forming a film while heating the substrate, the impurity concentration contained in the formed oxide semiconductor film can be reduced, and crystallinity can be increased. In addition, damage due to sputtering is reduced.

In order to remove residual moisture in a process chamber, it is preferable to use a suction type vacuum pump. For example, it is preferable to use a cryopump, an ion pump, and a titanium servation pump. As the exhaust means, a cold trap may be applied to the turbopump. When the process chamber is evacuated using a cryopump, for example, compounds containing hydrogen atoms such as hydrogen atoms and water (H ₂ O) (preferably compounds containing carbon atoms) and the like are exhausted. The concentration of impurities contained in the oxide semiconductor film formed in the processing chamber can be reduced.

As an example of film-forming conditions, the conditions which made the distance between a board | substrate and a target 170 mm, a pressure 0.4Pa, a direct current (DC) power supply 0.5kW, and oxygen (100% of oxygen flow rates) atmospheres apply. In addition, when a pulsed direct current (DC) power supply is used, dust called particle | grains which generate | occur | produce at the time of film-forming can be reduced, and since film thickness distribution becomes uniform, it is preferable. The oxide semiconductor film is preferably 1 nm or more and 30 nm or less. Moreover, an appropriate thickness differs with the oxide semiconductor material to apply, and what is necessary is just to select thickness suitably according to a material.

In order to prevent hydrogen, hydroxyl groups and moisture from being contained in the oxide semiconductor film as much as possible, as a pretreatment for film formation, the substrate is preheated in a preheating chamber of a sputtering apparatus to remove impurities such as hydrogen and moisture adsorbed on the substrate. It is preferable to evacuate. Moreover, the temperature of preheating is 100 degreeC or more and 600 degrees C or less, Preferably they are 150 degreeC or more and 300 degrees C or less. In addition, a cryopump is preferable for the exhaust means formed in the preheating chamber. In addition, the process of this preheating can also be abbreviate | omitted.

Subsequently, heat treatment is performed to grow crystals from the surface of the oxide semiconductor film, thereby obtaining an oxide semiconductor film in which at least part of the crystallized or single crystal is obtained. The temperature of heat processing is 450 degreeC or more and 850 degrees C or less, Preferably you may be 600 degreeC or more and 700 degrees C or less. In addition, heating time shall be 1 minute or more and 24 hours or less. The crystal layer is a plate crystal having an average thickness of 2 nm or more and 10 nm or less, with crystal growth growing from the surface toward the inside. In addition, the crystal layer formed on the surface has a-b surface in the surface, and has c-axis orientation in the perpendicular direction with respect to the surface. In this embodiment, the entire oxide semiconductor film may be crystallized by heat treatment.

Moreover, in heat processing, it is preferable that nitrogen, oxygen, or rare gas, such as helium, neon, argon, does not contain water, hydrogen, etc. Alternatively, the purity of nitrogen, oxygen, or rare gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (ie, impurity concentration is 1 ppm or less). Preferably 0.1 ppm or less). In addition, the H ₂ O may be conducted to a heat treatment under a dry air atmosphere 20ppm or less. In this embodiment, heat processing of 700 degreeC and 1 hour is performed in dry air atmosphere.

In addition, the heat processing apparatus is not limited to an electric furnace, and may be provided with the apparatus which heats a to-be-processed object by heat conduction or heat radiation from a heat generating body, such as a resistance heating body. For example, a Rapid Thermal Anneal (RTA) device such as a Gas Rapid Thermal Anneal (GRTA) device or a Lamp Rapid Thermal Anneal (LRTA) device may be used. An LRTA apparatus is an apparatus which heats a to-be-processed object by the radiation of the light (electromagnetic wave) emitted from lamps, such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, and a high pressure mercury lamp. A GRTA apparatus is an apparatus which heat-processes using high temperature gas. As the gas, a rare gas such as argon or an inert gas that does not react with the object to be processed by heat treatment such as nitrogen is used.

For example, as a heat treatment, the substrate may be moved into an inert gas heated at a high temperature of 650 ° C to 700 ° C, heated for several minutes, and then GRTA may be performed in which the substrate is moved and discharged in an inert gas heated at a high temperature. . GRTA enables short heat treatments at high temperatures.

Next, the oxide semiconductor region 308 is formed by processing the shape of the oxide semiconductor film into the shape described in Embodiment 1 using the photolithography method. Moreover, you may form the resist mask for this by the inkjet method. When the resist mask is formed by the inkjet method, the photomask is not used, and thus manufacturing cost can be reduced.

The matter disclosed in this embodiment can be implemented in appropriate combination with the matter disclosed by the other embodiment.

(Embodiment 5)

9A shows an example of a signal processing circuit of one embodiment of the present invention using the memory element described in the above embodiment as a storage device. The signal processing circuit of one embodiment of the present invention includes at least one computing device and at least one storage device. Specifically, the signal processing circuit 400 shown in FIG. 9A includes the arithmetic circuit 401, the arithmetic circuit 402, the memory device 403, the memory device 404, the memory device 405, and the control device 406. ) And a power supply control circuit 407.

The arithmetic circuit 401 and the arithmetic circuit 402 include an adder, a multiplier, various arithmetic units, and the like, as well as a logic circuit for performing a simple logic operation. The storage device 403 functions as a register that temporarily holds data at the time of the arithmetic processing in the arithmetic circuit 401. The memory device 404 functions as a register which temporarily holds data at the time of the arithmetic processing in the arithmetic circuit 402.

The storage device 405 can be used as a main memory, and can store a program executed by the control device 406 as data, or can store data from the arithmetic circuit 401 and the arithmetic circuit 402.

The control device 406 collectively handles operations of the calculation circuit 401, the calculation circuit 402, the memory device 403, the memory device 404, and the memory device 405 of the signal processing circuit 400. It is a circuit to control. In addition, although the control apparatus 406 shows the structure which is a part of signal processing circuit 400 in FIG. 9A, the control apparatus 406 may be formed outside the signal processing circuit 400. As shown in FIG.

By using the memory elements described in the above embodiments for at least one of the memory device 403, the memory device 404, and the memory device 405, the memory device 403, the memory device 404, and the memory device 405. Even if part or all of the supply of the furnace power supply voltage is stopped, data can be retained. Therefore, part or all of the supply of the power supply voltage to the whole signal processing circuit 400 can be stopped and power consumption can be suppressed.

For example, the supply of the power supply voltage to any one or more of the memory device 403, the memory device 404, or the memory device 405 can be stopped, and power consumption can be suppressed. Alternatively, for example, the potential between the node VDD and the node VSS of the memory element 100 shown in Figs. 1A and 1B is made the same, and Sig3 has no artificial potential (especially 0.5 V to ground potential). Low potential of 1.5V) is also effective in reducing power consumption.

When Sig3 is set to the above potential, it is thought to flow between the gate electrode of the capacitor switching element 106 and the oxide semiconductor region, but in reality, the value is so small that the value cannot be measured. Do not. On the other hand, if there is a potential difference corresponding to the node VDD and the node VSS, a through current of the inverter is generated and consumes a considerable amount of power. Therefore, the effect of power consumption reduction by stopping supply of power to the nodes VDD and VSS is absolute.

In addition to stopping the supply of the power supply voltage to the storage device, the supply of the power supply voltage to the arithmetic or control circuit for exchanging data with the storage device may be stopped. For example, in the arithmetic circuit 401 and the memory device 403, when the operation is not performed, the supply of the power supply voltage to the arithmetic circuit 401 and the memory device 403 may be stopped.

In addition, the power supply control circuit 407 includes the arithmetic circuit 401, the arithmetic circuit 402, the memory device 403, the memory device 404, the memory device 405, and the control device of the signal processing circuit 400. The magnitude of the power supply voltage supplied to 406 is controlled. As described above, the power supply control circuit can control electric potentials of VDD, VSS, and Sig3 to reduce power most effectively.

When the supply of the power supply voltage is stopped, the supply may be stopped in the power supply control circuit 407, and the arithmetic circuit 401, the arithmetic circuit 402, the memory device 403, the memory device 404, and the memory may be stopped. In each of the apparatus 405 and the control apparatus 406, supply may be stopped. That is, the switching element for stopping the supply of the power supply voltage may be formed in the power supply control circuit 407, and includes the arithmetic circuit 401, the arithmetic circuit 402, the memory device 403, the memory device 404, It may be provided in each of the memory device 405 and the control device 406. In the latter case, the power supply control circuit 407 does not necessarily need to be formed in the signal processing circuit of the present invention.

In addition, a memory device that functions as a cache memory may be provided between the memory device 405 that is the main memory, the arithmetic circuit 401, the arithmetic circuit 402, and the control device 406. By forming the cache memory, it is possible to reduce the low-speed access to the main memory and speed up signal processing such as arithmetic processing. The power consumption of the signal processing circuit 400 can be suppressed by using the above-described storage element in the storage device functioning as the cache memory.

(Embodiment 6)

In this embodiment, the structure of a CPU which is one of the signal processing circuits of one embodiment of the present invention will be described.

9B shows the configuration of the CPU of this embodiment. The CPU illustrated in FIG. 9B includes an arithmetic logic unit (ALU) 411, an ALU controller 412, an instruction decoder 413, and an interrupt controller on the substrate 410. (Interrupt Controller) 414, Timing Controller 415, Register 416, Register Controller 417, Bus Interface (Bus I / F) 418, Rewritable It mainly has a ROM 419 and a ROM interface (ROMI / F) 420. The ROM 419 and the ROM interface 420 may be formed on different chips. Of course, the CPU shown in Fig. 9B is merely an example of a simplified configuration, and the actual CPU has a variety of configurations depending on its use.

The instruction input to the CPU via the bus interface 418 is input to the instruction decoder 413 and decoded, and then the arithmetic circuit controller 412, the interrupt controller 414, the register controller 417, and the timing controller ( 415).

The arithmetic circuit controller 412, the interrupt controller 414, the register controller 417, and the timing controller 415 perform various controls based on the decoded instructions. Specifically, the arithmetic circuit controller 412 generates a signal for controlling the operation of the arithmetic circuit 411. In addition, the interrupt controller 414 determines the interrupt request from an external input / output device or a peripheral circuit from its priority or mask state and processes it during program execution of the CPU. The register controller 417 generates the address of the register 416 and reads or writes the register 416 in accordance with the state of the CPU.

The timing controller 415 also generates a signal for controlling the timing of the operation of the operation circuit 411, the operation circuit controller 412, the instruction decoder 413, the interrupt controller 414, and the register controller 417. For example, the timing controller 415 includes an internal clock generator that generates the internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signals CLK2 to the various circuits.

In the CPU of this embodiment, a storage element having the structure shown in the above embodiments may be formed in the register 416. The register controller 417 selects the holding operation in the register 416 in accordance with an instruction from the arithmetic circuit 411. That is, in the storage element of the register 416, it is selected whether to hold data by the phase inversion element or to hold data by the capacitor. When the retention of data by the phase inversion element is selected, the supply voltage to the storage element in the register 416 is supplied. When the retention of data in the capacitor is selected, the data is rewritten to the capacitor so that the supply of the power supply voltage to the storage element in the register 416 can be stopped.

In this way, even when the operation of the CPU is temporarily stopped and the supply of the power supply voltage is stopped, data can be retained and power consumption can be reduced. Specifically, for example, the CPU can be stopped while the user of the PC stops inputting information to an input device such as a keyboard, thereby reducing power consumption.

In the present embodiment, the CPU has been described as an example, but the signal processing circuit of the present invention is not limited to the CPU, but is applicable to LSIs such as DSPs, custom LSIs, and field programmable gate arrays (FPGAs). In addition, by using the signal processing circuit according to the present invention, it is possible to provide a highly reliable electronic device and an electronic device with low power consumption.

In particular, in the case of a portable electronic device in which it is difficult to always receive electric power from the outside, by adding a low power consumption signal processing circuit of one embodiment of the present invention to the component thereof, the continuous use time can be extended. Advantages are obtained.

A signal processing circuit of one embodiment of the present invention is a display device, a PC, and a display device equipped with a recording medium (typically, a display capable of reproducing a recording medium such as a DVD: Digital Versatile Disc and displaying the image). Device with). In addition, as an electronic device that can use the signal processing circuit of one embodiment of the present invention, a mobile phone, a game machine including a portable type, a portable information terminal, an electronic book, a camera such as a video camera or a digital still camera, a goggle type display, etc. (Head mounted display), navigation system, sound reproducing apparatus (car audio, digital audio player, etc.), copying machine, facsimile machine, printer, printer multifunction machine, cash dispenser (ATM), vending machine and the like.

100: memory element 100a: memory element
100b: memory element 100c: memory element
101: first phase inversion element 102: second phase inversion element
103 switching element 104 switching element
105: capacitor element 105a: first capacitor element
105b: second capacitance element 106: switching element for capacitance
106a: switching element for first capacitance 106b: switching element for second capacitance
107: P-channel transistor 108: N-channel transistor
109: P-channel transistor 110: N-channel transistor
111: capacitance containing parasitic capacitance 200: memory element
201: Inverter 202: Inverter
203: switching element 204: switching element
207: P-channel transistor 208: N-channel transistor
209 P-channel transistor 210 N-channel transistor
300: memory element 301: VDD wiring
302: Sig1 wiring 303: Sig2 wiring
304: IN wiring 305: OUT wiring
306: gate wiring 307: first capacitor electrode
308: oxide semiconductor region 309: source wiring
310: second capacitor electrode 311: device isolation region
312 interlayer insulation 313 contact plug
314: buried insulator 315: gate insulator
400: signal processing circuit 401: arithmetic circuit
402: arithmetic circuit 403: storage device
404: storage device 405: storage device
406: control device 407: power control circuit
410: substrate 411: arithmetic circuit
412 operation circuit controller 413 command decoder
414: interrupt controller 415: timing controller
416: register 417: register controller
418: bus interface 419: ROM
420: ROM interface N1: first node
N2: second node N3: third node
N4: fourth node IN: signal
OUT: Signal Sig1: Signal
Sig2: Signal Sig3: Signal
CLK1: reference clock signal CLK2: internal clock signal

Claims (20)

In a semiconductor device,
A pair of phase inversion elements, wherein one output terminal of the phase inversion elements is connected to the other input terminal of the phase inversion element to hold data;
A capacitive element;
A switching element, said switching element being provided over at least one of said phase inversion elements and controlling the writing of data to said capacitive element,
One of the electrodes of the capacitor is connected to one of an output terminal and an input terminal of the phase inversion element, and the other of the electrodes of the capacitor is connected to one of a source and a drain of the switching element. In a semiconductor device,
A pair of phase inversion elements, wherein one output terminal of the phase inversion elements is connected to the other input terminal of the phase inversion element to hold data;
A first capacitive element;
A first switching element, said first switching element being provided over at least one of said phase inversion elements and controlling the recording of data for said first capacitive element;
A second capacitive element;
A second switching element, said second switching element being provided over at least one of said phase inversion elements and controlling the writing of data for said second capacitive element,
One of the electrodes of the first capacitor is connected to an input terminal of one of the phase inversion elements,
The other electrode of the first capacitor is connected to one of a source and a drain of the first switching element,
One of the electrodes of the second capacitor is connected to an input terminal of the other of the phase inversion elements,
And the other electrode of the second capacitor is connected to one of a source and a drain of the second switching element. In a semiconductor device,
A pair of phase inversion elements, wherein one output terminal of the phase inversion elements is connected to the other input terminal of the phase inversion element to hold data;
A capacitive element;
A switching element, comprising: a switching element, comprising a semiconductor layer, provided on at least one of the phase inversion elements and controlling the writing of data to the capacitive elements;
One of the electrodes of the capacitor is connected to one of an output terminal and an input terminal of the phase inversion element, and the other electrode of the capacitor is connected to one of a source and a drain of the switching element,
And the switching element has at least one recess in the semiconductor layer. The method of claim 1,
The channel length of the switching element is at least 10 times the minimum processing line width. The method of claim 1,
The channel length of the switching element is 1 µm or more. The method of claim 1,
And the capacitance of the capacitor is lower than the gate capacitance of the switching element. The method of claim 1,
And the switching element comprises an oxide semiconductor in the channel formation region. The method of claim 7, wherein
The oxide semiconductor is an In—Ga—Zn oxide. The method of claim 7, wherein
And a hydrogen concentration in the channel formation region is 5 × 10 ¹⁹ / cm 3 or less. The method of claim 1,
One of the pair of phase inversion elements is a clocked inverter. In the method of driving the semiconductor device according to claim 1,
Setting both the potential of the input terminal of the phase inversion element and the potential of the output terminal to a first potential with the switching element off;
Turning on the switching element;
Activating the phase reversal element;
The first potential is higher than a lower potential among the potentials supplied to the phase inversion element when the phase inversion element is in an active state,
And wherein the first potential is lower than a higher one of the potentials applied to the phase inversion element when the phase inversion element is in an active state. The method of claim 2,
And the channel length of said first switching element is at least 10 times the minimum overhead line width. The method of claim 2,
The channel length of the said 1st switching element is a semiconductor device of 1 micrometer or more. The method of claim 2,
And the capacitance of the first capacitor is lower than the gate capacitance of the first switching element. The method of claim 2,
And the first switching element comprises an oxide semiconductor in a channel formation region. The method of claim 15,
The oxide semiconductor is an In—Ga—Zn oxide. In the method of driving the semiconductor device according to claim 2,
Setting both the potential of the input terminal of the phase inversion element and the potential of the output terminal to a first potential with the first switching element and the second switching element off;
Turning on the first switching element and the second switching element;
Activating the phase reversal element. The method of claim 3, wherein
The channel length of the switching element is at least 10 times the minimum processing line width. The method of claim 3, wherein
The channel length of the switching element is 1 µm or more. The method of claim 3, wherein
And the capacitance of the capacitor is lower than the gate capacitance of the switching element.

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