KR20120022218A - Reram of having buffer layer and method of fabricating the same - Google Patents

Abstract

A resistance change memory having a buffer layer interposed above or below a resistance change layer and a method of manufacturing the same are disclosed. The buffer layer disposed between the resistance change layer and the electrode controls the movement of oxygen ions that cause filament formation during forming and set operations. This adjusts the current capacity of the filament. In particular, oxynitride is included through deposition on the electrode surface of the buffer layer or modification of the electrode surface.

Description

Resistivity changing memory having a buffer layer and a method of manufacturing the same {ReRAM of having Buffer Layer and Method of fabricating the same}

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a resistance change memory device having a buffer layer and a method of manufacturing the same.

Recently, due to the development of the digital information communication and home appliance industry, the research of the device based on the existing charge control is known to reach the limit. In order to overcome these limitations, researches on new memory devices using phase change and magnetic field change have been conducted. The information storage method of new memory devices under study uses the principle of changing the resistance of the material itself by inducing a change of state of the material.

In the case of a flash memory which is a representative device of a nonvolatile memory, a high operating voltage is required for program and erase operations of data. Therefore, when scaled down to a line width of 45 nm or less, malfunction may occur due to interference between adjacent cells, and a slow operation speed and excessive power consumption become a problem.

Magnetic RAM (MRAM), another nonvolatile memory, has certain problems in commercialization due to complicated manufacturing process, multilayer structure, and small margin of read / write operation. Therefore, the development of the next generation nonvolatile memory devices that can replace them is an essential research field.

The ReRAM device has a structure in which upper and lower electrodes are disposed on a thin film, and a resistance change layer made of an oxide thin film is included between upper and lower electrodes. The memory operation is implemented using a phenomenon in which the resistance state of the resistance change layer is changed according to the voltage applied to the resistance change layer. ReRAM is theoretically free from deterioration due to infinite recording and playback, enables high speed operation, and has a non-volatile characteristic. Thus, it has advantages over other types of memory devices in terms of data stability. In addition, when an input pulse is applied, a high speed operation of about 10 ns to 20 ns is possible for a resistance change of 1000 times or more. Since the resistance change layer of the ReRAM device has a single film structure in the manufacturing process, it is possible to achieve high integration and high speed, and to apply the conventional CMOS process and integrated process technology. As the material of the resistance change layer, a binary oxide or a perovskite oxide is mainly used.

Korean Patent Laid-Open Publication No. 2006-83368 discloses a ReRAM using a multilayer film including metal oxides having different composition ratios as a resistance change layer. The metal oxide may be ZrO _x , NiO _x , HfO _x , TiO _x , Ta ₂ O _x , Al ₂ O _x , La ₂ O _x , Nb ₂ O _x , SrTiO _x , Cr doped SrTiO _x or Cr doped SrZrO _x (x is 1.5-1.9) is used.

In general, a binary oxide ReRAM device initially has a process of applying a predetermined voltage (Electroforming: hereinafter, 'forming') to form a conductive filament inside the binary oxide, and then break and regenerate (reset / set) through voltage control. Will go through the process. This controls the current flowing through the filament inside the binary oxide and operates as a nonvolatile memory device.

In the conventional ReRAM device, the filament formed during the forming and set process is not uniform in size, resulting in a filament having excessive current capacity. The filament formed as described above increases the current density required during the reset operation and increases the driving power when the device is implemented.

Accordingly, in order for the ReRAM device to be used in a highly integrated nonvolatile memory, it is required to simplify the manufacturing process, implement various resistance states through low operating voltages, and have low power consumption.

A first object of the present invention for solving the above problems is to provide a resistance change memory having a uniform switching characteristics with a low current density by controlling the current capacity of the filament formed in the oxide during forming and set switching operations.

In addition, a second object of the present invention is to provide a method of manufacturing a resistance change memory for achieving the first object.

The present invention to achieve the first object, a substrate; A lower electrode formed on the substrate; A resistance change layer formed on the lower electrode; An upper electrode formed on the resistance change layer; And a buffer layer disposed between the resistance change layer and the two electrodes.

The present invention to achieve the second object, forming a lower electrode on the substrate; Forming a buffer layer through a thermal oxidation process on the lower electrode; Forming a resistance change layer on the buffer layer; And forming an upper electrode on the resistance change layer.

According to the present invention described above, a buffer layer is inserted between the upper or lower electrode and the oxide thin film. The resistance change memory with a buffer layer restricts the movement of oxygen ions that cause filament formation during forming and set operations. Through this, the current capacity of the filament formed by controlling the thickness of the buffer layer disposed above or below the resistance change layer is controlled. Therefore, it is possible to reduce the operating power of the device and to ensure stable switching characteristics.

1 and 2 are cross-sectional views illustrating a resistance change memory according to a preferred embodiment of the present invention.
3 to 6 are cross-sectional views illustrating a method of manufacturing the resistance change memory shown in FIG. 1 according to a preferred embodiment of the present invention.
FIG. 7 is a graph illustrating voltage-current characteristics of a resistance change memory device manufactured by a preferred embodiment of the present invention.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

Example

1 and 2 are cross-sectional views illustrating a resistance change memory according to a preferred embodiment of the present invention.

First, referring to FIG. 1, the resistance change memory includes a substrate 100, a lower electrode 110, a buffer layer 120 disposed on the lower electrode 110, and a resistance change layer 130 disposed on the buffer layer 120. ) And an upper electrode 140 positioned on the resistance change layer 130.

The substrate 100 may be used as long as it is applied to a conventional semiconductor memory device, and is not particularly limited. Representatively usable substrate 100 may be Si, SiO ₂ , Si / SiO ₂ multi-layer substrate or a polysilicon substrate.

The lower electrode 110 may be formed of a nitride electrode material including TiN or WN or at least one selected from the group consisting of Pt, Au, Al, Cu, Ti, and alloys thereof, depending on the material of the electrode material. To 500 nm in thickness.

In addition, the resistance change layer 130 is Ti oxide, Mg oxide, Ni oxide, Ce oxide, Zn oxide, Hf oxide, Co oxide, Ta oxide, Al oxide, La oxide, Nb oxide, SrTi oxide, Cr doped SrTi At least one selected from the group consisting of oxides and Cr doped SrZr oxides can be used.

The thickness of the buffer layer 120 for limiting oxygen ions in the forming and set processes may be 5 nm to 15 nm, and preferably, 5 nm to 10 nm. If the thickness of the buffer layer 120 is less than 5 nm, a decrease in operating current does not occur. If the thickness exceeds 10 nm, a problem of malfunction due to excessive increase in operating voltage occurs. The buffer layer 120 has at least one selected from the group consisting of TiON, TaON, CoON, and WON. That is, the buffer layer 120 is preferably composed of oxynitride (oxynitride).

In addition, in the present invention, the oxide film constituting the resistance change layer 130 may be changed to the set and reset states of the memory device through different oxygen composition ratios. The oxide films that form the resistance change layer 130 are preferably made of TiO ₂ . The thickness of the TiO ₂ constituting the resistance change layer 130 may be 15 nm to 100 nm, preferably 15 nm to 50 nm. If the thickness of the resistance change layer 130 is less than 15 nm, more filaments are formed due to excessive foaming. In addition, when the thickness of the resistance change layer 130 exceeds 50nm, the operating voltage increases to cause an increase in power consumption.

The upper electrode 140 may be at least one selected from the group consisting of Pt, Au, Al, Cu, Ti, and alloys thereof, or at least one selected from a nitride electrode material including TiN or WN. In addition, the thickness of the upper electrode 140 is preferably formed to a thickness of 20nm to 500nm. The upper electrode 140 is formed in a fine patterned structure through a dry etching process using a shadow mask or photolithography.

Referring to FIG. 2, a buffer layer 120 is formed between the resistance change layer 130 and the upper electrode 140. That is, as compared with FIG. 1, materials of the substrate 100, the lower electrode 110, the resistance change layer 130, the buffer layer 120, and the upper electrode 140 are the same as those described with reference to FIG. 1. However, the buffer layer 120 is interposed between the resistance change layer 130 and the upper electrode 140. That is, the same as described with reference to FIG. 1 except for the position where the buffer layer 120 is interposed.

That is, in FIGS. 1 and 2, the buffer layer 120 is disposed between the resistance change layer 130 and the electrodes 110 and 140. As shown in the above two figures, the buffer layer 120 may be selectively disposed above or below the resistance change layer 130, and may be simultaneously disposed above and below the resistance change layer 130. .

3 to 6 are cross-sectional views illustrating a method of manufacturing the resistance change memory shown in FIG. 1 according to a preferred embodiment of the present invention.

Referring to FIG. 3, the lower electrode 110 is formed on the substrate 100.

The lower electrode 110 is a conventional deposition method using at least one selected from the group consisting of Pt, Au, Al, Cu, Ti and alloys thereof, or at least one selected from a nitride electrode material including TiN or WN. Is formed through.

The deposition method may include physical vapor deposition, chemical vapor deposition, pulsed laser deposition, thermal evaporation, electron beam evaporation, and atomic layer. Atomic layer deposition or molecular beam epitaxy is possible, and sputtering is preferable.

Referring to FIG. 4, a buffer layer 120 is formed on the lower electrode 110. The buffer layer 120 may be at least one selected from the group consisting of TiON, TaON, CoON, and WON, and may be formed using a conventional deposition method or a thermal oxidation process such as the lower electrode 110. Preferably, the buffer layer 120 has TiON. In particular, when the buffer layer is formed through a thermal oxidation process, the buffer layer 120 is formed through surface modification of the lower electrode. That is, a buffer layer may be formed of oxynitride due to thermal oxidation.

The buffer layer 120 formed through the above-described process restricts excessive formation of the filament having excessive current density capacity by preventing oxygen ions from moving when the filament is formed during the initial forming and the repeated switching set process.

Referring to FIG. 5, a resistance change layer 130 is formed on the buffer layer 120. The resistance change layer 130 may be formed in the same manner as the lower electrode 110, or may be formed by one of the methods for forming the lower electrode 110. The resistance change layer 130 may include Ti oxide, Mg oxide, Ni oxide, Ce oxide, Zn oxide, Hf oxide, Co oxide, Ta oxide, Al oxide, La oxide, Nb oxide, SrTi oxide, Cr doped SrTi oxide, or It has Cr doped SrZr oxide. The resistance change layer 130 is preferably formed of TiO ₂ having a thickness of 15nm to 50nm.

Referring to FIG. 6, an upper electrode 140 is formed on the resistance change layer 130.

The upper electrode 140 may have at least one material selected from the group consisting of Pt, Au, Al, Cu, Ti, and alloys thereof, or a nitride electrode material including TiN or WN, and may include shadow masks or photolithography. It is formed into a pattern by a fine dry etching process using.

In addition, the formation of the upper electrode 140 may be achieved using the deposition method proposed in the aforementioned lower electrode 110. In the resistance change memory device formed through the above-described steps, a baking process or an annealing process may be additionally performed as necessary.

FIG. 7 is a graph illustrating voltage-current characteristics of a resistance change memory device manufactured by a preferred embodiment of the present invention.

Referring to FIG. 7, a lower electrode is formed on a SiO ₂ substrate. The lower electrode is made of TiN and its thickness is set to 100 nm. Subsequently, a buffer layer including TiON is formed through a thermal oxidation process for the lower electrode. The thickness of the buffer layer is about 5 nm. The thermal oxidation process for the formation of the buffer layer is carried out for about 5 minutes at a temperature of 900 ℃ in an atmospheric pressure atmosphere.

Subsequently, a resistance change layer is formed on the TiON buffer layer formed through the thermal oxidation process. The resistance change layer is made of TiO ₂ , and its thickness is set to 50 nm.

Subsequently, a patterned upper electrode is formed on top of the resistance change layer. The thickness of the upper electrode is set to 100 nm and consists of TiN.

In FIG. 7, the resistance change memory device is gradually applied from the negative voltage (−1.5 V to −2 V) to the positive voltage (1.5 V to −2 V) or gradually starts from the positive voltage (1.5 V to 1.8 V). Apply gradually to negative voltage (-1.5V ~ -2V).

First, a graph denoted by Δ represents the voltage and current characteristics of the resistance change memory device without the buffer layer. The device without the buffer layer refers to a device in which the thermal oxidation process for the lower electrode is not performed in the resistance change memory.

The current characteristic when a resistive change memory device without a buffer layer is applied from -2V to + 1.5V is represented by Δ. When a voltage of 0V to 1.5V is applied to a device having an initial high resistance state, it is changed from a high resistance state to a low resistance state at 1.5V. In addition, if the voltage is changed from 1.5V to -2V, it is changed to the low resistance state around -1.8V, and finally, at -2V, it is changed to the initial high resistance state. Through this, it can be seen that the resistance state of the resistance change layer is changed by the application of the characteristic voltages of the negative voltage and the positive voltage. At this time, the maximum value of the current during the switching operation is about 20mA.

The graph denoted by o indicates the voltage and current characteristics of the resistance change memory device having the 5 nm TiON buffer layer as described above. The resistance change memory device is applied a voltage from 1.8V to -1.5V and its characteristic is measured. Applying a negative voltage of -1.5V at 0V to the initial high resistance state changes from high resistance to low resistance state at -1.2V. Again, applying a positive voltage from -1.5V to 1.8V changes to a high resistance state around 1.5V, and finally changes to an initial high resistance state at 1.8V. At this time, the maximum value of the current appearing during the switching operation is 2mA to 3mA. Accordingly, it can be seen that the resistance change memory device having the buffer layer inserted therein can switch even with a current of about 1/10 of the current without the buffer layer.

The fabrication of the resistance change memory device according to the present invention described above has the advantage of simplifying the process because the lower electrode, the upper electrode and the inserted buffer layer and the resistance change layer are formed through a continuous process. In addition, in the case of using TiN or WN as the lower electrode, the buffer layer may be manufactured using a thermal oxidation method in which the lower electrode is manufactured without additional deposition and then heat treated in an oxygen atmosphere. This simplifies the process. In addition, the resistance change memory device according to the present invention reduces the amount of current consumed during the switching operation to less than 1/10 due to the insertion of the buffer layer. In addition, the insertion / buffer layer has the advantage that the set / reset voltage characteristics are stable compared to the film quality composed of conventional TiO ₂ alone.

100 substrate 110 lower electrode
120: buffer layer 130: resistance change layer
140: upper electrode

Claims (9)

Board;
A lower electrode formed on the substrate;
A resistance change layer formed on the lower electrode;
An upper electrode formed on the resistance change layer; And
And a buffer layer disposed between the resistance change layer and the two electrodes. The resistance change of claim 1, wherein the lower electrode comprises a nitride electrode material including at least one selected from the group consisting of Pt, Au, Al, Cu, Ti, and alloys thereof, or TiN or WN. Memory. The resistance change memory of claim 1, wherein the buffer layer is disposed between the resistance change layer and the lower electrode. The resistance change memory of claim 3, wherein the buffer layer comprises TiON, TaON, CoON, or WON. The resistance change memory of claim 4, wherein the buffer layer is formed through a thermal oxidation process for the lower electrode. The method of claim 1, wherein the resistance change layer is Ti oxide, Mg oxide, Ni oxide, Ce oxide, Zn oxide, Hf oxide, Co oxide, Ta oxide, Al oxide, La oxide, Nb oxide, SrTi oxide, Cr doped A resistance change memory comprising SrTi oxide or Cr doped SrZr oxide. Forming a lower electrode on the substrate;
Forming a buffer layer through a thermal oxidation process on the lower electrode;
Forming a resistance change layer on the buffer layer; And
And forming an upper electrode on the resistance change layer. The method of claim 7, wherein the thermal oxidation process,
And forming an oxynitride by modifying a surface of the lower electrode including a nitride electrode material. The method of claim 8, wherein the oxynitride comprises TiON, TaON, CoON, or WON.

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