KR20110116970A - Variable gate field effect transistor (FET) and electric and electronic device having the FET - Google Patents

Abstract

The variable gate field effect transistor (FET) according to the present invention and an electric and electronic device including the FET effectively solve the problem of reducing the source-drain current of the FET due to heat, and also reduce the temperature of the FET. An effect transistor (FET) and an electronic device having the FET are provided. The variable gate field effect transistor includes a field effect transistor (FET); And a gate control element attached to a surface or a heat generating portion of the FET and circuitally connected to a gate terminal of the FET to vary the voltage of the gate terminal. The voltage of the gate terminal is varied by a gate variable element to control the channel current between the source and the drain of the FET.

Description

Variable gate field-effect transistor (FET) and, electrical and electronic apparatus comprising the same FET}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to field effect transistors (FETs), and more particularly, to high efficiency and low heat generation FETs that can operate stably by varying the gate voltage of FETs using MIT devices or thermistor devices.

A typical switch among electronic components is a transistor, which is a three-terminal device. The transistors are classified into bipolar transistors using a pn junction principle and field effect transistors (FETs) using capacitors. High-speed signal amplification FETs are used for RF signal amplification, DC-DC converters, and DC switching devices at the front-end of electrical and electronic devices. It is pointed out that a typical problem of the FET is that the FET generates heat in the source-drain conductive layer during high-speed switching, and the heat is transferred to the gate insulator to reduce the channel current between the source and the drain.

Because of this problem, FETs are not capable of high-speed signal amplification. Accordingly, for high speed amplification of FETs, peripheral devices such as temperature sensors, memories, DA converters, and microprocessors for controlling these peripheral devices are required, and complex system concept programs are required to operate these peripheral devices. .

The problem to be solved by the present invention is to effectively solve the problem of the source-drain current reduction of the FET due to heat, and also to reduce the temperature of the FET, a variable gate field effect transistor (FET) and an electrical and electronic device having the FET Is in providing.

In order to solve the above problems, the present invention provides a field effect transistor (FET); And a gate control element attached to a surface or a heat generating portion of the FET and circuitally connected to a gate terminal of the FET to vary the voltage of the gate terminal. Provided is a variable gate field effect transistor in which the voltage of the gate terminal is varied by a gate variable element to control the channel current between the source and the drain of the FET.

In one embodiment of the present invention, the gate control device may include an MIT device that generates a sudden metal-insulator transition (MIT) at a critical temperature. The MIT device includes an MIT thin film that causes abrupt MIT at the critical temperature; And two electrode thin films contacting the abrupt MIT thin film, wherein one of the two electrode thin films is connected to the gate terminal, and the second electrode thin film is connected to a control voltage source or ground. Can be connected. A driving voltage source may be connected to a drain electrode of the FET, a driving device may be connected to a source electrode of the FET, and a gate voltage source and the MIT device may be commonly connected to a gate of the FET.

In one embodiment of the present invention, the gate control element may include a thermistor element whose resistance decreases with increasing temperature. One of two terminals of the thermistor element may be connected to a gate of the FET, and the other may be connected to a control voltage source or ground.

In one embodiment of the present invention, the FET and the gate control element may be packaged into one chip. In addition, the variable gate field effect transistor includes a heat transfer medium for transferring heat generated from the FET, the FET and the gate control element are respectively packaged, the packaged FET and the gate control element is the heat transfer medium. Can be combined to allow heat transfer.

Also, in order to solve the above problems, a drive element of the present invention; And at least one variable gate field effect transistor connected to the driving element to control a current supplied to the driving element.

In an embodiment of the present disclosure, the gate control device may include an MIT device in which an abrupt metal insulator transition (MIT) occurs at a critical temperature or a thermistor device whose resistance decreases with increasing temperature. Either one of the two terminals of the MIT device or thermistor element may be connected to the gate of the FET, and the other may be connected to a control voltage source or ground.

In one embodiment of the present invention, the variable gate field effect transistor is a plurality, each of the plurality of the FET of the variable gate field effect transistor is arranged in an array structure constituting a FET array element, the FET array element The gate control element may be connected to each FET.

In one embodiment of the present invention, the electrical and electronic device, the variable gate field effect transistor is used, RF signal amplification device, DC-DC switching device, power supply switching device, microprocessor for high-speed signal processing Switching element, switching element for power control of electronic devices, switching element for lithium ion charging, switching element for LED control, switching element for display pixel control, switching element for memory cell control, switching element for amplifying sound and voice signals in sound equipment, photo-relay And an optical switch.

A variable gate field effect transistor (FET) of the present invention and an electric and electronic device including the FET use a MIT element or a thermistor element to vary the voltage applied to the gate of the FET according to the heat generated in the FET, By increasing the current between the source-drain and lowering the temperature of the FET, the operation of the FET can be kept stable.

Accordingly, the variable gate field effect transistor (FET) of the present invention is a high speed, high power, and low heat switching device, and is a high speed signal in an RF signal amplification device, a DC-DC switching device, a power supply switching device, and a microprocessor. Switching element for processing, switching element for controlling power of electronic devices, switching element for charging lithium ion, switching element for controlling LED, switching element for controlling display pixel, switching element for controlling memory cell, switching element for amplifying sound and voice signals in acoustic equipment, photo It can be used in switching elements such as relays and optical switches, and can also be usefully used in all electric and electronic devices such as mobile phones, notebook computers, computers, memories, etc. including such switching elements.

1 is a basic circuit diagram illustrating the operation of an N-type field effect transistor (FET).
FIG. 2 is a graph showing the drain current I _{D versus} the source-drain voltage V _DS according to the gate voltage V _GS in the circuit of FIG. 1.
FIG. 3 is a graph showing the surface temperature T of the FET _versus the source-drain current I _DS according to the gate voltage V _GS in the circuit of FIG. 1.
4 is a circuit diagram of an electronic device including a variable gate FET according to an embodiment of the present invention.
5 is a circuit diagram of an electronic device including a variable gate FET according to an embodiment of the present invention.
6A-6B are cross-sectional views and plan views of MIT devices used in the variable gate FETs of FIGS. 4 or 5.
FIG. 7 is a graph showing resistance to temperature of an MIT device implemented using vanadium oxide (VO ₂ ).
8 is a modified circuit diagram of FIG. 4 used to measure the change in output voltage with respect to a sinusoidal input.
9A and 9B are signal waveform diagrams showing an input voltage and an output voltage measured in the circuit diagram of FIG. 8.
FIG. 10 is a graph showing the maximum minimum value of the output voltage according to the V _MIT change measured in the circuit diagram of FIG. 8.
FIG. 11 is a graph showing the maximum minimum value of the output voltage according to the change of R _MIT measured in the circuit diagram of FIG. 8.
12A and 12B are signal waveform diagrams showing an output voltage after passing through a capacitor in the circuit diagram of FIG. 8.
13 is a circuit diagram of an electronic device including a variable gate FET according to another embodiment of the present invention.
14 is a circuit diagram of an electronic device including a variable gate FET according to another embodiment of the present invention.
15A and 15B are cross-sectional views of thermistor elements used in the variable gate FETs in FIG. 13 or FIG.
16 is a graph showing resistance characteristics with respect to temperature of a thermistor element.
17 is a plan view illustrating a case in which a variable gate FET is packaged in one package according to an embodiment of the present invention.
18A and 18B are cross-sectional views and plan views illustrating a state in which a gate variable element and a FET of a variable gate FET are packaged and combined, respectively, according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, when an element is described as being present on top of another element, it may be directly on top of the other element, and a third element may be interposed therebetween. In the drawings, the thickness and size of each constituent element are exaggerated for convenience and clarity of description, and a portion not related to the description is omitted. Like numbers refer to like elements in the figures. It is to be understood that the terminology used is for the purpose of describing the present invention only and is not used to limit the scope of the present invention. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

1 is a basic circuit diagram illustrating the operation of an N-type field effect transistor (FET).

Referring to FIG. 1, in general, the field effect transistor 10 (hereinafter, referred to as 'FET') is a three-terminal switch, and adjusts a voltage applied from the gate voltage source V _G to the gate G, thereby controlling the source of the FET 10. By turning on and off the channel between (S) and the drain (D), it functions to supply the current from the driving voltage source (V _D ) to the driving element (not shown). The FET 10 is classified into an N-type FET and a P-type FET. In this figure, the N-type FET is shown.

The FET 10 applies a gate voltage to the gate and causes electric charges induced by the voltage to flow by the source-drain voltage to supply current to the driving device. This FET 10 can be used as a power FET by increasing the source-drain voltage to flow a large current. In addition, the FET 10 may be used as a high speed switching element for performing high speed switching by applying an appropriate gate voltage to a low source-drain voltage.

는 구동소자 대신 FET(10)에 연결시킨 전류계이다.However, the FET 10 generates heat in the source-drain channel layer during high-speed switching, and heat is transferred to the gate insulator to reduce the channel current between the source and the drain, thereby preventing malfunction of a driving device (not shown). cause. here,

Is an ammeter connected to the FET 10 instead of the driving element.

FIG. 2 is a graph showing the drain current I _D versus the source-drain voltage V _DS according to the gate voltage V _GS in the circuit of FIG. 1, which is obtained using an N-MOS IRF640 as a FET.

Referring to FIG. 2, as the source-drain voltage V _DS increases, the drain current I _D also increases. In addition, it can be seen that as the gate voltage V _GS increases, the rate of increase of the drain current I _D , that is, the slope of the graph increases. On the other hand, from the gate voltage of 5.5 V or higher, despite the increase in the gate voltage V _GS , the rate of increase of the drain current I _D becomes about the same. On the graph, when the source-drain voltage V _DS is about 3.7 V, the portion where the drain current I _D is 2A is indicated by an arrow.

3 is a graph showing the surface temperature (T) of the FET versus the source-drain current (I _DS ) according to the gate voltage (V _GS ) in the circuit of FIG. 1, which is also a graph obtained using N-MOS IRF640 as the FET to be. Here, the source-drain current I _DS may be regarded as the same as the drain current I _D of FIG. 2.

Referring to FIG. 3, it can be seen that as the source-drain current I _DS increases, the surface temperature T of the FET increases. In addition, the higher the gate voltage (V _GS ) can be seen that the surface temperature (T) graph moves to the right, which can be interpreted that the surface temperature of the FET can be lowered by increasing the gate voltage (V _GS ). have. In other words, when the black arrow is drawn along the X axis at about 70 ° C on the Y axis, the surface temperature T of the FET is constant despite the increase in the source-drain current I _DS according to the increase in the gate voltage V _GS . Do.

For example, in the graph A having a gate voltage V _GS of 5.0 V, the surface temperature of the FET may be 100 ° C. or higher at a portion where the source-drain current I _DS is about 2.0A. However, if the gate voltage (V _GS ) is increased (graphs with gate voltage (V _GS ) of 5.5V or more), the surface temperature of the FET decreases to about 60 ° C at the same 2.0A source-drain current (I _DS ). Can be. Meanwhile, in FIG. 2, in spite of the increase in the gate voltage V _GS from the gate voltage V _GS of 5.5 V or more, the increase rate of the drain current I _D does not increase. From the voltage (V _GS ), the surface temperature graph of the FET also remains almost similar without moving to the right.

Finally, based on the graph of FIG. 3, it can be seen that by increasing the voltage applied to the gate electrode of the FET, the source-drain current I _DS can be increased, and the surface temperature of the FET can be lowered as well. have.

4 is a circuit diagram of an electronic device including a variable gate FET according to an embodiment of the present invention.

Referring to FIG. 4, the electrical and electronic device of this embodiment may include a variable gate FET 1000 and a driving device 300. The variable gate FET 1000 may include a FET 100 and an MIT device 200 connected to the gate G of the FET 100.

The driving voltage source V _D may be connected to the drain D of the FET 100, and the driving device 300 may be connected to the source S. In addition, the gate voltage source V _G and the MIT device 200 may be connected to the gate G of the FET 100 through the contact A. One terminal of the MIT device 200 may be connected to the gate G of the FET 100, and the other terminal may be connected to a control voltage source V _MIT .

On the other hand, a resistor 400 for voltage drop and protection of the FET 100 may be connected between the drain D of the FET 100 and the driving voltage source V _D. Also, although not shown, a resistor may be connected between the gate voltage source V _G and the gate G, and the control voltage source V _MIT and the other terminal. Furthermore, of course, other resistive elements may be added or omitted to each required portion of the electrical and electronic device.

The MIT element 200 is a two-terminal element, and maintains its characteristics as an insulator below the critical temperature, and then rapidly transitions above the threshold temperature to have the characteristics as a metal. Specific structures and features of the MIT device 200 will be described in more detail later with reference to FIGS. 6A to 7.

Referring to the operation of the variable gate FET 1000 in the electrical and electronic device of the present embodiment,

As described above, when the FET 100 switches at high speed, heat accumulates in the source-drain channel layer, resulting in a reduction in the channel current of the source-drain channel. However, since the generated heat is transferred to the MIT device 200 and the MIT device 200 is transferred to the metal by heat, the voltage of the control voltage source V _MIT is transferred to the gate of the FET 100 through the contact A. G) is applied to raise the gate voltage of the FET 100.

As the gate voltage of the FET 100 rises, as shown in the graph of FIG. 3, the source-drain current increases. As a result, the current reduced by the heat generation is compensated for by the current increased by the increase of the gate voltage, so that there is no decrease in the substantial current supplied to the driving device 300, and thus the driving device 300 can be stably operated. have. On the other hand, with the increase in the source-drain current, the temperature of the source-drain channel layer also tends to decrease. This is the same principle as the temperature is kept constant despite the increase in the source-drain current with the increase in the gate voltage shown by the black arrow at 70 ° C on the Y axis, as explained in the graph of FIG.

In the designed circuit as shown in Figure 4, the experimentally measured results are shown in Table 1 below. Here, the IRF640 is used as the FET 100, and the resistance value of the resistance element 400 between the driving voltage source V _D and the FET 100 is 5 Ω, and a heat gun is applied to the MIT element 200. Heat was applied through.

V _G V _D I _DS V _MIT Tem. Remarks 4V 7 V 0.6 A 5 V
ΔV = 1V (voltage between V _MIT and contact (A)) 136 ℃ Before heating the MIT device 4.7 V 7 V 1.0A 70 ℃ After heating the MIT device

In Table 1, V _G represents the gate voltage of the FET 100, V _D represents the drain voltage of the FET 100, I _DS represents the source-drain current, and V _MIT represents the MIT device 200. Voltage of the control voltage source connected to Tem. Represents the surface temperature of the FET 100.

As can be seen from Table 1, before applying heat to the MIT device 200 through the heat gun, the surface temperature of the FET 100 was 136 ° C and the source-drain current was 0.6A. After applying heat to the MIT device 200, the gate voltage of the FET 100 rose from 4V to 4.7V, so that the source-drain current also rose from 0.6A to 1.0A, and also the FET 100 The surface temperature of was decreased from 136 ° C to 70 ° C. This result is exactly in accordance with the operating principle of the variable gate FET 1000.

On the other hand, based on the operating principle of the variable gate FET 1000 as described above, the MIT device 200 may be attached to the surface of the FET 100, or the heat generation well. For example, the MIT device 200 may be attached to a portion near the channel layer and the gate electrode of the FET 100 where heat is generated so that the generated heat can be effectively transferred.

5 is a circuit diagram of an electronic device including a variable gate FET according to an embodiment of the present invention.

Referring to FIG. 5, the electrical and electronic device of this embodiment has a structure similar to the electrical and electronic device of FIG. 4, but only a portion of the MIT device 200 is different. That is, one terminal of the MIT device 200 may be connected to the gate G of the FET 100 through the contact A, and the other terminal may be connected to the ground rather than the control voltage source.

As such, by connecting ground to the MIT device 200, the source-drain current of the FET 100 may be reduced. For example, through the structure as shown in FIG. 4, after the source-drain current is increased, it is necessary to reduce the source-drain current by connecting ground to the MIT element 200 when it is necessary to reduce the source-drain current. Can be.

Meanwhile, although the circuit structure in which one MIT device is connected to one FET has been described so far, the present invention is not limited thereto, and the variable gate FET of the embodiment of the present invention includes a FET array device having a plurality of FETs arranged in an array structure. It goes without saying that the MIT device can be extended to a circuit structure in which one MIT device is connected to each FET in the FET array device.

6A to 6B are cross-sectional views and a plan view of an MIT device used in the variable gate FET of FIG. 4 or 5, and FIG. 6A is a cross-sectional view of an MIT device 200 having a stacked structure, and FIG. 6B is a horizontal structure. 6 is a plan view of the horizontal MIT device of FIG. 6B.

Referring to FIG. 6A, the stacked MIT device 200 may include a substrate 210, a buffer layer 220, a transition thin film 230, and an electrode thin film 240.

The substrate 210 is doped with Si, SiO ₂ , GaAs, Al ₂ O ₃ , plastic, glass, V ₂ O ₅ , PrBa ₂ Cu ₃ O ₇ , YBa ₂ Cu ₃ O ₇ , MgO, SrTiO ₃ , Nb SrTiO ₃ And a silicon on insulator (SOI).

The buffer layer 220 is formed on the substrate 210 and serves to mitigate lattice mismatch between the substrate 210 and the first electrode thin film 241. When the lattice mismatch between the substrate 210 and the first electrode thin film 241 is very small, the buffer layer 220 may be omitted. The buffer layer 220 may include a SiO ₂ or Si ₃ N ₄ film.

The electrode thin film 240 may include a first electrode thin film 241 and a second electrode thin film 243 below the transition thin film 230. The first electrode thin film 241 may be formed on the buffer layer 220, and in the case of the buffer layer 220, may be directly formed on the substrate 210. Electrode thin film 240 is W, Mo, W / Au, Mo / Au, Cr / Au, Ti / W, Ti / Al / N, Ni / Cr, Al / Au, Pt, Cr / Mo / Au, YBa ₂ Cu ₃ O _{7 -d} , Ni / Au, Ni / Mo, Ni / Mo / Au, Ni / Mo / Ag, Ni / Mo / Al, Ni / W, Ni / W / Au, Ni / W / Ag and It may be formed including at least one material of Ni / W / Al. The electrode thin film 240 may be formed using at least one deposition method among sputter deposition, vacuum deposition, and E-beam deposition.

The transition thin film 230 may be formed on the first electrode thin film 241. The transition thin film 230 may include inorganic compound semiconductors and insulators having low concentrations of holes including oxygen, carbon, semiconductor elements (Groups III-V, II-VI), transition metal elements, rare earth elements, and lanthanide elements, At least one of an organic semiconductor and an insulator to which holes of low concentration are added, a semiconductor to which holes of low concentration are added, and an oxide semiconductor and an insulator to which holes of low concentration are added may be included. Here, the concentration of the added holes is about 3 x 10 ¹⁶ cm ^-3 . In addition, the transition thin film 230 may be formed of an n-type semiconductor and an insulator having a very large resistance.

The MIT device 200 rapidly changes its electrical characteristics in response to various physical characteristics such as voltage, temperature, and electromagnetic waves. For example, below the threshold temperature, the MIT device 200 exhibits the characteristics of an insulator, and a discontinuous MIT occurs above the threshold temperature to have the properties of a metallic material.

Referring to FIG. 6B, similar to the stacked MIT device 200, the horizontal MIT device 200a may include a substrate 210, a buffer layer 220, a transition thin film 230a, and an electrode thin film 240a. .

The transition thin film 230a is formed on the buffer layer 220, and may be directly formed on the substrate 210 when the lattice mismatch with the substrate 210 is small. In addition, the first electrode thin film 241a and the second electrode thin film 243a of the electrode thin film 240a may be formed on the buffer layer 220, and may be formed to face both sides of the transition thin film 230a. In addition, the first electrode thin film 241a and the second electrode thin film 243a may be formed to cover a portion of the upper surface of the transition thin film 230a as shown.

Meanwhile, materials of the substrate 210, the buffer layer 220, the transition thin film 230a and the electrode thin film 240a of the horizontal MIT device 200a may be formed of the same material as described with reference to FIG. 6A.

Referring to FIG. 6C, a buffer layer 220, a transition thin film 230a, and first and second electrode thin films 241a and 243a of the horizontal MIT device 200a are illustrated. As shown, in the horizontal MIT device 200a, each of the first electrode thin film 241a and the second electrode thin film 243a may have a first width W, and the first electrode thin film 241a may also be used. The second electrode thin film 243a may have a first gap d.

The stacked or horizontal MIT devices 200 and 200a can be made compact in micrometer (μm) units and can be manufactured at a very low cost in terms of economy. In addition, the MIT devices 200 and 200a may change the critical temperature by a change in the structure itself, for example, by changing the first interval d or the first width W of the electrode thin film in FIG. 6C.

FIG. 7 is a graph showing a resistance characteristic of a MIT device made of vanadium dioxide (VO ₂ ) with respect to temperature. A predetermined voltage is applied to the MIT device.

Referring to FIG. 7, an MIT device exhibits characteristics as an insulator having a resistance value of 10 ⁵ Ω or more at less than 340 K, and exhibits characteristics as a metal having a resistance value of several tens of Ω due to a rapid discontinuous transition at 340 K or more. Referring to this graph, the MIT device used in the experiment has a discontinuous MIT at 340K, so the critical temperature can be viewed as about 340K.

Although not shown in the figure, in the case of the graph of the voltage-current curve of the MIT device, it can be seen that the current rapidly increases through the discontinuous jump and the voltage decreases at the critical temperature. Although MIT generation according to temperature has been described here, in general, MIT devices may generate MIT due to various physical characteristics such as pressure, voltage, electric field, and electromagnetic wave in addition to temperature. However, since there is a distance from the gist of the present invention, a detailed description of MIT generation due to other physical characteristics is omitted.

On the other hand, the MIT device used in this experiment was fabricated using the MIT thin film formed of VO ₂ , but is not limited to VO ₂ , MIT using a new material or material that can have a discontinuous jump characteristic by various physical properties. Of course, a thin film can be produced. The MIT thin film can also be produced in the form of a ceramic thin film or a single crystal thin film.

8 is a modified circuit diagram of FIG. 4 used to measure a change in output voltage with respect to a sinusoidal input, in which an input voltage V _IN is applied to a gate terminal V _G connected to one terminal of a capacitor, and a drain terminal of the FET. The first output voltage V _OUT1 is measured at, and the second output voltage V _OUT2 at the other terminal of the capacitor C1 is measured.

Referring to FIG. 8, in the variable gate FET used in this experiment, a capacitor C1 is connected to the gate of the FET to form an RC circuit. This RC circuit may be the same circuit as that of FIG. 4 except for the capacitor C1. Meanwhile, the FET used may be a metal oxide semiconductor (MOS) FET, for example, KTK919S.

In such an RC circuit, a 15 MHz high frequency sine wave is applied to the gate terminal V _G as an input voltage V _IN , and the change of the resistance R _MIT of the MIT device and the voltage applied to the MIT device ( Observe two output waveforms for the first output voltage V _{OUT1 as the} V _MIT ) changes. Also, at the other end of the capacitor, the output waveform of the second output voltage V _OUT2 according to the change of the resistance R _MIT of the MIT device is observed.

The RC circuit is regarded as a high-pass filter, and according to the following equation (1), the ratio of the output voltage to the input voltage becomes large at high frequency.

, (ω=2πf)...........................식(1)

, (ω = 2πf) ........................ Equation (1)

Table 2 shows the first output voltage V _OUT1 when the voltage V _MIT applied to the MIT device is changed in the RC circuit diagram of FIG. 8.

V _G (V) = 5sin2πft V _D (V) Freq.
(Mhz) C (pF) R ₁
(Ω) R _MIT (Ω) V _MIT (V) V _OUT1 ( mV ) Max . Min . 5 4 15 10 10k Do not connect Do not connect +230 -230 5 4 15 10 10k 30 0 500 -500 5 4 15 10 10k 30 0.6 650 -650 5 4 15 10 10k 30 1.0 700 -650 5 4 15 10 10k 30 2.0 800 -700 5 4 15 10 10k 30 4.0 900 -700

In Table 2, V _G represents the voltage applied to the gate terminal, V _D represents the voltage applied to the drain terminal of the FET, Freq. Is the frequency of the input voltage, the unit is Mhz, and C is the capacitance of the capacitor C1. It represents capacitance, and R1 represents a resistance value of the resistor element R1 connected to the drain terminal of the FET.

Analyzing Table 2,

a. The first output voltage (V _OUT1 ) before V _MIT is applied is 230 mV After the V _MIT is applied, the first output voltage (V _OUT1 ) increases up to 900 mV, so that the first output voltage before V _MIT is applied. It is amplified by 2 ~ 4 times the output voltage (V _OUT1 ).

b. An offset is generated in the positive sine wave after the V _MIT voltage of 1 V or more is applied. First maximum value of the output voltage (V _OUT1) is but rises as the voltage rise of the V _MIT, the minimum value is constant at least from -700mV _MIT V = 2V.

9A and 9B are signal waveform diagrams showing input voltages and output voltages measured in the circuit diagram of FIG. 8, and FIG. 9A is a waveform diagram of a first output voltage when the MIT device is not connected. FIG. 9B is a MIT device. Is a waveform diagram of a first output voltage when a voltage of 4V is applied.

The waveform diagram of FIG. 9A shows a case where the topmost condition of Table 2, that is, the input voltage V _IN is 5sin2πft and R _MIT and V _MIT are not connected. In this case, it can be seen that the first output voltage is very small, about 230 mV. Meanwhile, ch1 5V in the lower part of FIG. 9A means that the unit of scale on the graph of the input voltage portion is 5V, and ch2 200mV means that the unit of scale of the output voltage portion is 200mV.

The waveform diagram of FIG. 9B shows a case where the lowermost condition of Table 2, namely, the input voltage V _IN is 5sin2πft, the R _MIT is 30 Hz and the V _MIT is 4V. In this case, it can be seen that the first output voltage increases by about 900 mV, and also, an offset of about 200 mV occurs with a minimum value of -700 mV. As a result, it can be seen that as the V _MIT increases, the first output voltage is amplified than before the V _MIT connection. For example, when the V _MIT is 4V, the first output voltage is amplified by about four times compared to before the V _MIT connection.

FIG. 10 is a graph showing the maximum minimum value of the first output voltage V _OUT1 according to the V _MIT change measured in the circuit diagram of FIG. 8.

As can be seen from FIG. 10, the first output voltage at the portion where the V _MIT is not connected is shown, and as the V _MIT increases, the first output voltage may increase. On the other hand, in terms of the maximum value and the minimum value of the first output voltage, the first output voltage continues to increase as V _MIT increases, but the minimum value may be constant to -700mV from V _MIT = 2V or more. . Accordingly, it can be seen that the offset generated from V _MIT = 1 V or more continues to increase.

The first output voltage V _OUT1 according to the change of R _MIT measured in the circuit diagram of FIG. 8 is shown in Table 3.

V _G (V) = 5sin2πft V _D (V) Freq.
(Mhz) C (pF) R ₁ (Ω) R _MIT (Ω) V _MIT (V) V _OUT1 ( mV ) Max . Min . 5 4 15 10 5k 30 4 900 -700 5 4 15 10 5k 10k 4 620 -520 5 4 15 10 5k 50k 4 500 -450 5 4 15 10 5k 100k 4 450 -400

The meanings of the variables shown in Table 3 are the same as described in Table 1.

Analyzing Table 3,

a. As the resistance of R _MIT increases, the first output voltage V _OUT1 decreases. That is, the amplification is not good.

b. R _MIT = 30Ω, the maximum value of V _OUT1 and the absolute value of the difference between the minimum value is 200mV. In other words,

│900│-│-700│ = 200 [mV]

c. At R _MIT = 100kΩ, the offset between the maximum and minimum values of V _OUT1 is 50mV and the offset decreases as the resistance increases. In other words,

│450│-│-400│ = 50 [mV]

FIG. 11 is a graph showing the maximum minimum value of the first output voltage V _OUT1 according to the change of R _MIT measured in the circuit diagram of FIG. 8.

Referring to FIG. 11, it can be seen that when R _MIT = 30 μs, the offset of the first output voltage is the largest at 200 mV, and when the R _MIT = 100 k μs, the offset of the first output voltage is reduced to 50 mV. . It is expected that the offset of the first output voltage decreases as the R _MIT increases based on the slope of the graph, and the offset disappears from a certain value.

12A and 12B are signal waveforms illustrating the second output voltage V _OUT2 after passing through a capacitor in the circuit diagram of FIG. 8, except for R _MIT , experimental conditions such as input voltage and frequency are shown in Table 3. The same applies as in the first output voltage measurement.

FIG. 12A illustrates a second output voltage V _OUT2 in a region of 120 mA ≤ R _MIT ≤ 200 mA. It can be seen that a DC component is added to the second output voltage V _OUT2 , which is an output waveform after passing through a capacitor. For example, it can be seen that a DC voltage of about 0.5V is added (the base voltage is increased). This is presumably due to voltage application from the MIT element.

FIG. 12B shows the second output voltage V _OUT2 in the resistance region other than the region of 120 mA ≤ R _MIT ≤ 200 mA, where a DC component is also added. The added DC voltage is measured above 0.5V. Here, ch1 5V means that the interval of the scale of the input voltage portion is 5V, ch2 1V means that the interval of the scale of the output voltage portion is 1V.

On the other hand, through the comparison of the input voltage and the second output voltage of Figure 12a and 12b, after passing through the capacitor it can be seen that the output signal is reduced by 7 to 8 times the input signal. In addition, if the DC voltage addition is not taken into account, in the region of 120 mA? R _MIT ? 200 mA, the least offset occurs.

The conclusions of the first and second output voltage measurement experiments through the circuit diagram of FIG. 8 up to now are as follows.

a. As a result of varying the voltage and resistance applied to the MIT device in the RC high frequency circuit, the first output voltage is higher than that of the circuit consisting of only R-C.

b. The maximum first output voltage (900mV) is shown at V _MIT = 4V. These results show that the first output voltage is about four times higher than without V _MIT applied.

c. As R _MIT increases, the first output voltage drops but the offset decreases.

d. The minimum offset occurs when the resistance of the MIT device is 120 Ω ≤ R _MIT ≤ 200 Ω.

In addition, in this experiment, the input voltage was used as a high frequency sinusoidal wave of 15 MHz, but the same result is expected for the RF signal.

13 is a circuit diagram of an electronic device including a variable gate FET according to another embodiment of the present invention.

Referring to FIG. 13, the electronic device of the present embodiment may include a variable gate FET 1000a and a driving device 300 similarly to the electronic device of FIG. 4. However, the variable gate FET 1000a is different from the variable gate FET 1000 in FIG. That is, the variable gate FET 1000a according to the present embodiment may include a FET 100 and a thermistor element 500 connected to the gate G of the FET 100.

The thermistor element 500 in the present embodiment may perform the same function as the MIT element 200 in the electrical and electronic device of FIG. 4. Accordingly, the device connection structure of the variable gate FET 1000a in this embodiment is the same as that of the variable gate FET 1000 in FIG.

That is, the driving voltage source V _D is connected to the drain D of the FET 100, and the driving element 300 is connected to the source S. In addition, the gate voltage source V _G and thermistor element 500 are connected to the gate G of the FET 100 through the contact A. One terminal of the thermistor element 500 is connected to the gate G of the FET 100, and the other terminal is connected to the control voltage source V _Th . Furthermore, a resistive element 400 can be connected between the drain D of the FET 100 and the drive voltage source V _D , and other resistive elements can be added or omitted to each required portion of the electrical and electronic device. .

Thermistor element 500 is a two-terminal or three-terminal element, and the resistance of the thermistor element 500 decreases with increasing temperature. Specific structures and features of the thermistor element 500 will be described in more detail in the description of FIGS. 15A and 15B.

The operating principle of the variable gate FET 1000a in the electric and electronic device of this embodiment is similar to that of the variable gate FET 1000 in the electric and electronic device of FIG.

In other words, while the heat is generated by the fast switching of the FET 100, the channel current of the source-drain is reduced. However, heat generated at this time is transferred to the thermistor element 500, and the resistance of the thermistor element 500 decreases due to heat, so that the voltage of the control voltage source V _Th is applied to the gate of the FET 100 through the contact A. G) is applied to raise the gate voltage of the FET 100. In the case of the MIT element 200, however, a voltage almost equal to the voltage of the control voltage source V _MIT is applied to the gate of the FET 100. However, in the case of the thermistor element 500, the control voltage source ( A voltage obtained by subtracting the voltage drop corresponding to the resistance value after the resistance decrease from the voltage of V _Th ) is applied to the gate of the FET 100.

As a result, as described above, the source-drain current increases due to the increase in the gate voltage of the FET 100, and the temperature of the source-drain channel layer decreases due to the increase in the source-drain current.

14 is a circuit diagram of an electronic device including a variable gate FET according to another embodiment of the present invention.

Referring to FIG. 14, the electrical and electronic device of this embodiment has a structure similar to the electrical and electronic device of FIG. 13, but differs only in the thermistor element 500. That is, one terminal of the thermistor element 500 may be connected to the gate G of the FET 100 through the contact A, and the other terminal may be connected to the ground. By connecting ground to the thermistor element 500 in this manner, the source-drain current of the FET 100 can be reduced. This is the same as the reason or principle of applying the ground voltage to the MIT device 200 in the circuit for the electrical and electronic device of FIG. 5.

On the other hand, the variable gate FET using a thermistor thin film can be extended to a circuit structure in which one thermistor element is connected to each FET in the FET array element, like the variable gate FET using the MIT element.

Hereinafter, when describing the variable gate FET, the MIT element 200 and the thermistor element 500 are collectively referred to as a 'gate control element' for convenience of description.

15A and 15B are cross-sectional views of a thermistor element used in the variable gate FET in FIG. 13 or 14, FIG. 15A is a cross-sectional view of a two-terminal thermistor element, and FIG. 15B is a cross-sectional view of a three-terminal thermistor element.

Referring to FIG. 15A, the two-terminal thermistor element 500 may include a substrate 510, a thermistor thin film 520, and an electrode thin film 530.

The substrate 510 may be an insulating substrate or a semiconductor substrate such as silicon.

The thermistor thin film 520 is formed on the substrate 510 and has a negative temperature coefficient (NTC) characteristic. NTC characteristics will be described in the graph section of FIG. 16. For example, the thermistor thin film 20 may be composed of a group III + V semiconductor, a group II + VI semiconductor, a graphene and carbon nanotube, a carbon compound, a pn junction diode such as a pn junction Si, V ₂ O ₅ , p-type GaAs, And a semiconductor thin film including p-type Ge and the like.

The thermistor thin film 520 is formed between the first electrode thin film 531 and the second electrode thin film 533. In the planar structure, the first and second electrode thin films 531 and 533 have a rectangular band shape. The structure may be connected to each other, or may be formed to be connected in parallel between the first and second electrode thin films 531 and 533 in the form of at least two rectangular bands.

The electrode thin film 530 is an electrode for applying a voltage to the thermistor thin film 520 and may include a first electrode thin film 531 and a second electrode thin film 533. The first electrode thin film 531 and the second electrode thin film 533 may be formed on the substrate 510 to face each other on both sides of the thermistor thin film 520. As illustrated, the first electrode thin film 531 and the second electrode thin film 533 may be formed to cover a part of the upper surface of the thermistor thin film 520.

Referring to FIG. 15B, the three-terminal thermistor element 500a may include a substrate 510, a thermistor thin film 520, an electrode thin film 530, and a heat dissipating thin film 540. That is, unlike the two-terminal thermistor element 500 of FIG. 15A, the thermistor element 500a of the present embodiment further includes a heat dissipation thin film 540 under the substrate 510.

As a terminal for dissipating the thermistor element 500a of the heat dissipation thin film 540, the heat dissipation thin film 540 may be formed of a metal material having good heat transfer on the entire lower surface of the substrate 510. By dissipating heat through the heat dissipation thin film 540, malfunction of the thermistor element 500a due to its own temperature rise may be prevented.

Although not shown, thermistor elements 500 and 500a may include a buffer layer (not shown) formed on the substrate 510 to mitigate lattice mismatch between the substrate 510 and the thermistor thin film 520. have. In addition, thermistor elements 500 and 500a may include an electrode thin film 530 and an thermistor protective insulating film (not shown) formed on the thermistor thin film 520 to protect the thermistor thin film 520.

16 is a graph showing resistance characteristics with respect to temperature of a thermistor element.

Referring to FIG. 16, a graph A of resistance against temperature of a thermistor element, more specifically the thermistor thin film, decreases exponentially with increasing temperature as shown. In this way, a thermistor whose resistance decreases with increasing temperature is called a negative temperature coefficient (NTC) thermistor.

Such a thermistor thin film having NTC characteristics may be formed of a Be-doped GaAs thin film. However, the film is not limited to the Be-doped GaAs thin film, and any kind of material thin film having NTC characteristics may be used for thermistor device fabrication. For example, a pn junction portion between a base-emitter of a pn junction diode or a transistor may be used as a thermistor element.

The variable gate FET having the gate control element of the present embodiments described above is a high speed, high power, and low heat switching element, and is an RF signal amplification element, a DC-DC switching element, a power supply switching element, and a high speed in a microprocessor. Switching element for signal processing, switching element for controlling power of electronic devices, switching element for charging lithium-ion, switching element for controlling LED, switching element for controlling display pixels, switching element for controlling memory cells, switching element for amplifying sound and voice signals in acoustic devices, It can be used for switching elements such as photo-relays and optical switches. In addition, it can be usefully used in all electrical and electronic devices such as mobile phones, notebook computers, computers, memory, including such switching elements.

17 is a plan view illustrating a state in which the variable gate FET is one-chip in one package according to an embodiment of the present invention.

Referring to FIG. 17, the variable gate FETs 1000, 1000a in the electrical and electronic devices of FIGS. 4, 5, 13, and 14, ie, the FET 100 and the gate control elements 200, 500, are packaged as shown. It can be one chip (2000). In the one-chip structure package 2000, the gate control elements 200 and 500 may be disposed at portions where heat of the FET 100 is likely to occur.

Exposed pins 1-8 of the one-chip structure package 2000 connect the terminals of the devices connected to the variable gate FETs 1000, 1000a in the electrical and electronic devices of FIGS. 4, 5, 13, and 14. Can be used for On the other hand, the arrangement or number of the pins of the one-chip structure package 2000 may be changed.

18A and 18B are cross-sectional and plan views illustrating another package structure of the variable gate FET according to an embodiment of the present invention.

Referring to FIG. 18A, unlike the one-chip structure package 2000 of FIG. 17, the package structure of the gate variable transistors 1000 and 1000a according to the present exemplary embodiment is the FET 100 and the gate constituting the variable gate FETs 1000 and 1000a. The control elements 200 and 500 may be packaged and coupled to each other.

The second package 4000 in which the gate control elements 200 and 500 are packaged may be coupled to the first package 3000 in which the FET 100 is packaged through the heat transfer medium 3500. The heat transfer medium 3500 may be formed of a material that efficiently transfers heat generated from the FET 100 to the gate control elements 200 and 500, for example, a material having high thermal conductivity. In addition, in order to improve operating performance of the gate control elements 200 and 500, the second package 4000 may be combined into a portion where heat is generated on the first package 3000.

Referring to FIG. 18B, the FET 100 may be disposed in the first package 3000, and the second package 4000 may be disposed on the dotted line B of the ellipse, which is a heat generating portion. Although not shown because of the plan view, the heat transfer medium 3500 may be present between the first package 3000 and the second package 4000.

While the present invention has been described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. will be. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

100: FET 200, 200a: MIT device
210: substrate 220: buffer
230, 230a: MIT thin film 240, 240a: electrode thin film
241 and 241a: first electrode thin film 243 and 243a: second electrode thin film
300: drive element 400: resistance element
500, 500a: thermistor element 510: substrate
520: thermistor thin film 530: electrode thin film
531: first electrode thin film 533: second electrode thin film
540: heat dissipation thin film 1000, 1000a: gate variable transistor
2000: one-chip structure package 3000: first package
3500: heat transfer medium 4000: second package

Claims (19)

Field Effect Transistors (FETs); And
A gate control element attached to a surface or a heat generating portion of the FET, and electrically connected to a gate terminal of the FET to vary a voltage of the gate terminal;
And a gate voltage of the gate terminal is changed by the gate variable element when the FET rises above a predetermined temperature, thereby controlling the channel current between the source and the drain of the FET. The method according to claim 1,
The gate control element,
A variable gate field effect transistor comprising an MIT device in which an abrupt Metal-Insulator Transition (MIT) occurs at a critical temperature. The method of claim 2,
The MIT device includes an MIT thin film that causes abrupt MIT at the critical temperature; And
And at least two electrode thin films contacting the abrupt MIT thin film.
The MIT device may be a stacked type in which two electrode thin films are stacked up and down with the MIT thin film interposed therebetween, or horizontally in which two electrode thin films are disposed on both sides of the MIT thin film. Variable gate field effect transistor. The method of claim 2,
The MIT device includes an MIT thin film that causes abrupt MIT at the critical temperature;
And two electrode thin films contacting the abrupt MIT thin film.
The first electrode thin film, which is one of two electrode thin films, is connected to the gate terminal, and the other second electrode thin film is connected to a control voltage source or ground. The method of claim 4, wherein
When the FET rises above the threshold temperature,
And the control voltage source or ground voltage is applied to the gate terminal as the MIT thin film transitions from an insulator to a metal. The method of claim 4, wherein
A driving voltage source is connected to the drain electrode of the FET.
A driving element is connected to the source electrode of the FET,
And a gate voltage source and the MIT device are commonly connected to the gate of the FET. The method according to claim 1,
The gate control element,
A variable gate field effect transistor comprising a thermistor element whose resistance decreases with increasing temperature. The method of claim 7, wherein
Wherein one of two terminals of the thermistor element is connected to a gate of the FET, and the other is connected to a control voltage source or ground. The method according to claim 1,
The FET is N type or P type,
The FET includes one of an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor (MOS) transistor. The method according to claim 1,
And the FET and the gate control element are packaged into one chip. The method according to claim 1,
The variable gate field effect transistor includes a heat transfer medium that transfers heat generated from the FET,
The FET and the gate control element are respectively packaged, and the packaged FET and the gate control element are coupled for heat transfer through the heat transfer medium. Drive elements; And
And at least one variable gate field effect transistor connected to the driving element to control a current supplied to the driving element. The method of claim 12,
And the gate control device comprises an MIT device in which an abrupt metal insulator transition (MIT) occurs at a critical temperature. The method of claim 13,
The gate control element,
The MIT device includes an MIT thin film that causes abrupt MIT at the critical temperature;
And two electrode thin films contacting the abrupt MIT thin film.
The first electrode thin film, which is one of two electrode thin films, is connected to the gate terminal, and the other second electrode thin film is connected to a control voltage source or ground. The method of claim 14,
A driving voltage source is connected to the drain electrode of the FET.
The driving device is connected to the source electrode of the FET,
And a gate voltage source and the MIT device are commonly connected to the gate of the FET. The method of claim 12,
The gate control element,
An electrical and electronic device comprising a thermistor element whose resistance decreases with increasing temperature. The method of claim 16,
Any one of two terminals of the thermistor element is connected to a gate of the FET, and the other is connected to a control voltage source or ground. The method of claim 12,
The variable gate field effect transistor is a plurality,
And wherein each of the FETs of the plurality of variable gate field effect transistors is arranged in an array structure to form a FET array element, and the gate control element is connected to each FET of the FET array element. The method of claim 12,
The electrical and electronic device,
RF signal amplification element, DC-DC switching element, switching element for power supply, switching element for high-speed signal processing of microprocessor, switching element for power control of electronic devices, lithium ion charging, in which the variable gate field effect transistor is used A switching element, a switching element for controlling an LED, a switching element for controlling a display pixel, a switching element for controlling a memory cell, a switching element for amplifying sound and voice signals in an acoustic device, a photo-relay, and an optical switch. Electronics.

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