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KR20110097474A - Memory chips and multichip packages containing them - Google Patents

Memory chips and multichip packages containing them Download PDF

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KR20110097474A
KR20110097474A KR1020100017334A KR20100017334A KR20110097474A KR 20110097474 A KR20110097474 A KR 20110097474A KR 1020100017334 A KR1020100017334 A KR 1020100017334A KR 20100017334 A KR20100017334 A KR 20100017334A KR 20110097474 A KR20110097474 A KR 20110097474A
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memory chip
cell array
memory cell
disposed
memory
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이상범
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주식회사 하이닉스반도체
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
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    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
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    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2924/1434—Memory
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract

멀티칩 패키지는 패키지기판상에 배치된 제1 메모리칩 및 상기 제1 메모리칩 상에 배치되고, 최와곽에 얼라인키가 위치하는 제2 메모리칩을 포함한다.The multichip package includes a first memory chip disposed on a package substrate and a second memory chip disposed on the first memory chip and having an alignment key at an outermost edge thereof.

Description

메모리칩 및 그를 포함하는 멀티칩 패키지{MEMORY CHIP AND MULTI CHIP PAKAGE INCLUDING THE SAME}MEMORY CHIP AND MULTI CHIP PAKAGE INCLUDING THE SAME}

본 발명은 메모리칩 및 그를 포함하는 멀티칩 패키지에 관한 것이다. The present invention relates to a memory chip and a multichip package including the same.

오늘날 반도체 산업은 반도체 소자를 소형화하는 것에 초점을 맞춰 발전하고 있다. 특히, 반도체 소자의 소형화는 패키지 공정에서 두드러지는데, 패키지란 미세회로가 설계된 집적회로, 즉 메모리칩(memory chip)을 전자기기에 실장하여 사용할 수 있도록 플라스틱 수지나 세라믹으로 봉한 것을 의미한다.Today, the semiconductor industry is developing with a focus on miniaturizing semiconductor devices. In particular, the miniaturization of semiconductor devices is prominent in the packaging process, which means that an integrated circuit designed for a microcircuit, that is, a memory chip is sealed with a plastic resin or ceramic so as to be mounted on an electronic device.

기존에는 패키지 한 개가 한 개의 메모리칩을 내장하였으나, 최근에는 패키지 한 개가 복수의 메모리칩을 내장하여 단위면적당 패키지 차지하는 면적을 최소화하고 있다. 이와 같이, 패키지 한 개가 복수의 메모리칩을 내장하고 있는 것을 멀티칩 패키지(multi chip pakage)라고 한다.Conventionally, one package has one memory chip, but recently, one package has a plurality of memory chips, thereby minimizing an area of the package per unit area. In this way, a package containing a plurality of memory chips is called a multi chip package.

도 1 내지 도 4는 종래기술에 따른 멀티칩 패키지의 제조 방법을 나타낸 도면이다. 여기서, 도 2 및 도 4는 각각 도 1 및 도 3의 Ⅰ-Ⅰ' 절단면을 나타낸 단면도이다.1 to 4 are diagrams illustrating a method of manufacturing a multichip package according to the prior art. 2 and 4 are cross-sectional views illustrating the cut planes II ′ of FIGS. 1 and 3, respectively.

도 1 및 도 2에 도시된 바와 같이, 볼(2)이 형성된 패키지기판(1) 상에 제1 접착층(3)과 제1 메모리칩(4)과 제2 접착층(5) 및 제2 메모리칩(6)을 적층시킨다.1 and 2, the first adhesive layer 3, the first memory chip 4, the second adhesive layer 5, and the second memory chip on the package substrate 1 on which the balls 2 are formed. (6) is laminated.

볼(2)은 멀티칩 패키지와 모듈을 연결하기 위한 리드(lead)와 와이드본딩(wire bonding)되는 금속패턴이다.The ball 2 is a metal pattern that is wire-bonded with a lead for connecting a multichip package and a module.

제1 접착층(3)은 패키지기판(1)과 제1 메모리칩(4)을 접착하기 위한 박막이고, 제2 접착층(5)은 제1 메모리칩(4)과 제2 메모리칩(6)을 접착하기 위한 박막이다.The first adhesive layer 3 is a thin film for bonding the package substrate 1 and the first memory chip 4 to each other, and the second adhesive layer 5 connects the first memory chip 4 and the second memory chip 6 to each other. Thin film for bonding.

제1 및 제2 메모리칩(4, 6)은 데이터를 저장하는 반도체 메모리 장치를 의미한다. 이중, 제2 메모리칩(6)은 기판(미도시)과 메모리셀 어레이(61)와 패드(62) 및 전원배선(63)으로 구성된다. 메모리셀 어레이(61)는 데이터를 저장하기 위한 메모리셀의 군집영역으로서, 기판의 중앙에 배치된다. 패드(62)는 볼(2)과 연결되어 신호를 입력받거나 출력하는 금속패턴으로서, 기판의 일측 가장자리에 배치된다. 전원배선(63)은 외부에서 인가받은 전원 또는 내부에서 생성한 전원을 필요로하는 장치에 전달하기 위한 금속배선으로서, 기판의 타측 가장자리에 배치된다.The first and second memory chips 4 and 6 refer to semiconductor memory devices that store data. The second memory chip 6 includes a substrate (not shown), a memory cell array 61, a pad 62, and a power supply wiring 63. The memory cell array 61 is a cluster area of memory cells for storing data, and is disposed at the center of the substrate. The pad 62 is a metal pattern connected to the ball 2 to receive or output a signal, and is disposed at one edge of the substrate. The power wiring 63 is a metal wiring for transferring the power applied from the outside or the power generated therein and is disposed at the other edge of the substrate.

도 3 및 도 4에 도시된 바와 같이, 패키지기판(1) 상에 제1 접착층(3)과 제1 메모리칩(4)과 제2 접착층(5)과 제2 메모리칩(6)을 순차적으로 적층시킨 후, 압착공정을 진행하여 멀티칩 패키지를 완성한다.As shown in FIGS. 3 and 4, the first adhesive layer 3, the first memory chip 4, the second adhesive layer 5, and the second memory chip 6 are sequentially formed on the package substrate 1. After lamination, the pressing process is performed to complete the multichip package.

압착공정은 표면이 노출된 제2 메모리칩(6)의 네 모서리를 눌러, 적층된 각 구성들의 부착들 돕는 공정을 뜻한다.The crimping process refers to a process of pressing the four corners of the second memory chip 6 having the exposed surface to assist the attachment of the stacked components.

그런데, 압착공정은 직접적으로 제2 메모리칩(6)에 물리적인 힘을 가하는 공정이기 때문에, 제2 메모리칩(6)의 네 모서리는 스트레스(stress)를 받게 된다. 따라서, 제2 메모리칩(6)의 모서리는 스트레스에 인한 크랙(C, crack)이 발생된다.However, since the pressing process is a step of directly applying a physical force to the second memory chip 6, four corners of the second memory chip 6 are subjected to stress. Therefore, the edge of the second memory chip 6 is cracked due to stress (C, crack).

제2 메모리칩(6)의 모서리에 크랙(C)이 발생하면, 패드(62)와 전원배선(63)이 파괴되어 원활한 신호 및 전원의 전달을 방해한다. 따라서, 크랙(C)이 발생된 제2 메모리칩(6)은 정상동작을 수행하지 못하기 때문에, 제2 메모리칩(6)을 포함하는 멀티칩 패키지는 폐기처리될 수밖에 없다.
If a crack C is generated at the edge of the second memory chip 6, the pad 62 and the power wiring 63 are destroyed to prevent the smooth transmission of signals and power. Therefore, since the second memory chip 6 in which the crack C is generated cannot perform a normal operation, the multi-chip package including the second memory chip 6 has no choice but to be disposed of.

본 발명은 압착공정에서 메모리칩에 크랙이 발생하여도, 정상적으로 동작할 수 있는 메모리칩 및 그를 포함하는 멀티칩 패키지를 개시한다.The present invention discloses a memory chip capable of operating normally even if a crack occurs in a memory chip in a crimping process, and a multichip package including the same.

이를 위해, 본 발명은 기판의 중앙에 배치되고, 데이터를 저장하는 메모리셀 어레이와 상기 메모리셀 어레이와 인접하게 배치되고, 상기 메모리셀 어레이에서 출력되는 데이터를 외부에 전달하거나, 외부의 데이터를 상기 메모리셀 어레이에 전달하는 패드 및 상기 패드와 인접하되, 상기 기판의 최외곽에 배치된 얼라인키를 포함하는 메모리 칩을 제공한다.To this end, the present invention is disposed in the center of the substrate, and disposed adjacent to the memory cell array and the memory cell array for storing data, and transfers the data output from the memory cell array to the outside, or the external data A memory chip includes a pad to be transferred to a memory cell array and an alignment key adjacent to the pad and disposed at an outermost side of the substrate.

또한, 본 발명은 패키지기판상에 배치된 제1 메모리칩 및 상기 제1 메모리칩 상에 배치되고, 최외곽에 얼라인키가 위치하는 제2 메모리칩을 포함하는 멀티칩 패키지를 제공한다
The present invention also provides a multichip package including a first memory chip disposed on a package substrate and a second memory chip disposed on the first memory chip and having an align key at the outermost side thereof.

도 1 내지 도 4는 종래기술에 따른 멀티칩 패키지의 제조 방법을 나타낸 도면이다.
도 5 내지 도 8은 본 발명의 실시예에에 따른 멀티칩 패키지의 제조 방법을 나타낸 도면이다.1 to 4 are diagrams illustrating a method of manufacturing a multichip package according to the prior art.
5 to 8 illustrate a method of manufacturing a multichip package according to an exemplary embodiment of the present invention.

이하, 실시예를 통하여 본 발명을 더욱 상세히 설명하기로 한다. 이들 실시예는 단지 본 발명을 예시하기 위한 것이며, 본 발명의 권리 보호 범위가 이들 실시예에 의해 제한되는 것은 아니다.Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

도 5 내지 도 8은 본 발명의 실시예에 따른 멀티칩 패키지의 제조 방법을 나타낸 도면이다. 여기서, 도 6 및 도 8은 각각 도 5 및 도 7의 Ⅱ-Ⅱ' 절단면을 나타낸 단면도이다.5 to 8 illustrate a method of manufacturing a multichip package according to an exemplary embodiment of the present invention. 6 and 8 are cross-sectional views illustrating cut planes II-II 'of FIGS. 5 and 7, respectively.

도 5 및 도 6에 도시된 바와 같이, 볼(120)이 형성된 패키지기판(110) 상에 제1 접착층(130)과 제1 메모리칩(140)과 제2 접착층(140) 및 제2 메모리칩(160)을 적층시킨다.5 and 6, the first adhesive layer 130, the first memory chip 140, the second adhesive layer 140, and the second memory chip on the package substrate 110 on which the ball 120 is formed. 160 is laminated.

볼(120)은 멀티칩 패키지와 모듈을 연결하기 위한 리드와 와이드본딩되는 금속패턴이다.The ball 120 is a metal pattern wide bonded with a lead for connecting the multichip package and the module.

제1 접착층(130)은 패키지기판(110)과 제1 메모리칩(140)을 접착하기 위한 박막이고, 제2 접착층(150)은 제1 메모리칩(140)과 제2 메모리칩(160)을 접착하기 위한 박막이다.The first adhesive layer 130 is a thin film for bonding the package substrate 110 and the first memory chip 140, and the second adhesive layer 150 connects the first memory chip 140 and the second memory chip 160. Thin film for bonding.

제1 및 제2 메모리칩(140, 160)은 데이터를 저장하는 반도체 메모리 장치를 의미한다. 이중, 제2 메모리칩(160)은 기판(미도시)과 메모리셀 어레이(161)와 패드(162)와 전원배선(163) 및 얼라인키(164)로 구성된다. The first and second memory chips 140 and 160 refer to semiconductor memory devices that store data. The second memory chip 160 includes a substrate (not shown), a memory cell array 161, a pad 162, a power supply wiring 163, and an alignment key 164.

메모리셀 어레이(161)는 데이터를 저장하기 위한 메모리셀의 군집영역으로서, 기판의 중앙에 배치된다.The memory cell array 161 is a cluster area of memory cells for storing data and is disposed at the center of the substrate.

패드(162)는 볼(120)과 연결되어 외부의 데이터를 메모리셀 어레이(161)에 전달하거나 메모리셀 어레이(161)의 데이터를 외부에 전달하는 금속패턴이다. 패드(162)는 메모리셀 어레이(161)의 일측에 배치된다. The pad 162 is a metal pattern connected to the ball 120 to transfer external data to the memory cell array 161 or to transfer data of the memory cell array 161 to the outside. The pad 162 is disposed on one side of the memory cell array 161.

전원배선(163)은 외부에서 인가받은 전원 또는 내부에서 생성한 전원을 필요로하는 장치, 예를 들어 메모리셀 어레이(161)에 전달하기 위한 금속배선으로서, 기판의 타측에 배치된다.The power line 163 is disposed on the other side of the substrate as a metal line for transferring to a device, for example, a memory cell array 161, which requires an externally applied power or an internally generated power.

얼라인키(164)는 기판의 최외곽에 배치된다. 얼라인키(164)는 메모리셀을 패터닝하는 과정에서, 포토마스크와 기판을 정렬하기 위해 형성된 일종의 키(key)를 의미한다. 포토마스크는 리소그라피 공정에서 포토레지스트(photo resist)를 노광 및 현상할 때 사용하는 마스크를 의미한다.The alignment key 164 is disposed at the outermost side of the substrate. The alignment key 164 refers to a kind of key formed to align the photomask and the substrate in the process of patterning the memory cells. The photomask refers to a mask used for exposing and developing photoresist in a lithography process.

도 7 및 도 8에 도시된 바와 같이, 패키지기판(110) 상에 제1 접착층(130)과 제1 메모리칩(140)과 제2 접착층(150)과 제2 메모리칩(160)을 순차적으로 적층시킨 후, 압착공정을 진행하여 멀티칩 패키지를 완성한다.As shown in FIGS. 7 and 8, the first adhesive layer 130, the first memory chip 140, the second adhesive layer 150, and the second memory chip 160 are sequentially formed on the package substrate 110. After lamination, the pressing process is performed to complete the multichip package.

압착공정은 표면이 노출된 제2 메모리칩(160)의 네 모서리를 눌러, 적층된 각 구성들의 부착들 돕는 공정을 뜻한다.The pressing process refers to a process of pressing the four corners of the second memory chip 160 having the exposed surface to help attachment of the stacked components.

그런데, 압착공정은 직접적으로 제2 메모리칩(160)에 물리적인 힘을 가하는 공정이기 때문에, 제2 메모리칩(160)의 네 모서리는 스트레스를 받게 된다. 따라서, 제2 메모리칩(160)의 모서리는 스트레스에 인한 크랙(C)이 발생되어, 제2 메모리칩(160)의 얼라인키(164)가 파괴된다.However, since the pressing process is a step of directly applying a physical force to the second memory chip 160, the four corners of the second memory chip 160 are stressed. Accordingly, cracks C are generated at the edges of the second memory chip 160 due to stress, and the alignment key 164 of the second memory chip 160 is destroyed.

하지만, 위와 같이 제2 메모리칩(160)의 모서리에 얼라인키(164)를 배치할 경우, 압착공정에서 제2 메모리칩(160)의 모서리에 크랙(C)이 발생하여도 멀티칩 패키지는 정상적으로 동작할 수 있다. 멀티칩 패키지가 정상적으로 동작할 수 있는 이유는, 패드(162)와 전원배선(163)이 아닌 얼라인키(164)가 파괴되었기 때문이다.However, when the alignment key 164 is disposed at the corner of the second memory chip 160 as described above, even if a crack C is generated at the corner of the second memory chip 160 in the crimping process, the multi-chip package is normally. It can work. The reason why the multi-chip package can operate normally is that the align key 164 other than the pad 162 and the power wiring 163 is broken.

얼라인키(164)는 앞서 설명한 바와 같이, 메모리셀을 패터닝하는 과정에서 포토마스크와 기판을 정렬하기 위해 형성된 패턴이다. 따라서, 얼라인키(164)는 메모리셀의 패터닝이 완료된 상태에서는 불필요한 패턴이다. 즉, 제2 메모리칩(160) 모서리의 크랙(C)으로 인해 얼라인키(105)가 파괴되어도, 제2 메모리칩(160)의 동작에는 어떠한 악영향도 미치지 않는다. 또한, 패드(162)와 전원배선(163)은 제2 메모리칩(160)의 모서리에 배치되지 않기 때문에, 압착공정에서 파괴되지 않는다. 따라서, 제2 메모리칩(160)은 정상적으로 동작할 수 있다.As described above, the alignment key 164 is a pattern formed to align the photomask and the substrate in the process of patterning the memory cells. Accordingly, the alignment key 164 is an unnecessary pattern in the state where the patterning of the memory cell is completed. That is, even if the alignment key 105 is destroyed due to the crack C at the edge of the second memory chip 160, the operation of the second memory chip 160 has no adverse effect. In addition, since the pad 162 and the power supply wiring 163 are not disposed at the corners of the second memory chip 160, they are not destroyed in the pressing process. Therefore, the second memory chip 160 may operate normally.

전술한 바와 같은 본 실시예를 정리해 보면, 압착공정에서 제2 메모리칩(160)의 네 모서리에 크랙(C)이 발생하여도 제2 메모리칩(160)이 정상적으로 동작할 수 있도록, 제2 메모리칩(160)의 최외곽에 제2 메모리칩(160)이 동작하는데 불필요한 소자들을 배치시킨다. 예를 들어, 제2 메모리칩(160)의 최외곽에 얼라인키(164)를 배치시킨다. 얼라인키(164)는 제2 메모리칩(160)이 제조된 후에는 불필요한 패턴이기 때문에, 제2 메모리칩(160)의 네 모서리에 크랙(C)이 발생하여 파괴되어도 제2 메모리칩(160)의 정상적인 동작에는 어떠한 악영향도 미치지 않는다.In the present embodiment, the second memory chip 160 can operate normally even if cracks C are formed at four corners of the second memory chip 160 in the pressing process. Elements unnecessary for the second memory chip 160 to operate are disposed on the outermost side of the chip 160. For example, the alignment key 164 is disposed at the outermost side of the second memory chip 160. Since the alignment key 164 is an unnecessary pattern after the second memory chip 160 is manufactured, the second memory chip 160 may be broken even if cracks C are generated at four corners of the second memory chip 160. There is no adverse effect on the normal operation of.

따라서, 제2 메모리칩(160)의 네 모서리에 크랙(C)이 발생하여도, 제2 메모리칩(160)은 정상적으로 동작하며, 나아가 제2 메모리칩(160)을 포함하는 멀티칩 패키지도 정상적으로 동작할 수 있다.
Therefore, even if cracks C occur at four corners of the second memory chip 160, the second memory chip 160 operates normally, and the multi-chip package including the second memory chip 160 also normally operates. It can work.

110 : 패키지기판 120 : 볼
130 : 제1 접착층 140 : 제1 메모리칩
150 : 제2 접착층 160 : 제2 메모리칩
161 : 메모리셀 어레이 162 : 패드
163 : 전원배선 164 : 얼라인키110: package substrate 120: ball
130: first adhesive layer 140: first memory chip
150: second adhesive layer 160: second memory chip
161: memory cell array 162: pad
163: power supply wiring 164: alignment key

Claims (10)

기판의 중앙에 배치되고, 데이터를 저장하는 메모리셀 어레이;
상기 메모리셀 어레이와 인접하게 배치되고, 상기 메모리셀 어레이에서 출력되는 데이터를 외부에 전달하거나, 외부의 데이터를 상기 메모리셀 어레이에 전달하는 패드; 및
상기 패드와 인접하되, 상기 기판의 최외곽에 배치된 얼라인키
를 포함하는 메모리 칩.
A memory cell array disposed in the center of the substrate and storing data;
A pad disposed adjacent to the memory cell array and configured to transfer data output from the memory cell array to an external device, or external data to the memory cell array; And
An alignment key adjacent to the pad and disposed at an outermost side of the substrate
Memory chip comprising a.
제 1 항에 있어서, 상기 얼라인키는 상기 메모리셀 어레이를 패터닝하기 위한 키 패턴인 메모리 칩.
The memory chip of claim 1, wherein the alignment key is a key pattern for patterning the memory cell array.
제 1 항에 있어서, 상기 메모리셀 어레이와 상기 얼라인키 사이에 배치되고, 전원을 상기 메모리셀 어레이에 전달하는 전원배선을 더 포함하는 메모리칩.
The memory chip of claim 1, further comprising a power supply wiring disposed between the memory cell array and the alignment key and configured to transfer power to the memory cell array.
패키지기판상에 배치된 제1 메모리칩; 및
상기 제1 메모리칩 상에 배치되고, 최외곽에 얼라인키가 위치하는 제2 메모리칩
을 포함하는 멀티칩 패키지.
A first memory chip disposed on the package substrate; And
A second memory chip disposed on the first memory chip and having an align key at an outermost position thereof
Multichip package comprising a.
제 4 항에 있어서, 상기 얼라인키는 상기 제2 메모리칩 제조 후에는 상기 제2 메모리칩의 동작과는 무관한 패턴인 멀티칩 패키지.
The multichip package of claim 4, wherein the alignment key is a pattern that is independent of the operation of the second memory chip after fabrication of the second memory chip.
제 4 항에 있어서, 상기 제2 메모리칩은
기판의 중앙에 배치되고, 데이터를 저장하는 메모리셀 어레이;
상기 메모리셀 어레이와 인접하게 배치되고, 상기 메모리셀 어레이에서 출력되는 데이터를 외부에 전달하거나, 외부의 데이터를 상기 메모리셀 어레이에 전달하는 패드; 및
상기 패드와 인접하되, 상기 기판의 최외곽에 배치된 상기 얼라인키를 포함하는 멀티칩 패키지.
The method of claim 4, wherein the second memory chip
A memory cell array disposed in the center of the substrate and storing data;
A pad disposed adjacent to the memory cell array and configured to transfer data output from the memory cell array to an external device, or external data to the memory cell array; And
And a align key adjacent to the pad and disposed at the outermost side of the substrate.
제 6 항에 있어서, 상기 얼라인키는 상기 메모리셀 어레이를 패터닝하기 위한 키 패턴인 멀티칩 패키지.
The multichip package of claim 6, wherein the alignment key is a key pattern for patterning the memory cell array.
제 4 항에 있어서, 상기 메모리셀 어레이와 상기 얼라인키 사이에 배치되고, 전원을 상기 메모리셀 어레이에 전달하는 전원배선을 더 포함하는 메모리칩.
5. The memory chip of claim 4, further comprising a power supply wiring disposed between the memory cell array and the alignment key and transferring power to the memory cell array.
제 4 항에 있어서, 상기 패키지기판과 상기 제1 메모리칩 사이에 배치된 제1 접착층을 더 포함하는 멀티칩 패키지
The multichip package of claim 4, further comprising a first adhesive layer disposed between the package substrate and the first memory chip.
제 4 항에 있어서, 상기 제1 메모리칩과 상기 제2 메모리칩 사이에 배치된 제2 접착층을 더 포함하는 멀티칩 패키지
The multichip package of claim 4, further comprising a second adhesive layer disposed between the first memory chip and the second memory chip.
KR1020100017334A 2010-02-25 2010-02-25 Memory chips and multichip packages containing them Withdrawn KR20110097474A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2595360A2 (en) 2011-09-27 2013-05-22 Lg Electronics Inc. Display device and method for controlling the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2595360A2 (en) 2011-09-27 2013-05-22 Lg Electronics Inc. Display device and method for controlling the same

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