KR20110076654A - Liquid Crystal Display Manufacturing Method - Google Patents

Abstract

The present invention discloses a method for manufacturing a liquid crystal display device. The disclosed liquid crystal display device manufacturing method includes: forming a common electrode and a first device electrode on a gate electrode and a real region on a substrate; Sequentially forming a gate insulating film, an amorphous silicon film, and a doped amorphous silicon film on the substrate on which the gate electrode is formed, and then forming an active layer on the gate electrode; Forming a source / drain metal film on the substrate on which the active layer is formed, and then forming a source / drain electrode and a second device electrode on the seal region; Forming a passivation layer on the substrate on which the source / drain electrodes are formed, and then exposing a portion of the drain electrode, the common line, the first device electrode, and the second device electrode; And sequentially forming a transparent conductive material film and an insulating film on the substrate on which the protective film is formed, and then sequentially performing a first dry etching process, a wet etching process, and a second dry etching process to contact the drain electrode. Forming a contact pattern contacting the common line, a connection pattern connecting the first and second device electrodes, and a capping layer on the connection pattern.

Description

Liquid crystal display device manufacturing method {Method for fabricating liquid crystal display device}

The present invention relates to a method for manufacturing a liquid crystal display device.

Conventional liquid crystal display devices display an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which pixel regions are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

In the liquid crystal display panel, a TFT (Thin Film Transistor) substrate and a color filter substrate are bonded to each other with a liquid crystal layer interposed therebetween. Therefore, in order to drive the liquid crystal layer for each pixel, a plurality of gate lines and a plurality of data lines are arranged to cross each other in the TFT substrate to define a pixel region. Pixel electrodes are formed in each pixel region, and TFTs are formed at portions where the gate lines and the data lines cross each other. The TFT is turned on according to the scan signal of each gate line to apply the data signal of the data line to each pixel electrode.

In addition, the color filter substrate includes a color filter layer formed in each pixel area to realize black matrix, red (R), green (G), and blue (B) colors to block light in portions other than the pixel area. And a common electrode corresponding to the pixel electrode to form an electric field for driving the liquid crystal layer.

In addition, a gate driver for sequentially supplying a scan pulse to each gate line and a data driver for supplying a data signal to each data line are provided.

Conventionally, the gate driver has used a separate gate driver integrated circuit (Gate Driver IC) in which a shift register is built, and connected the gate driver pad to a gate line pad of a liquid crystal panel using a TCP (Taped Carrier Package) process.

Recently, however, a gate in panel (GIP) technology has been developed in which a gate driver is directly mounted on a liquid crystal display panel in order to reduce material costs, process number, and process time.

However, a liquid crystal display having a GIP structure has a disadvantage in that a bezel width is increased because a plurality of signal lines and circuits are formed in a gate pad region and a seal line is formed outside.

In addition, when the conductive sealant is used to electrically connect the common line of the TFT substrate and the common electrode of the color filter substrate, a short circuit occurs when the conductive sealant is applied to the GIP region.

If the insulating sealant is applied and a separate Ag dotting process is performed, the process becomes complicated.

Accordingly, in order to simplify the process while reducing the bezel width, it is necessary to apply the conductive sealant to the GIP region to simultaneously perform the bonding process and the connection process between the common line and the common electrode.

An object of the present invention is to provide a method of manufacturing a liquid crystal display device having a reduced bezel area by applying a conductive sealant to a GIP region and a signal line region to bond a TFT substrate and a color filter substrate.

The present invention provides a liquid crystal display device that can connect a common line and a common electrode while preventing a short circuit of circuit elements by forming a capping layer on a connection pattern connecting circuit elements among a GIP region and a signal line region to which a conductive sealant is applied. Another purpose is to provide a method.

The liquid crystal display device manufacturing method of the present invention for solving the above problems comprises the steps of forming a common electrode and a first device electrode on the gate electrode and the real region on the substrate; Sequentially forming a gate insulating film, an amorphous silicon film, and a doped amorphous silicon film on the substrate on which the gate electrode is formed, and then forming an active layer on the gate electrode; Forming a source / drain metal film on the substrate on which the active layer is formed, and then forming a source / drain electrode and a second device electrode on the seal region; Forming a passivation layer on the substrate on which the source / drain electrodes are formed, and then exposing a portion of the drain electrode, the common line, the first device electrode, and the second device electrode; And sequentially forming a transparent conductive material film and an insulating film on the substrate on which the protective film is formed, and then sequentially performing a first dry etching process, a wet etching process, and a second dry etching process to contact the drain electrode. Forming a contact pattern contacting the common line, a connection pattern connecting the first and second device electrodes, and a capping layer on the connection pattern.

The manufacturing method of the liquid crystal display of the present invention has the effect of connecting the common line and the common electrode together with the bonding process without short circuit failure of the circuit elements in the region where the conductive sealant is formed.

The manufacturing method of the liquid crystal display of the present invention has the effect of simplifying the manufacturing process by forming a capping layer on the connection pattern of the GIP region when forming the pixel electrode.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following embodiments are provided as examples to sufficiently convey the spirit of the present invention to those skilled in the art. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the size and thickness of the device may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 schematically shows the structure of a liquid crystal display according to the present invention.

Referring to FIG. 1, in the liquid crystal display device of the present invention, the color filter substrate 102 and the TFT substrate 100 are bonded by the conductive sealant 50. A / A is an area where an image is displayed as an active area.

On the TFT substrate 100, a plurality of gate lines and a plurality of data lines are arranged to cross each other, and a pixel region is positioned in an area defined by crossing the gate lines and the data lines. Pixel electrodes for forming an electric field are formed in each of the pixel regions.

The black matrix, red (R), green (G), blue (B) color filter layers and a common electrode are formed on the color filter substrate 102.

In addition, one side of the TFT substrate 100 of the present invention includes a GIP region 33 in which circuit elements of a gate driver are formed. A plurality of signal lines 25 are formed in an area adjacent to the GIP area 33.

In addition, a data driver 27 is formed on the other side of the TFT substrate 100. Signal lines 25 for supplying signals to circuit elements of the GIP region 33 are electrically connected to link lines (not shown) drawn from one of the data drivers 27. That is, the signal lines 25 receive a signal from the system via any one of the data drivers 27.

The conductive sealant 50 includes a plurality of conductive balls, and the color filter substrate 102 and the TFT substrate are electrically connected to the common line of the signal lines 25 and the common electrode of the color filter substrate 102. (100) is bonded.

In the present invention, the conductive sealant 50 is applied to the signal lines 25 and the GIP region 33 to reduce the bezel region. In addition, although not shown in the drawing, a capping layer formed of an insulating material is formed on the connection patterns exposed to the outside in the GIP region 33, so that the common line and the color filter substrate of the TFT substrate 100 are not shorted. The common electrode of 102 was electrically connected.

2 is an enlarged cross-sectional view of a signal line region and a GIP region coated with a conductive sealant in the liquid crystal display of the present invention.

Referring to FIG. 2, in the TFT substrate of the liquid crystal display of the present invention, the common line 15 and the first device electrode 16 in the GIP region are formed on the first substrate 10, and the common line 15 is formed. ) And a gate insulating film 12 are formed on the first device electrode 16. The second device electrode 21 is formed on the gate insulating film 12 in the GIP region.

The passivation layer 19 is formed on the first substrate 10 on which the second device electrode 21 is formed.

In the common line 15, the passivation layer 19 and the gate insulating layer 12 are removed to make electrical contact with the common electrode 80 of the color filter substrate. The contact electrode 45 is formed in the region where the common line 15 is exposed.

In addition, in the GIP region, the first device electrode 16 and the second device electrode 21 are connected by a connection pattern 46, and a capping layer 48 made of an insulating material is formed on the connection pattern 46. have.

In the color filter substrate, the black matrix 21 and the color filter layer 23 are formed on the second substrate 20, and the common electrode 80 is formed on the black matrix 21 and the color filter layer 23. .

The common line 15 of the TFT substrate and the common electrode 80 of the color filter substrate are electrically connected to each other by the conductive balls 300 included in the conductive sealant 50.

However, the capping layer 48 is formed on the connection pattern 46 exposed to the GIP region, so that the elements and the common electrode 80 in the GIP region are formed even when the conductive ball 300 is positioned on the connection pattern 46. There is no electrical short.

Therefore, in the present invention, the conductive sealant can be applied to the signal lines and the GIP region, thereby reducing the bezel region.

In addition, the conductive sealant does not cause short circuits or signal defects in the GIP region.

3A to 3E illustrate a manufacturing process of a liquid crystal display according to the present invention.

3A to 3E, after forming a metal film on the first substrate 10, a first mask process is performed to form the gate electrode 11 in the TFT region, and a common line in the seal region. 15 and the first device electrode 16 are formed.

The metal film may be formed of a single metal layer such as copper (Cu), aluminum (Al), molybdenum (Mo), or Cr having high conductivity, and in some cases, at least one of them may be formed in a laminate or alloy form. .

When the gate electrode 11 is formed on the first substrate 10 as described above, as shown in FIG. 3B, the gate insulating film 12, the amorphous silicon film, and the P + or N + type are formed on the first substrate 10. Doped amorphous silicon film is formed sequentially.

Next, a second mask process is performed to form an active layer 14 made of an amorphous silicon film and a doped amorphous silicon film on the gate electrode 11.

At this time, the amorphous silicon film and the doped amorphous silicon film formed in the seal region are removed. However, the active layer 14 is formed in the TFT region of the GIP region (not shown).

As described above, when the active layer 14 is formed on the first substrate 10, as shown in FIG. 3C, a source / drain metal layer is formed, and then a third mask process is performed to form the source / drain electrodes 17a. , 17b). The second element electrode 21 is formed in the real region.

When the source / drain electrodes 17a and 17b are formed on the first substrate 10, as shown in FIG. 3D, the passivation layer 19 is formed and then a fourth mask process is performed to form the drain electrode 17b. Part of the At this time, the passivation layer 19 on the common line 15, the first device electrode 16, and the second device electrode 21 in the real region is also removed and exposed.

3E, a transparent conductive material film and an insulating film are sequentially formed on the first substrate 10, and then a fifth mask process is performed to form the pixel electrode 39. In the real region, a connection pattern 48 connecting the contact electrode 45, the first device electrode 16, and the second device electrode 21 is formed on the exposed common line 15.

At this time, since the insulating film is formed on the transparent conductive material film, the insulating film is etched by the primary dry etching process, and the wet conductive process is performed to etch the transparent conductive material film. The pixel electrode 39, the first device electrode 16, and the second device electrode 21 are formed by etching the transparent conductive material film.

In this case, since an insulating film is formed on the pixel electrode 39, the contact electrode 45, and the connection pattern 48, the secondary dry etching process is continuously performed on the pixel electrode 39 and the contact electrode 45. The insulating film formed in the film is removed. The insulating film remaining on the connection pattern 48 is not removed and becomes the capping layer 48.

Therefore, even if the conductive sealant is applied, the devices in the GIP region do not have a short circuit, and the common line 15 is electrically connected to the common electrode of the color filter substrate through the conductive balls included in the conductive sealant.

As described above, the present invention enables the common line and the common electrode to be conductive while applying the conductive sealant to the signal lines and the GIP region, thereby simplifying the manufacturing process.

1 schematically shows the structure of a liquid crystal display according to the present invention.

2 is an enlarged cross-sectional view of a signal line region and a GIP region coated with a conductive sealant in the liquid crystal display of the present invention.

3A to 3E illustrate a manufacturing process of a liquid crystal display according to the present invention.

 (Explanation of reference numerals for the main parts of the drawings)

10: first substrate 15: common line

16: first device electrode 12: gate insulating film

19: protective film 45: contact electrode

46: connection pattern 48: capping layer

300: Challenge Ball

Claims (4)

Forming a common electrode and a first device electrode in the gate electrode and the real region on the substrate; Sequentially forming a gate insulating film, an amorphous silicon film, and a doped amorphous silicon film on the substrate on which the gate electrode is formed, and then forming an active layer on the gate electrode; Forming a source / drain metal film on the substrate on which the active layer is formed, and then forming a source / drain electrode and a second device electrode on the seal region; Forming a passivation layer on the substrate on which the source / drain electrodes are formed, and then exposing a portion of the drain electrode, the common line, the first device electrode, and the second device electrode; And A transparent conductive material film and an insulating film are sequentially formed on the substrate on which the protective film is formed, and then a first dry etching process, a wet etching process, and a second dry etching process are sequentially performed to contact the drain electrode; And forming a capping layer on the contact pattern and a contact pattern connecting the first and second device electrodes. The method of claim 1, wherein the capping layer is formed of an insulating film formed on the transparent conductive material film. The method of claim 1, wherein a conductive sealant is formed in the seal region. The method of claim 1, wherein in the second dry etching process, an insulating layer formed on the contact electrode of the pixel electrode and the common line is removed, and an insulating layer formed on the connection pattern is not removed. .

Images