KR20100108821A - Auxiliary power supply and user device including the same - Google Patents

Abstract

The auxiliary power supply according to the present invention includes a first power storage device for storing auxiliary power; A second power storage device for storing auxiliary power; And a power control device for gradually providing auxiliary power of the first and second power storage devices in a sudden power-off of the external power supply device. According to the present invention, the auxiliary power supply can provide an auxiliary power in stages during sudden power-off of the main power supply, thereby preparing for a failure of the super capacitor, and stably performing the power-off operation.

Description

AUXILIARY POWER SUPPLY AND USER DEVICE INCLUDING THE SAME}

The present invention relates to a user device, and more particularly, to a user device including an auxiliary power supply.

User devices include electronic devices such as personal computers, digital cameras, camcorders, mobile phones, MP3s, PMPs, PDAs, and the like, as well as storage devices such as memory cards, USB memories, and the like. Most of these user devices include a memory device for storing data internally. Memory devices include volatile memory such as DRAM and SRAM, and nonvolatile memory such as EEPROM, FRAM, PRAM, MRAM, and Flash Memory. Volatile memory loses its stored data when power is lost, while nonvolatile memory preserves its data even when power is lost.

The user device is powered from an internal or external power supply. Here, the power supply device may be a home or business power supply such as 110V, 220V, or the like, or may be a charging device inside the user device. The user device may be fatally damaged such as data loss due to sudden power off (hereinafter referred to as sudden power off) of the power supply.

For example, flash memory-based semiconductor disk devices (eg, SSDs) need to secure metadata or cache data, which can be lost due to sudden power off. To solve this problem, manufacturers are developing various user devices to prepare for sudden power off of the power supply.

Conventional user equipment uses one super capacitor to provide auxiliary power at sudden power off. Conventional user equipment has limitations in preparing for sudden power off due to the lack of auxiliary power of the super capacitor at the time of sudden power off. In addition, the conventional user device has a problem that can not be prepared for sudden power off, if a failure or a problem occurs in the super capacitor.

The present invention has been proposed in order to solve the above technical problem, and an object of the present invention is to provide a secondary power source capable of solving a problem due to a shortage of secondary power supply and failure of a super capacitor during sudden power off (SPO). A device and a user device including the same are provided.

An auxiliary power device according to an embodiment of the present invention includes a first power storage device for storing auxiliary power; A second power storage device for storing auxiliary power; And a power control device for gradually providing auxiliary power of the first and second power storage devices in a sudden power-off of the external power supply device.

In example embodiments, the power control device may include a timer for calculating a time when the auxiliary power of the first power storage device is provided, and providing the auxiliary power of the second power storage device after a preset time. Alternatively, the power control device may include: a first power line connected to the external power supply device and configured to provide auxiliary power of the first power storage device; A second power line for providing auxiliary power of the second power storage device; A switch for switching the second power line; And a timer controlling the switch according to a time when the auxiliary power of the first power storage device is provided. The power control device may further include a unidirectional element connected between the first and second power lines and blocking the auxiliary power of the second power storage device from being provided to the first power line.

In another embodiment, the power control device may include a voltage detector for detecting an auxiliary power level of the first power storage device and providing an auxiliary power supply of the second power storage device when a preset level is reached. Alternatively, the power control device may include a first power line connected to the external power supply device and configured to provide auxiliary power of the first power storage device; A second power line for providing auxiliary power of the second power storage device; A switch for switching the second power line; And a voltage detector controlling the switch according to the auxiliary power level of the first power storage device. The power control device may further include a unidirectional element connected between the first and second power lines and blocking the auxiliary power of the second power storage device from being provided to the first power line.

In another embodiment, the power control device detects a charging state of the first and second power storage devices, and provides a charge detector for providing auxiliary power of the first and second power storage devices step by step according to the detection result. It includes. The charge detector may inform the external state of charge of the first and second power storage devices.

A user device according to an embodiment of the present invention includes a main power supply for providing a main power source; And an auxiliary power supply for providing auxiliary power at sudden power-off of the main power supply. Here, the auxiliary power supply device includes a plurality of power storage devices, and provides auxiliary power of the plurality of power storage devices in stages.

In example embodiments, the user device may further include a memory device including a nonvolatile memory and a volatile memory, wherein the memory device uses the auxiliary power from the volatile memory when the main power supply is suddenly powered off. Back up data to nonvolatile memory.

In another embodiment, the auxiliary power supply device calculates a time period during which the auxiliary power of the first power storage device is provided among the plurality of power storage devices, and when the preset time passes, the auxiliary power supply of the second power storage device is stored in the memory device. It further includes a timer to provide.

In another embodiment, the auxiliary power supply may be configured to be configured to receive an operation end signal from the memory device until a preset time elapses after the auxiliary power of the first power storage device is provided from among the plurality of power storage devices. And a timer for providing auxiliary power of a two power storage device to the memory device.

In another exemplary embodiment, the auxiliary power supply may include a second power supply when the operation continuation signal arrives from the memory device after a preset time elapses after the auxiliary power of the first power storage device is provided among the plurality of power storage devices. And a timer for providing an auxiliary power source of a storage device to the memory device.

In another embodiment, the auxiliary power supply may detect an auxiliary power level of the first power storage device among the plurality of power storage devices, and when the preset power level is reached, the auxiliary power supply of the second power storage device may be transferred to the memory device. It further comprises a voltage detector for providing.

According to another embodiment, the auxiliary power supply may be configured to receive an operation end signal from the memory device until the auxiliary power supply of the first power storage device is supplied to the first power storage device and then drops to a preset level. And a voltage detector for providing an auxiliary power of a two power storage device to the memory device.

In another exemplary embodiment, the auxiliary power supply may include a second power supply when the operation continuation signal arrives from the memory device after the auxiliary power of the first power storage device is provided and falls to a predetermined level among the plurality of power storage devices. And a voltage detector for providing an auxiliary power source of a storage device to the memory device.

In another embodiment, the auxiliary power supply further includes a charge detector for sensing a charging state of the plurality of power storage devices and providing auxiliary power in stages according to the detection result. The display apparatus may further include a display device configured to notify the outside of the state of charge of the plurality of power storage devices.

According to the present invention, the auxiliary power supply can prepare for the failure of the super capacitor by supplying the auxiliary power in stages at the time of sudden power-off of the main power supply, and can perform the stable power-off operation stably.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

1 is a block diagram illustrating a first embodiment of a user device according to the present invention. Referring to FIG. 1, the user device 100 includes a power supply 110, an auxiliary power supply 120, and a storage device 130. The user device 100 may gradually supply auxiliary power during Sudden Power Off (SPO).

The power supply device 110 provides the operating power of the user device 100. The power supply unit 110 may include various types of power supply devices, such as a DC power source, an AC power source, and a rechargeable battery. In the following description, the power supply 110 will be used in terms of a main power supply or an external power supply to distinguish it from an auxiliary power supply 120.

The main power supply 110 may be suddenly cut off due to an unexpected situation such as user carelessness or a device defect. This phenomenon is called Sudden Power Off (SPO). If a sudden power off occurs, the storage device 130 is at risk of losing data being processed or stored. In particular, if the data being processed in the storage device 130 is important data such as cache data or metadata, the user device 100 may be fatally damaged due to sudden power off.

The user device 100 shown in FIG. 1 includes an auxiliary power supply 120 to reduce losses due to sudden power off. Since the auxiliary power supply 120 includes a plurality of power storage devices, the auxiliary power supply 120 may gradually supply auxiliary power during sudden power off.

Referring to FIG. 1, the auxiliary power supply 120 includes first and second supercapacitors 121 and 122, a unidirectional element 125, a switch 127, and a timer 128. Here, the first and second supercapacitors 121 and 122 are power storage devices for storing auxiliary power. The unidirectional element 125, the switch, and the timer 128 are power control devices for controlling the power storage device.

The supercapacitors 121 and 122 are power storage devices capable of holding high capacity charges and are used to store auxiliary power. The super capacitors 121 and 122 may charge electric charges during power up or normal operation of the user device 100. The supercapacitors 121 and 122 may provide auxiliary power to the user device 100 using the charging charge. Auxiliary power supplies of the first and second supercapacitors 121 and 122 are provided in stages. That is, the auxiliary power supply of the first super capacitor 121 is provided, and after a predetermined time, the auxiliary power supply of the second super capacitor 122 is provided.

The unidirectional element 125 is connected between the first and second power lines PL1 and PL2. The unidirectional device 125 is a device capable of flowing a current only in one direction, such as a diode. The unidirectional element 125 forms a current path from the first power line PL1 to the second power line PL2 according to the voltage difference between the first and second power lines PL1 and PL2. . The unidirectional element 125 is turned on while the second supercapacitor 122 is being charged, and is turned off while being discharged. The unidirectional device 125 may block the auxiliary power supply of the second super capacitor 122 from being supplied to the first power line PL1.

The switch 127 is connected between the second super capacitor 122 and the storage device 130. The switch 127 provides the auxiliary power of the second super capacitor 122 to the storage device 130 through the second power line PL2 under the control of the timer 128. The switch 127 may be implemented as a device such as a MOS transistor, a pass gate, or the like.

The timer 128 calculates the time that the auxiliary power supply of the first super capacitor 121 is provided. The timer 128 controls the switch 127 so that the auxiliary power of the second super capacitor 122 is automatically provided after a preset time passes after the auxiliary power of the first super capacitor 121 is provided. The timer 128 previously stores the operating time of the second super capacitor 122 therein.

The timer 128 prevents a sudden power off operation from being normally performed due to the lack of an auxiliary power supply of the first super capacitor 121. A sudden power off operation (SPO operation) refers to a finishing operation such as garbage collection or data backup that can be performed at sudden power off.

Supercapacitors can reduce the amount of auxiliary power over time. If the auxiliary power supply is insufficient after the first supercapacitor 121 is operated and a predetermined time has elapsed, the user device 100 may not sufficiently perform the sudden power off operation. The timer 128 provides the auxiliary power supply of the second super capacitor 122 after a predetermined time, so that the sudden power off operation is normally performed.

The auxiliary power supply 120 shown in FIG. 1 provides auxiliary power of the first super capacitor 121 at sudden power-off, and automatically provides auxiliary power of the second super capacitor 122 after a predetermined time. do. The storage device 130 performs a sudden power-off operation by using the auxiliary power of the first and second supercapacitors 121 and 122 stepwise.

1, a semiconductor memory device including a volatile memory (VM) 131, a nonvolatile memory (NVM) 132, and a memory controller 133 is illustrated as an example of a storage device. The memory device 130 may receive power from the main power supply device 110 or the auxiliary power supply device 120 using the power lines PL1 and PL2. The storage device may include a magnetic disk device, a hard disk device (HDD), and the like in addition to the semiconductor memory device.

Volatile memory 131 is a storage device that can lose data when power is cut off and includes DRAM, SRAM, and the like. The nonvolatile memory 132 is a storage device capable of preserving data even when power is cut off. The nonvolatile memory 132 includes EEPROM, FRAM, PRAM, MRAM, and Flash Memory. The memory controller 133 may control read, write, and erase operations of the volatile memory 131 and the nonvolatile memory 132.

In general, the nonvolatile memory 132 may retain data even when power is cut off, but has a disadvantage of slow data processing speed. To compensate for this disadvantage, the user device 100 reads data stored in the nonvolatile memory 132 into the volatile memory 131 and then processes the data using the volatile memory 131. Data processed by the volatile memory 131 is backed up to the nonvolatile memory 132 for safe protection.

The auxiliary power supply 120 illustrated in FIG. 1 calculates a discharge time of the first super capacitor 121 and discharges the second super capacitor 122 according to the calculation result. The user device 100 may safely perform a data backup operation by using an auxiliary power source provided in stages during sudden power off.

The user device 100 illustrated in FIG. 1 may provide auxiliary power of the first and second super capacitors 121 and 122 step by step according to the discharge time of the first super capacitor 121. The user device 100 may solve a conventional problem in which the sudden power off operation is not normally performed due to the lack of an auxiliary power source. According to the user device 100 according to the present invention, it is possible to safely perform a sudden power off operation such as data backup at the time of sudden power off.

2 is a block diagram illustrating a second embodiment of a user device according to the present invention. Referring to FIG. 2, the user device 200 includes a main power supply 210, an auxiliary power supply 220, and a memory device 230. The configuration and operation of the main power supply device 210 and the memory device 230 are the same as those described with reference to FIG. 1. The memory device 230 includes a volatile memory 231, a nonvolatile memory 232, and a memory controller 233.

Referring to FIG. 2, the auxiliary power supply 220 includes first and second supercapacitors 221 and 222, a unidirectional element 225, a switch 227, and a voltage detector 228. The voltage detector 228 detects the auxiliary power level of the first super capacitor 221 at the sudden power off. The voltage detector 228 controls the switch 227 to provide an auxiliary power supply of the second super capacitor 222 when the auxiliary power supply of the first super capacitor 221 reaches a predetermined level. The voltage detector 228 prevents a sudden power off operation from being normally performed due to a defect of the first super capacitor 221 or a lack of an auxiliary power supply.

The user device 200 illustrated in FIG. 2 may provide auxiliary power of the first and second super capacitors 221 and 222 step by step according to the auxiliary power level of the first super capacitor 221. The user device 200 may solve a problem in which a sudden power off operation is not normally performed due to a defect of a super capacitor or a lack of an auxiliary power supply. According to the user device 200 according to the present invention, it is possible to safely perform the sudden power off operation.

3 is a block diagram illustrating a third embodiment of a user device according to the present invention. Referring to FIG. 3, the user device 300 includes a main power supply device 310, an auxiliary power supply device 320, and a memory device 330. The auxiliary power supply 320 includes first and second supercapacitors 321 and 322, a unidirectional element 325, a switch 327, and a timer 328. The memory device 330 includes a volatile memory 331, a nonvolatile memory 332, and a memory controller 333.

The auxiliary power supply 320 sequentially provides auxiliary power of the first and second supercapacitors 321 and 322 to the memory device 330 at the sudden power off. The auxiliary power supply 320 is provided with the auxiliary power supply of the first super capacitor 321, and if the auxiliary power supply 320 does not receive a job finish signal (JFS) from the memory device 330 within a predetermined time, the second super capacitor 322. ) Is supplied to the memory device 330.

The memory device 330 may perform a sudden power off operation by using auxiliary power supplies of the first and second supercapacitors 321 and 322. The memory device 330 may back up data stored in the volatile memory 331 to the nonvolatile memory 332. The memory controller 333 generates a job finish signal (JFS) when the data backup operation ends. The job end signal JFS is a signal indicating the end of the sudden power off operation. The job end signal JFS is provided to the timer 328.

The timer 328 calculates the time that the auxiliary power supply of the first super capacitor 321 is provided. The timer 328 prevents a sudden power off operation from being performed normally due to the lack of an auxiliary power supply of the first super capacitor 321. The timer 328 provides the auxiliary power supply of the second super capacitor 322 after a predetermined time, so that the sudden power off operation is normally performed.

On the other hand, the timer 328 is provided with the auxiliary power supply of the first super capacitor 321, and may receive the switch 327 when the job termination signal (JFS) is received after a predetermined time. The timer 328 prevents unnecessary discharge of the auxiliary power supply after the termination of the sudden power off operation. The timer 328 blocks the switch 327 when the sudden power-off operation is terminated during the operation of the first super capacitor 321, thereby preventing unnecessary discharge of the second super capacitor 322.

The user device 300 illustrated in FIG. 3 may use only the first supercapacitor 321 or use the first and second supercapacitors 322 step by step depending on whether the memory device 330 is finished. The user device 300 may solve a problem in which the sudden power-off operation is not normally performed due to a lack of auxiliary power. In addition, the user device 300 may efficiently use the auxiliary power of the super capacitor.

4 is a block diagram illustrating a fourth embodiment of a user device according to the present invention. Referring to FIG. 4, the user device 400 includes a main power supply 410, an auxiliary power supply 420, and a memory device 430. The auxiliary power supply 420 includes first and second supercapacitors 421 and 422, a unidirectional element 425, a switch 427, and a voltage detector 428. The memory device 430 includes a volatile memory 431, a nonvolatile memory 432, and a memory controller 433.

Referring to FIG. 4, the voltage detector 428 receives the job termination signal JFS from the memory controller 433 and controls the switch 427. The voltage detector 428 detects the auxiliary power level of the first super capacitor 421 at the time of sudden power-off, and turns on the switch 427 when the operation end signal JFS is not received until it falls to a preset level. do. In this case, the auxiliary power of the second super capacitor 422 is provided to the memory device 430.

On the other hand, the voltage detector 428 turns off the switch 427 when the operation end signal JFS is input before the auxiliary power of the first super capacitor 421 drops to a predetermined level. In this case, the auxiliary power of the second super capacitor 422 is not provided to the memory device 430. That is, the voltage detector 428 prevents unnecessary use of the second super capacitor 422.

The user device 400 shown in FIG. 4 uses only the first supercapacitor 421 or phases up the first and second supercapacitors 422 according to whether the memory device 430 ends the operation at the time of sudden power off. Can be used as According to the user device 400 illustrated in FIG. 4, an auxiliary power supply of a super capacitor may be efficiently used.

5 is a block diagram illustrating a fifth embodiment of a user device according to the present invention. Referring to FIG. 5, the user device 500 includes a main power supply 510, an auxiliary power supply 520, and a memory device 530. The auxiliary power supply 520 includes first and second supercapacitors 521 and 522, a unidirectional element 525, a switch 527, and a timer 528. The memory device 530 includes a volatile memory 531, a nonvolatile memory 532, and a memory controller 533.

The memory controller 533 generates a job continuation signal (JCS) when a data backup operation is continued. The generation of the job continuation signal JCS means that a sudden power off operation is in progress. The job continue signal JCS is provided to a timer 528.

The timer 528 receives a job continuation signal JCS from the memory controller 533 and controls the switch 567. The timer 528 calculates the time that the auxiliary power supply of the first super capacitor 521 is provided. The timer 528 turns on the switch 527 when the job continuation signal JCS is input after a predetermined time has passed. In this case, the auxiliary power of the second super capacitor 522 is provided to the memory device 530.

The timer 528 may allow auxiliary power to continue to be provided while a sudden power off operation is in progress. The timer 528 prevents the auxiliary power source from shutting down during the sudden power off operation. That is, the timer 528 allows the sudden power off operation to be performed stably. On the other hand, the timer 528 is provided with the auxiliary power supply of the first super capacitor 321, and if the operation continuation signal (JCS) is not input after a certain time, the switch 527 is blocked. The timer 528 may prevent unnecessary discharge of the auxiliary power source after the termination of the sudden power off operation.

The user device 500 shown in FIG. 5 may use only the first super capacitor 521 or use the first and second super capacitors 522 step by step, depending on whether the sudden power off operation is continued. According to the user device 500 illustrated in FIG. 5, it is possible to stably perform a sudden power off operation, and to efficiently use an auxiliary power source.

6 is a block diagram illustrating a sixth embodiment of a user device according to the present invention. Referring to FIG. 6, the user device 600 includes a main power supply 610, an auxiliary power supply 620, and a memory device 630. The auxiliary power supply 620 includes first and second supercapacitors 621 and 622, a unidirectional element 625, a switch 627, and a voltage detector 628. The memory device 630 includes a volatile memory 631, a nonvolatile memory 632, and a memory controller 633.

Referring to FIG. 6, the voltage detector 628 receives the operation continuation signal JCS from the memory controller 633 and controls the switch 667. The voltage detector 628 detects the auxiliary power level of the first super capacitor 621 upon sudden power off. The voltage detector 628 turns on the switch 627 when the operation continuation signal JCS is input after the auxiliary power source falls to a preset level. In this case, the auxiliary power of the second super capacitor 622 is provided to the memory device 630.

The user device 600 shown in FIG. 6 may use only the first supercapacitor 621 or use the first and second supercapacitors 622 step by step, depending on whether the sudden power off operation is continued. According to the user device 600 illustrated in FIG. 6, a sudden power off operation may be safely performed.

7 is a block diagram illustrating a seventh embodiment of a user device according to the present invention. Referring to FIG. 7, the user device 700 includes a main power supply 710, an auxiliary power supply 720, and a memory device 730. The auxiliary power supply 720 includes first to Nth supercapacitors 721 to 723, a plurality of unidirectional elements 725 to 726, a switch 727, and a switch control circuit 728. The memory device 730 includes a volatile memory 731, a nonvolatile memory 732, and a memory controller 733.

The auxiliary power supply 720 may gradually provide the auxiliary power of the first to Nth supercapacitors 721 to 723 to the memory device 730 at the sudden power off. In FIG. 7, the switch control circuit 728 may control the switch 727 according to time or voltage level, such as a timer or a voltage detector described above.

The switch control circuit 728 may receive a control signal CTRL from the memory controller 733 and control the switch 727. Here, the control signal CTRL is a switch control signal such as the job end signal JFS or the job continuation signal JCS described above. The switch 727 may gradually provide the auxiliary power of the second to Nth supercapacitors 722 to 723 to the memory device 730 under the control of the switch control circuit 728.

The user device 700 shown in FIG. 7 includes two or more supercapacitors, and may use the auxiliary power supply in stages according to a sudden power off operation. According to the user device 700 illustrated in FIG. 7, a sudden power-off operation may be performed for a longer time by distributing an operating time or a voltage level of the super capacitor.

8 is a block diagram illustrating an eighth embodiment of a user device according to the present invention. Referring to FIG. 8, the user device 800 includes a main power supply 810, an auxiliary power supply 820, a memory device 830, and a display device 840. The auxiliary power supply 820 includes first to Nth supercapacitors 821 to 823, a plurality of unidirectional elements 825 to 826, a switch 827, and a charge detector 828. The memory device 830 includes a volatile memory 831, a nonvolatile memory 832, and a memory controller 833.

The auxiliary power supply 820 may gradually provide the auxiliary power of the first to Nth supercapacitors 821 to 823 to the memory device 830 at the sudden power off. In FIG. 8, the charge detector 828 may detect the state of charge of the first to Nth supercapacitors 821 to 823, and control the switch 827 according to the detection result. In addition, the charge detector 828 may provide the detection result to the display device 840.

The user device 800 illustrated in FIG. 8 may provide a charging state of the first to Nth supercapacitors 821 to 823 to the outside through the display device 840. The user can easily know the state of charge and replacement of the supercapacitors 821 to 823 through the display device 840.

9 is a block diagram illustrating a ninth embodiment of a user device according to the present invention. Referring to FIG. 9, the user device 900 includes a main power supply 910, an auxiliary power supply 920, and a memory device 930. The auxiliary power supply 920 includes first and second supercapacitors 921 and 922, a unidirectional element 925, a switch 927, and a switch control circuit 928. The memory device 930 includes a volatile memory 931, a nonvolatile memory 932, and a memory controller 933.

The auxiliary power supply 920 may gradually provide auxiliary power of the first and second supercapacitors 921 and 922 to the memory device 930 at the sudden power off. In FIG. 9, the switch control circuit 928 may control the switch 927 according to time or voltage level, such as a timer or a voltage detector described above. The switch control circuit 928 may receive a control signal CTRL from the memory controller 933 and control the switch 927.

9, a switch 927 is connected between the first and second super capacitors 921 and 922. The user device 900 illustrated in FIG. 9 may provide an auxiliary power source of the second super capacitor 922 to the memory device 930 through the first power line PL1. According to the user device 900 illustrated in FIG. 9, the number of power lines may be reduced.

10 is a block diagram illustrating a tenth embodiment of a user device according to the present invention. Referring to FIG. 10, the user device 950 includes a main power supply 960, an auxiliary power supply 970, and a memory device 980. The auxiliary power supply 970 includes first to Nth supercapacitors 971 to 973 and unidirectional elements 975 to 976. The memory device 980 includes a volatile memory 981, a nonvolatile memory 982, and a memory controller 983.

Referring to FIG. 10, the first to Nth supercapacitors 971 to 973 are connected to the first power line PL1. According to the user device 950 illustrated in FIG. 10, a plurality of supercapacitors may be used to increase the amount of auxiliary power supplied. The auxiliary power supply 970 illustrated in FIG. 10 may further include the switch or switch control circuit described above.

11 is a flowchart illustrating an operation of a user device according to the present invention. Hereinafter, referring to FIGS. 1 and 11, an operation principle of the user device 100 according to the present invention will be described.

When the user device 100 is powered on (S110), the user device 100 receives power from the main power supply device 110. The user device 100 performs a normal operation. Meanwhile, the auxiliary power supply 120 receives power from the main power supply 110 and charges the first and second supercapacitors 121 and 122 during the power up operation or the normal operation (S120).

When sudden power off occurs while using the user device 100 (S130), the user device 100 provides an auxiliary power source of the first super capacitor 121 (S140). The memory device 130 performs a sudden power off operation using an auxiliary power source. That is, a data backup operation from the volatile memory 131 to the nonvolatile memory 132 is performed.

The timer 128 calculates the discharge time of the first super capacitor 121 (S150), and discharges the second super capacitor 122 after a predetermined time (S160). The auxiliary power supply 120 provides the auxiliary power of the first and second super capacitors 121 and 122 step by step. The user device 100 may stably perform a power-off operation by using the auxiliary power provided in stages.

Meanwhile, the user device illustrated in FIGS. 2 to 8 may gradually provide an auxiliary power source using a switch control circuit such as a timer, a voltage detector, a charge detector, or the like.

The user device according to an embodiment of the present invention can be applied or applied to various products. A user device is not only an electronic device such as a personal computer, a digital camera, a camcorder, a mobile phone, an MP3, a PMP, a PDA, etc., but also a memory card, a USB memory, a semiconductor disk (for example, an SSD), a hard disk ( HDD) or the like.

12 is a block diagram illustrating an example of implementing a user device as a semiconductor disk device. Referring to FIG. 12, the semiconductor disk apparatus 1000 includes an SSD controller 1100 and nonvolatile memories 1210-1240. The SSD controller 1100 includes a CPU 1110, an ATA interface 1120, an SRAM cache 1130, a flash interface 1140, and an auxiliary power supply 1150.

In FIG. 12, a solid state drive (SSD) is shown as an example of the semiconductor disk apparatus 1000. SSD products, which are expected to replace hard disk drives (HDDs), are in the spotlight in the next-generation memory market. An SSD is a data storage device that uses memory chips such as flash memory to store data instead of a rotating dish used in a typical hard disk drive. SSDs have the advantage of being faster, more resistant to external shocks, and lower power consumption than mechanically moving hard disk drives.

The CPU 1110 receives a command from a host (not shown) and determines and controls whether to store data from the host in a flash memory or read and store stored data in the flash memory to a host.

The ATA interface 1120 exchanges data with the host side under the control of the CPU 1110 described above. The ATA interface 1120 patches commands and addresses from the host side and delivers the commands and addresses to the CPU 1110 through the CPU bus. Data input from the host or data to be transmitted to the host through the ATA interface 1120 is transferred through the SRAM cache 1130 without passing through the CPU bus under the control of the CPU 1110. Here, the ATA interface 1120 may be implemented as a SATA or PATA interface.

The SRAM cache 1130 temporarily stores cache data (or metadata) of the host and flash memories 1210-1240. The SRAM cache 1130 is also used to store a program to be operated by the central processing unit 1110. The SRAM cache 1130 may be regarded as a kind of buffer memory, and may not necessarily be configured as SRAM.

The flash interface 1140 exchanges data with the nonvolatile memories 1210-1240. The flash interface 1140 may be configured to support NAND flash memory, One-NAND flash memory, or multi-level flash memory. The flash interface 1140 and the nonvolatile memories 1210-1240 exchange control signals CE, CLE, ALE, WE, RE, and RB and data DQ.

The auxiliary power supply 1150 may be located inside or outside of the SSD controller 1100. In FIG. 10, the auxiliary power supply 1150 is located in the SSD controller 1100. The auxiliary power supply 1150 has the same configuration and operation principle as the previous embodiments. That is, the auxiliary power supply 1150 may gradually provide an auxiliary power supply for performing a data backup operation from the SRAM cache 1130 to the nonvolatile memory 1200 in a sudden power off state of the main power supply.

13 is a block diagram illustrating an example of implementing a user device as a semiconductor memory device. Referring to FIG. 13, the semiconductor memory device 2000 includes a memory controller 2100 and a flash memory 2200. The semiconductor memory device 2000 may include any storage device including volatile memory or nonvolatile memory, such as a memory card (eg, SD or MMC) or a removable removable storage device (eg, a USB memory). Include.

Referring to FIG. 13, the memory controller 2100 may include a central processing unit (CPU) 2110, a host interface 2120, a random access memory (RAM) 2130, a flash interface 2140, and an auxiliary power supply 2150. Include. The auxiliary power supply 2150 may be located in the memory controller 2100 or may be located outside. The auxiliary power supply 2150 has the same configuration and operating principle as the previous embodiments.

The semiconductor memory device 2000 is used in connection with a host. The semiconductor memory device 2000 exchanges data with the host through the host interface 2120, and exchanges data with the flash memory 2200 through the flash interface 2140. The semiconductor memory device 2000 receives internal power from a host to perform internal operations. The auxiliary power supply 2150 may gradually provide an auxiliary power supply for performing a data backup operation from the RAM 2130 to the flash memory 2200 when power from the host is suddenly cut off.

14 is a block diagram illustrating an example of implementing a user device as an electronic device. The electronic device 3000 may be implemented as a personal computer (PC) or a portable electronic device such as a notebook computer, a mobile phone, a personal digital assistant (PDA), a camera, or the like.

Referring to FIG. 14, the user device 3000 may include a semiconductor memory device 3100, a power supply device 3200, an auxiliary power supply device 3250, a central processing unit 3300, a RAM 3400, and a user interface 3500. It includes. The semiconductor memory device 3100 includes a flash memory 3110 and a memory controller 3120. The auxiliary power supply 3250 may provide auxiliary power in stages during sudden power off of the power supply 3200.

15 to 24 are structural diagrams schematically showing the shape and arrangement of the supercapacitor. The supercapacitor may be implemented in various forms such as a planar type, a can type, a coil type, and a slot type.

15 to 20 exemplarily show a planar type super capacitor. Referring to FIG. 15, the first super capacitor SC1 is stacked in parallel on the memory device. The second super capacitor SC2 is stacked in parallel on the first super capacitor SC1. 16 to 19 show that a plurality of super capacitors are arranged side by side on the same plane above the memory device. The planar supercapacitor may be disposed below, left, or right, in addition to the top side of the memory device. Further, as shown in FIG. 20, the memory device may be disposed in a groove of the memory device.

21 and 22 exemplarily show a can type super capacitor. Referring to FIG. 21, first and second supercapacitors SC1 and SC2 are disposed side by side on a memory device. Referring to FIG. 22, first and second supercapacitors SC1 and SC2 are disposed in both side grooves of the memory device. The can-type super capacitors may be arranged in various forms in addition to the arrangements shown in FIGS. 21 and 22.

In FIG. 23, a coil type super capacitor is exemplarily shown. Referring to FIG. 23, first and second supercapacitors SC1 and SC2 are disposed side by side on a memory device.

FIG. 24 exemplarily shows a slot type super capacitor. The slotted super capacitors SC1 and SC2 are removable.

 It will be apparent to those skilled in the art that the structure of the present invention can be variously modified or changed without departing from the scope or spirit of the present invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention provided they fall within the scope of the following claims and equivalents.

1 to 10 are block diagrams illustrating an exemplary user device according to the present invention.

11 is a flowchart illustrating an operation of a user device according to the present invention.

12 is a block diagram illustrating an example in which a user device is applied to a semiconductor disk device.

13 is a block diagram illustrating an example in which a user device is applied to a semiconductor memory device.

14 is a block diagram illustrating an example in which a user device is applied to an electronic device.

15 to 24 are structural diagrams schematically showing the shape and arrangement of the auxiliary power supply.

Claims (25)

A first power storage device for storing auxiliary power; A second power storage device for storing auxiliary power; And And a power control device for gradually providing auxiliary power of the first and second power storage devices in a sudden power off of an external power supply. The method of claim 1, And the first and second power storage devices are supercapacitors. The method of claim 1, The power control device includes a timer for calculating a time that the auxiliary power of the first power storage device is provided, and providing a secondary power of the second power storage device after a preset time. The method of claim 1, The power control device A first power line connected to the external power supply and configured to provide auxiliary power to the first power storage device; A second power line for providing auxiliary power of the second power storage device; A switch for switching the second power line; And And a timer for controlling the switch according to a time when the auxiliary power of the first power storage device is provided. The method of claim 4, wherein The power supply control device further includes a unidirectional element connected between the first and second power lines, and configured to block an auxiliary power supply of the second power storage device from being provided to the first power line. The method of claim 1, The power supply control apparatus includes a voltage detector for detecting an auxiliary power level of the first power storage device and providing auxiliary power of the second power storage device when a preset level is reached. The method of claim 1, The power control device A first power line connected to the external power supply and configured to provide auxiliary power to the first power storage device; A second power line for providing auxiliary power of the second power storage device; A switch for switching the second power line; And And a voltage detector controlling the switch in accordance with an auxiliary power level of the first power storage device. The method of claim 7, wherein The power supply control device further includes a unidirectional element connected between the first and second power lines, and configured to block an auxiliary power supply of the second power storage device from being provided to the first power line. The method of claim 1, The power control device may include a charge detector configured to detect a state of charge of the first and second power storage devices and to provide auxiliary power of the first and second power storage devices step by step according to the detection result. . The method of claim 9, And the charge detector externally informs the state of charge of the first and second power storage devices. A main power supply for providing main power; And In the case of sudden power off of the main power supply, including an auxiliary power supply for providing auxiliary power, The auxiliary power supply device includes a plurality of power storage devices and provides a step-by-step auxiliary power of the plurality of power storage devices. The method of claim 11, Further comprising a memory device including a nonvolatile memory and volatile memory, And the memory device backs up data from the volatile memory to the nonvolatile memory using the auxiliary power when the main power supply is suddenly powered off. 13. The method of claim 12, The auxiliary power supply device further includes a timer for calculating a time for which the auxiliary power of the first power storage device is provided and providing auxiliary power of the second power storage device to the memory device after a preset time. 13. The method of claim 12, After the auxiliary power supply of the first power storage device is provided, the auxiliary power supply device provides the auxiliary power of the second power storage device to the memory device if a job termination signal does not arrive from the memory device until a preset time elapses. The user device further comprises a timer to. 13. The method of claim 12, The auxiliary power supply may be configured to provide auxiliary power of the second power storage device to the memory device when the operation continuation signal arrives from the memory device after a preset time elapses after the auxiliary power of the first power storage device is provided. The user device further comprises a timer. 13. The method of claim 12, The auxiliary power supply device further includes a voltage detector for detecting an auxiliary power level of the first power storage device and providing auxiliary power of a second power storage device to the memory device when a preset level is reached. 13. The method of claim 12, The auxiliary power supply may provide the auxiliary power of the second power storage device to the memory device if a job termination signal does not arrive from the memory device until the auxiliary power supply of the first power storage device is provided and then falls to a predetermined level. The user device further comprises a voltage detector for. 13. The method of claim 12, The auxiliary power supply may be configured to provide auxiliary power of the second power storage device to the memory device when the auxiliary power supply of the first power storage device is provided and falls to a predetermined level, and when the operation continuation signal arrives from the memory device. The user device further comprising a voltage detector. 13. The method of claim 12, The auxiliary power supply device further comprises a charge detector for detecting a state of charge of the plurality of power storage devices, and providing the auxiliary power in stages according to the detection result. The method of claim 19, And a display device for informing the outside of the state of charge of the plurality of power storage devices. 13. The method of claim 12, The auxiliary power supply device, the volatile memory, and the nonvolatile memory are implemented as a semiconductor disk device (SSD). 13. The method of claim 12, The auxiliary power supply device, the volatile memory, and the nonvolatile memory are implemented as a memory card. 13. The method of claim 12, The auxiliary power supply device, the volatile memory, and the nonvolatile memory are implemented as a removable removable storage device. 13. The method of claim 12, The main power supply device, the auxiliary power supply device, and the memory device are computer implemented. 13. The method of claim 12, The main power supply device, the auxiliary power supply device, and the memory device are implemented as a portable electronic device.

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