KR20100066965A - Semiconductor device of stack structure of capacitor and diode and manufacturing method for semiconductor device of stack structure of capacitor and diode - Google Patents

Abstract

A method of manufacturing a semiconductor device having a capacitor and a diode stack structure according to an embodiment may include forming a well region on an upper surface of a semiconductor substrate; Forming a trench on the well region; Forming a second oxide layer inside the trench; Forming an isolation layer at the bottom of the trench; Forming a poly spacer on both sidewalls of the trench; Forming a third oxide layer on the exposed surface of the poly spacer; And forming a second nitride layer in the trench.

According to an embodiment, a PIP capacitor and a varactor diode may be implemented on a single semiconductor substrate in a stack structure through the same process.

Description

Semiconductor device of stack structure of capacitor and diode and manufacturing method for semiconductor device of stack structure of capacitor and diode

Embodiments relate to a semiconductor device having a capacitor and a diode stack structure and a method for manufacturing a semiconductor device having a capacitor and a diode stack structure.

Capacitors and diodes, in particular, PIP (Poly-silicon Insulator Poly-silicon) capacitors and varactor (varactor) diodes on a single semiconductor substrate, a semiconductor device in a stack structure through the same process has not been developed.

Therefore, when a circuit including a PIP capacitor and a varactor diode is to be implemented, the PIP capacitor and the varactor diode are implemented on separate semiconductor substrates through separate processes, and the implemented PIP capacitor and the varactor diode are implemented in a circuit configuration step. Should be connected at.

Therefore, the process becomes complicated, manufacturing time and manufacturing cost are high, and there is a problem that a circuit size becomes large.

The embodiment provides a semiconductor device capable of forming a capacitor and a diode together in a stack structure on a single semiconductor substrate, and a method of manufacturing the same.

A semiconductor device having a capacitor and a diode stack structure according to an embodiment may include a well region formed on an upper surface of a semiconductor substrate and including a trench; A second oxide layer formed on the sidewalls of the trench; An isolation layer formed on the bottom of the trench; A poly spacer formed on both sidewalls of the trench; A third oxide layer formed on the exposed surface of the poly spacer; And a second nitride layer formed in the trench on the third oxide layer.

A method of manufacturing a semiconductor device having a capacitor and a diode stack structure according to an embodiment may include forming a well region on an upper surface of a semiconductor substrate; Forming a trench on the well region; Forming a second oxide layer inside the trench; Forming an isolation layer at the bottom of the trench; Forming a poly spacer on both sidewalls of the trench; Forming a third oxide layer on the exposed surface of the poly spacer; And forming a second nitride layer in the trench.

According to the embodiment, the following effects are obtained.

First, a PIP capacitor and a varactor diode may be implemented on a single semiconductor substrate in a stack structure through the same process.

Second, therefore, when a circuit including a PIP capacitor and a varactor diode is to be implemented, the PIP capacitor and the varactor diode are implemented on separate semiconductor substrates through separate processes, and the PIP capacitor and the varactor diode are implemented. There is no need to connect at the stage.

Third, it is possible to simplify the production process of the circuit element, to reduce the manufacturing time and manufacturing cost, there is an effect that can minimize the size of the circuit element.

Hereinafter, a method of manufacturing a semiconductor device having a capacitor and a diode stack structure and a semiconductor device having a capacitor and a diode stack structure (hereinafter, referred to as a "semiconductor device according to an embodiment") will be described in detail with reference to the accompanying drawings. .

The capacitor according to the embodiment is a PIP capacitor and the diode is a varactor diode.

Hereinafter, in describing the embodiments, detailed descriptions of related well-known functions or configurations are deemed to unnecessarily obscure the subject matter of the present invention, and thus only the essential components directly related to the technical spirit of the present invention will be referred to. .

In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure may be "on" or "under" the substrate, each layer (film), region, pad or pattern. "On" and "under" include both being formed "directly" or "indirectly" through another layer. do. Also, the criteria for top, bottom, or bottom of each layer will be described with reference to the drawings.

1 is a side cross-sectional view showing the shape of a semiconductor device after the well region 115 is formed according to the embodiment.

First, a well region 115 is formed on a semiconductor substrate, for example, a semiconductor substrate 100 in a single crystal silicon wafer state, and the surface of the well region 115, that is, the semiconductor substrate ( The first oxide layer 110 is formed on the surface of the 100.

The first oxide layer 110 serves to protect the surface of the malleable semiconductor substrate 100 and to heal crystal defects, crystal defects, etc. generated on the substrate surface.

2 is a side cross-sectional view showing the shape of a semiconductor device after the second oxide layer 115 is formed according to the embodiment.

Subsequently, a photoresist pattern (not shown) for opening regions of the semiconductor substrate 100 spaced apart at regular intervals is formed on the first oxide layer 110, and the photoresist pattern is used as an etching mask. The trench T is formed by etching the layer 110 and the well region 115.

The trench T may be formed to have the same depth as the well region 115 or may be formed slightly deeper than the well region, for example, about 2000 micrometers deeper.

Thereafter, a second oxide layer 120 is formed on the semiconductor substrate 100 in the trench T and on sidewalls of the well region 115 through an oxidation process.

The second oxide layer 120 compensates for defects generated in the inner wall of the trench T during an etching process.

3 is a side cross-sectional view illustrating the shape of a semiconductor device after the first nitride layer 125 is formed according to the embodiment.

Subsequently, a first nitride layer is formed on the first oxide layer 110 formed on the surface of the semiconductor substrate 100 except for the trench T and the second oxide layer 120 formed inside the trench T. 125) is deposited to a predetermined thickness.

4 is a side cross-sectional view illustrating a shape of a semiconductor device after the device isolation layer 130 is formed according to an embodiment.

When the first nitride layer 125 is formed, the first nitride layer 125 formed on the surface of the semiconductor substrate 100 except for the trench T, and the first nitride formed on sidewalls of the trench T A photoresist pattern (not shown) for closing the layer 125 is formed, and the etching process is performed using the photoresist pattern as a mask.

When the second oxide layer 120 formed on the bottom of the trench T is exposed by the etching process, a field oxidation process is performed to form a field oxide layer, that is, a device isolation layer 130.

Thus, as shown in FIG. 4, the device isolation layer 130 may be formed on the bottom of the trench T and connected to the second oxide layer 120 on the sidewall of the trench T.

Thereafter, the first nitride layer 125 is removed.

5 is a side cross-sectional view showing the shape of a semiconductor device after the polysilicon layer 135 is formed according to the embodiment.

Subsequently, the trench T is buried to form a polysilicon layer 135 having a predetermined thickness on the device isolation layer 130, the second oxide layer 120, and the first oxide layer 110.

6 is a side cross-sectional view illustrating the shape of a semiconductor device after the third oxide layer 140 is formed according to the embodiment.

When the polysilicon layer 135 is formed, the polysilicon layer 135 is etched by performing an etching process, for example, a blanket etching process.

Thus, as shown in FIG. 6, the polysilicon layer 135 on the first oxide layer 110 and the polysilicon layer 135 on the device isolation layer 130 are removed and the trench T is removed. Only the polysilicon layer 135 remains on the second oxide layer 120 of the sidewalls.

For reference, the remaining polysilicon layer 135 forms a spacer and will be referred to as a "poly spacer".

When the poly spacer 135 is formed, an oxidation process is performed on the entire surface of the semiconductor substrate, and a third oxide layer 140 is formed on an open side of the poly spacer 135.

Thus, the poly spacer 135 has a shape surrounded by the second oxide layer 120, the third oxide layer 140, and the device isolation layer 130.

FIG. 7 is a side cross-sectional view illustrating the shape of a semiconductor device after the second nitride layer 150 is formed according to an embodiment.

As such, when the third oxide layer 140 is formed, the trench T is buried so that the second nitride layer 150 is stacked on the semiconductor substrate 100, and the surface of the semiconductor substrate 100 is formed. The second nitride layer 150 is planarized to expose the first oxide layer 110.

Therefore, the second nitride layer 150 remains only inside the trench T.

8 is a side cross-sectional view illustrating a completed structure of a semiconductor device having a capacitor and a diode stack structure according to an embodiment.

Subsequently, a wet etching process, for example, a wet etching process using phosphoric acid may be performed to thinly remove the surface of the second nitride layer 125 and to perform a silicide process.

Referring to FIG. 8, the region “A” functions as a varactor diode including the well region 115 and the poly spacer 135.

Also, the “B” region functions as a PIP capacitor including the poly spacer 135 on one side of the trench T, the second nitride layer 125, and the poly spacer 135 on the other side of the trench T.

The third oxide layer 140, the second nitride layer 135, and the third oxide layer 140 between the poly spacers 135 on both sidewalls of the trench T are oxide-nitride-oxide (ONO). ) To function as an insulating layer of the capacitor.

As such, according to the embodiment, by using a single trench structure through a single process, it is possible to simultaneously form a capacitor and a diode forming a stack structure.

Thereafter, an electrode is formed in the well region 115 and the poly spacer 135, and an insulation layer is formed and a metal wiring process is performed.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood that various modifications and applications other than those described above are possible. For example, each component specifically shown in the embodiments of the present invention can be modified and implemented. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is a side cross-sectional view showing the shape of a semiconductor device after the well region according to the embodiment is formed;

Fig. 2 is a side sectional view showing the form of a semiconductor device after the second oxide layer according to the embodiment is formed.

3 is a side cross-sectional view showing the form of a semiconductor device after the first nitride layer is formed according to the embodiment;

4 is a side cross-sectional view showing the shape of a semiconductor device after the device isolation layer is formed according to the embodiment.

5 is a side cross-sectional view showing the form of a semiconductor device after the polysilicon layer is formed according to the embodiment.

Fig. 6 is a side cross-sectional view showing the form of a semiconductor device after the third oxide layer according to the embodiment is formed.

FIG. 7 is a side sectional view showing the shape of a semiconductor device after the second nitride layer according to the embodiment is formed; FIG.

8 is a side cross-sectional view illustrating a completed form of a semiconductor device having a capacitor and a diode stack structure according to an embodiment;

Claims (18)

Forming a well region on the semiconductor substrate; Forming a trench on the well region; Forming a second oxide layer inside the trench; Forming an isolation layer at the bottom of the trench; Forming a poly spacer on both sidewalls of the trench; Forming a third oxide layer on the exposed surface of the poly spacer; And A method of manufacturing a semiconductor device having a capacitor and a diode stack structure comprising forming a second nitride layer in the trench. The method of claim 1, wherein the well region is formed. And forming a first oxide layer on a surface of the well region. The method of claim 1, wherein the device isolation layer is formed. Forming a first nitride layer having a predetermined thickness on an entire surface of the semiconductor substrate including the second oxide layer; Patterning the first nitride layer to expose a second oxide layer on the bottom of the trench, and forming the device isolation layer on the exposed second oxide layer; And The method of manufacturing a semiconductor device having a capacitor and a diode stack structure comprising the step of removing the first nitride layer. The method of claim 1, wherein the poly spacer is formed Forming a polysilicon layer having a predetermined thickness on the device isolation layer, the second oxide layer, and the semiconductor substrate; And And forming a polysilicon layer by remaining an polysilicon layer only on the second oxide layer of the trench sidewall by performing an etching process. The method of claim 4, wherein the etching process is performed. A method of manufacturing a semiconductor device having a capacitor and a diode stack structure, which is performed in a blanket manner. The method of claim 1, wherein the second nitride layer is formed Allowing the trench to be buried to form the second nitride layer on the semiconductor substrate; And And planarizing the second nitride layer to expose the semiconductor substrate. The method of claim 1, wherein the second nitride layer is formed Removing a portion of an upper side of the second nitride layer through the wet etching process; And Method of manufacturing a semiconductor device having a capacitor and a diode stack structure comprising the step of performing a silicide process. The method of claim 1, And a metal wiring process is performed such that the well region and the poly spacer form a varactor diode. The method of claim 1, And a metal wiring process is performed such that the poly spacer on the one side of the trench, the second nitride layer, and the poly spacer on the other side of the trench form a PIP capacitor. . 10. The method of claim 9, The third oxide layer next to the poly spacer on one side of the trench, the second nitride layer, and the third oxide layer next to the poly spacer on the other side of the trench form an ONO structure. Method of preparation. A well region formed on the semiconductor substrate and including a trench; A second oxide layer formed on the sidewalls of the trench; An isolation layer formed on the bottom of the trench; A poly spacer formed on both sidewalls of the trench; A third oxide layer formed on the exposed surface of the poly spacer; And And a capacitor and a diode stack structure including a second nitride layer formed in the trench on the third oxide layer. The method of claim 11, And a first oxide layer formed on the well region excluding the trench. The method of claim 11, The device isolation layer is a semiconductor device having a capacitor and a diode stack structure, characterized in that connected to the second oxide layer. The method of claim 11, The second nitride layer is a semiconductor device having a capacitor and a diode stack structure, characterized in that the upper portion is removed to be formed shallower than the trench, the silicide layer is formed in the removed portion. The method of claim 11, An electrode formed in the well region and the poly spacer; An insulating layer formed on the entire surface of the semiconductor substrate; And a metal wiring connected to the electrode, the semiconductor device having a capacitor and a diode stack structure formed on the insulating layer. The method of claim 15, wherein the metal wiring And the well region and the poly spacer to form a varactor diode circuit. The method of claim 15, wherein the metal wiring And a poly spacer on one side of the trench, the second nitride layer, and a poly spacer on the other side of the trench to form a PIP capacitor circuit. The method of claim 15, The third oxide layer next to the poly spacer on one side of the trench, the second nitride layer, and the third oxide layer next to the poly spacer on the other side of the trench form an ONO structure. .

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