KR20100012671A - Method for manufacturing image sensor - Google Patents

Abstract

In another embodiment, a method of manufacturing an image sensor includes forming a readout circuitry on a substrate; Forming an interlayer insulating layer on the substrate; Forming a wire on the interlayer insulating layer, the wiring being electrically connected to the lead-out circuit; Forming an amorphous silicon image sensing device on the wiring; And crystalline siliconizing the amorphous silicon image sensing unit.

Description

Method for Manufacturing Image Sensor

An embodiment relates to a method of manufacturing an image sensor.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is divided into a charge coupled device (CCD) image sensor and a CMOS image sensor (CMOS). .

In the prior art, a photodiode is formed on a substrate by ion implantation. However, as the size of the photodiode gradually decreases for the purpose of increasing the number of pixels without increasing the chip size, the image quality decreases due to the reduction of the area of the light receiver.

In addition, since the stack height is not reduced as much as the area of the light receiving unit is reduced, the number of photons incident on the light receiving unit is also decreased due to diffraction of light called an airy disk.

One alternative to overcome this is to deposit photodiodes with amorphous Si, or read-out circuitry using wafer-to-wafer bonding such as silicon substrates. And photodiodes are formed on the lead-out circuit (hereinafter referred to as "three-dimensional image sensor"). The photodiode and lead-out circuit are connected via a metal line.

On the other hand, according to the prior art, there is a method of depositing amorphous silicon (a-Si) and then using it as a photodiode after metal wiring. The problem is that since Si is an amorphous structure, leakage occurs frequently, resulting in dark. The property is bad . For reference, in order to directly deposit polysilicon (Poly Si), a high temperature condition of 1000 ° C. or higher is required, which causes a problem in the underlying metal, and the transistor also has a problem in that Vt / Id is misaligned, thus depositing a-Si. .

In addition, according to the related art, since both the source and the drain of the both ends of the transfer transistor are doped with a high concentration of N-type, charge sharing occurs. When charge sharing occurs, the sensitivity of the output image is lowered and image errors may occur.

In addition, according to the related art, a dark current is generated between the photodiode and the lead-out circuit and the photocharge is not smoothly moved, and saturation and sensitivity are decreased.

Embodiments provide a method of manufacturing an image sensor capable of making an image sensing unit of amorphous silicon formed on a readout circuit by using laser annealing with polysilicon or crystalline silicon.

In addition, the embodiment is to provide a method of manufacturing an image sensor that can increase the charge factor (Charge Sharing) does not occur.

In addition, the embodiment of the present invention manufactures an image sensor capable of minimizing dark current sources and preventing saturation and degradation of sensitivity by making a smooth movement path of photo charge between the photodiode and the lead-out circuit. To provide a method.

In another embodiment, a method of manufacturing an image sensor includes forming a readout circuitry on a substrate; Forming an interlayer insulating layer on the substrate; Forming a wire on the interlayer insulating layer, the wiring being electrically connected to the lead-out circuit; Forming an amorphous silicon image sensing device on the wiring; And crystalline siliconizing the amorphous silicon image sensing unit.

According to the method of manufacturing an image sensor according to the embodiment, leakage current, which was a problem of amorphous silicon (a-Si), may be improved by polycrystalline silicon or crystalline siliconized amorphous silicon by laser annealing.

In addition, according to the embodiment, by increasing the number of laser annealing to three times, a more uniform Si lattice structure (Crystalline Si) may be formed to improve dark current.

In addition, according to the embodiment, the device may be designed such that there is a potential difference between the source and the drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge.

In addition, according to the embodiment, the charge connection region is formed between the photodiode and the lead-out circuit to create a smooth movement path of the photo charge, thereby minimizing the dark current source, and reducing saturation and sensitivity. It can prevent.

Hereinafter, a method of manufacturing an image sensor according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

The present invention is not limited to the CMOS image sensor, and may be applied to an image sensor requiring a photodiode.

In an exemplary embodiment, the image sensing unit 210 may be a photodiode, but is not limited thereto. The image sensing unit 210 may be a photogate, a combination of a photodiode and a photogate, and the like.

(First embodiment)

Hereinafter, a method of manufacturing the image sensor according to the first embodiment will be described with reference to FIGS. 1 to 4.

1 is a schematic diagram of a substrate on which an interconnect 150, a ground line 157, and a pad 159 are formed on an interlayer insulating layer 160, and FIG. 2 is a lead-out circuit 120 and an electrical junction region 140. ) And the substrate 100 on which the wiring 150 is formed. A description with reference to FIG. 2 is as follows.

First, as shown in FIG. 2, the substrate 100 having the wiring 150 and the readout circuit 120 is prepared. For example, an isolation region 110 is formed on the second conductive substrate 100 to define an active region, and a readout circuit 120 including a transistor is formed in the active region. For example, the readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. can do. Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed. In addition, according to the embodiment, the noise can be improved by adding a noise removing circuit (not shown).

The forming of the lead-out circuit 120 on the substrate 100 may include forming an electrical junction region 140 on the substrate 100 and connecting the wiring 150 to an upper portion of the electrical junction region 140. The method may include forming a first conductive connection region 147.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 2, but is not limited thereto. The substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device can be designed such that there is a voltage difference between the source / drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, the embodiment forms the electrical junction region 140 on the substrate 100 on which the readout circuit 120 is formed as shown in FIG. 2 so that there is a voltage difference between the sources / drains across the transfer transistors Tx 121. Full dumping of the charge may be possible.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

In detail, the electrons generated by the photodiode 210 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on to be converted into a voltage.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the FD (131) node becomes Vdd-Rx Vth, the charge sharing is performed due to the potential difference between both ends of the Tx (131). Electrons generated from the photodiode 210 above the chip may be fully dumped to the FD 131 node.

That is, in the embodiment, the reason why the P0 / N- / P-well junction is formed instead of the N + / P-well junction in the silicon sub, which is the substrate 100, is P0 / N during the 4-Tr APS Reset operation. Since-voltage is applied to N- (143) at-/ P-well junction, and ground voltage is applied to P0 (145) and P-well (141), P0 / N- / P-well double junction Pinch-Off occurs as in the BJT structure. This is called pinning voltage. Therefore, a voltage difference is generated in the source / drain at both ends of the Tx 121, and thus the photocharge is completely dumped from the N-well to the FD through the Tx at the Tx On / Off operation to prevent the charge sharing phenomenon.

Therefore, unlike the case where the photodiode is simply connected by N + junction as in the prior art, the embodiment can avoid problems such as degradation of saturation and degradation of sensitivity.

Next, according to the embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit to make a smooth movement path of the photo charge, thereby minimizing the dark current source and saturation ( Saturation) can be prevented and degradation of sensitivity.

To this end, the first embodiment may form an n + doped region as the first conductive connection region 147 for ohmic contact on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, in order to minimize the first conductive connection region 147 from becoming a leakage source, the width of the first conductive connection region 147 may be minimized. To this end, the embodiment may proceed with a plug implant after etching the first metal contact 151a, but is not limited thereto. For example, as another example, an ion implantation pattern (not shown) may be formed and the first conductive connection region 147 may be formed using the ion implantation mask as an ion implantation mask.

That is, as in the first embodiment, the reason for locally N + doping only to the contact forming part is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

Next, the interlayer insulating layer 160 may be formed on the substrate 100, and the wiring 150 may be formed. The wiring 150 may include a first metal contact 151a, a first metal 151, a second metal 152, a third metal 153, and a fourth metal contact 154a, but is not limited thereto. It is not.

Next, as shown in FIG. 3, a lower electrode 205 is formed on the wiring 150.

For example, a metal layer (not shown) may be formed on the wiring 150 and the interlayer insulating layer 160, and the lower electrode 205 may be formed by etching the metal layer leaving portions corresponding to the wiring 150. Can be. For example, at least one metal of Cr, Ti, TiN, Ta, TaN, Al, and W is deposited on the wiring 150 and the interlayer insulating layer 160 by about 50 to 2,000 microseconds.

Thereafter, the photolithography process may be performed, and the lower electrode 205 may be formed by etching the metal layer leaving a portion corresponding to the wiring 150. For example, the lower electrode may be formed by dry etching based on Cl ₂ and O ₂ , but is not limited thereto.

Next, an image sensing unit 210a may be formed on the lower electrode 205. For example, the amorphous silicon image sensing unit 210a including the N layer 212, the I layer 214, and the P layer 216 may be formed.

Next, as shown in FIG. 4, the amorphous silicon image sensing unit 210a is crystalline siliconized.

For example, laser annealing may be performed for several tens of ms to make the amorphous silicon (a-Si) image sensing unit 210a into the crystalline silicon (c-Si) image sensing unit 210c.

At this time, since the laser annealing is irradiated for several tens of ms, heat is not transferred to the wiring 150 and the lower readout circuit 120 of the substrate 100.

The first embodiment of the laser annealing in the example is not advance to about ^{600mJ / cm 2 ~ 1200mJ / cm} 2 of energy, but is not limited thereto.

When the amorphous silicon (a-Si) image sensing unit 210a is recrystallized by the crystalline silicon (c-Si) image sensing unit 210c, the amorphous silicon (a-Si) image sensing unit 210a has a polysilicon lattice structure and the amorphous silicon (a-Si) Leakage current, which was a problem, can be improved.

In addition, the first embodiment may repeat the laser annealing a plurality of times to further improve the image characteristics. For example, laser annealing may be repeated three times, but is not limited thereto.

Thereafter, an upper electrode (not shown) may be formed on the crystalline silicon image sensing unit 210c, and an additional wiring process such as a reset line and a color filter process may be performed.

Meanwhile, in the first exemplary embodiment, an etching process of separating the image sensing unit for each pixel may be performed to fill an etched portion between pixels with an inter-pixel insulating layer (not shown) to separate the pixels for each pixel.

(2nd Example)

5 is a cross-sectional view of the image sensor according to the second embodiment, which is a detailed view of a substrate on which the lead-out circuit 120, the electrical junction region 140, and the wiring 150 are formed.

The second embodiment can employ the technical features of the first embodiment.

Meanwhile, unlike the first embodiment, the second embodiment is an example in which the first conductive connection region 148 is formed on one side of the electrical bonding region 140.

According to an embodiment, an N + connection region 148 for ohmic contact may be formed in the P0 / N− / P− junction 140, where the Ricky is formed in the process of forming the N + connection region 148 and the M1C contact 151a. A Leakage Source may occur. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. The crystal defects generated during the contact forming process in the electric field become a liquid source.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-field by the N + / P0 junction 148/145 is added, which may also be a leakage source. .

Accordingly, in the second embodiment, the first contact plug 151a is formed in an active region formed of the N + connection region 148 without being doped with a P0 layer, and a layout for connecting the first contact plug 151a with the N-junction 143 is provided. present.

According to the second embodiment, the E-Field of the Si surface does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 to 4 are process cross-sectional views of a method of manufacturing the image sensor according to the first embodiment.

5 is a sectional view of an image sensor according to a second embodiment;

Claims (10)

Forming a readout circuitry on the substrate; Forming an interlayer insulating layer on the substrate; Forming a wire on the interlayer insulating layer, the wiring being electrically connected to the lead-out circuit; Forming an amorphous silicon image sensing device on the wiring; And And crystalline siliconizing the amorphous silicon image sensing unit. According to claim 1, Crystallizing the amorphous silicon image sensing unit The crystalline siliconization method of the amorphous silicon image sensing unit by laser annealing, characterized in that the manufacturing method. The method of claim 2, Crystallizing the amorphous silicon image sensing unit The crystalline siliconization method of the amorphous silicon image sensing unit through a plurality of laser annealing, characterized in that the manufacturing method of the image sensor. According to claim 1, And forming an electrical junction region electrically connected to the lead-out circuit on the substrate. The method of claim 4, wherein Forming the electrical junction region is Forming a first conductivity type ion implantation region in the substrate; And And forming a second conductivity type ion implantation region on the first conductivity type ion implantation region. The method of claim 4, wherein The lead out circuit is A method of manufacturing an image sensor, characterized in that there is a voltage difference between a source and a drain on both sides of a transistor. The method of claim 4, wherein The electrical junction region is Method of manufacturing an image sensor, characterized in that the PN junction (junction). The method of claim 4, wherein And forming a first conductive connection region between the electrical junction region and the wiring. The method of claim 8, The first conductivity type connection region And an electrical connection with the wirings formed on the electrical junction region. The method of claim 8, The first conductivity type connection region The method of manufacturing an image sensor, characterized in that formed on the one side of the electrical junction region is electrically connected to the wiring.

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