KR20090118333A - Solar cell and its formation method - Google Patents

Abstract

A solar cell is formed on a front surface of which an N-type electrode and a P-type electrode receive sunlight. The solar cell includes a crystalline silicon substrate of a first conductivity type and an amorphous silicon layer of a second conductivity type on the crystalline silicon substrate. A shallow depth of pn heterojunction is formed adjacent to the interface between the first conductive silicon substrate and the second conductive amorphous silicon layer. The first electrode is provided in the groove of the front surface.

Description

SOLAR CELL AND FORMING THE SAME

The present invention relates to a solar cell, and more particularly, to a solar cell having electrodes formed on a front surface thereof.

Solar cells generate electrons and holes by the light from outside, and electrons move to n-type semiconductors and holes move to p-type semiconductors by electric fields generated at pn junctions. .

In general, at least one of the P-type electrode and the N-type electrode of the solar cell is provided on the back surface of the substrate. If the metal electrode covers the front surface of the substrate, the shading loss caused by not absorbing sunlight by the area of the electrode is increased. Correspondingly, U.S. Patent Nos. 4,748,130 and 4,726,850 disclose a buried contact solar cell (BCSC) with a recessed electrode structure, which is one of high efficiency solar cell structures in order to increase the efficiency of the solar cell. The recessed electrode structure is formed in a form in which the metal electrode on the front surface is recessed by forming a groove in the front surface of the solar cell and filling the inside of the groove with a conductive material.

The present invention is to provide a solar cell having a high energy efficiency and a method of forming the same.

Embodiments of the present invention provide a solar cell. In one embodiment, the solar cell is a semiconductor substrate of the first conductivity type; A second conductive semiconductor layer on the first conductive semiconductor substrate; And a pn junction adjacent to an interface between the first conductive semiconductor substrate and the second conductive semiconductor layer. The depth of the pn junction may have a shallow junction of less than 1000Å.

The pn junction may be provided to the semiconductor substrate adjacent to the interface.

The semiconductor substrate has a second conductivity type interface region provided in an upper portion of the semiconductor substrate in contact with the semiconductor layer of the second conductivity type and a base of a first conductivity type provided in an upper portion of the semiconductor substrate. It can include an area. The interface region may have a lower impurity ion concentration than the semiconductor layer. The pn junction may be formed at an interface between the interface region and the base region.

In another embodiment, the solar cell includes a crystalline silicon substrate having a first region of the first conductivity type of the lower portion and a second region of the second conductivity type of the upper portion, the pn junction is formed at the interface therebetween; And an amorphous silicon layer of a second conductivity type on the crystalline silicon substrate. The second region may have a lower impurity concentration than the amorphous silicon layer.

In another embodiment, the solar cell comprises a semiconductor substrate having a front surface for receiving sunlight and a rear surface facing the front surface; A pn junction formed in the semiconductor substrate; And a first electrode and a second electrode provided on the front surface of the semiconductor substrate. Heights of the lower surface of the first electrode and the first electrode may be different from each other.

The P-type electrode may have a structure recessed in a groove formed on the front surface of the semiconductor substrate.

In another embodiment, the solar cell comprises a first conductive semiconductor substrate having a front surface and a rear surface facing the front surface; A second conductive semiconductor layer on an entire surface of the first conductive semiconductor substrate; An anti-reflection film on the second conductive semiconductor layer; A pn junction adjacent to an interface between the first conductive semiconductor substrate and the second conductive semiconductor layer; A first electrode formed in a first groove exposing the first conductive semiconductor substrate; And a second electrode formed in a second groove exposing the second conductive semiconductor layer and having a depth smaller than that of the first groove.

The lower surface of the second groove may be higher than the upper surface of the semiconductor substrate of the first conductivity type.

The solar cell may further include an insulating film spacer. The insulating layer spacer may be provided on the sidewall of the first groove to expose the semiconductor substrate of the first conductivity type. The insulating layer spacer may prevent the direct contact between the second conductive semiconductor layer and the first electrode by separating the first electrode from the second conductive semiconductor layer. The height of the insulating layer spacer may be at least the depth of the pn junction.

The first groove may have an extension groove extending toward the rear surface and coplanar with the sidewall of the insulation spacer.

The solar cell may further include a protective insulating layer covering the entire rear surface of the first conductive semiconductor substrate.

Embodiments of the present invention provide a method of forming a solar cell. In one embodiment, the method comprises forming an amorphous semiconductor layer of a second conductivity type on a semiconductor substrate of a first conductivity type; And performing a heat treatment process to form a pn junction adjacent to an interface between the first conductive semiconductor substrate and the second conductive amorphous semiconductor layer.

Forming the amorphous semiconductor layer may include forming an undoped amorphous semiconductor layer and subsequently forming an amorphous semiconductor layer doped with impurities of a second conductivity type.

In another embodiment, the method includes forming a second conductive semiconductor layer on a front surface of a first conductive semiconductor substrate having a front surface and a back surface facing the front surface; Forming a pn junction adjacent to an interface between the first conductive semiconductor substrate and the second conductive semiconductor layer; Forming an anti-reflection film on the second conductive semiconductor layer; Forming a protective insulating film on a rear surface of the first conductive semiconductor substrate; Forming a first electrode in a first groove exposing the first conductive semiconductor substrate; And exposing the second conductive semiconductor layer and forming a second electrode in a second groove having a depth smaller than that of the first groove.

Forming the first electrode comprises: forming a first mask pattern on the anti-reflection film; And etching the anti-reflection film, the second conductive semiconductor layer, and the first conductive semiconductor substrate by using the first mask pattern to form a first groove having a depth equal to or greater than the depth of the pn junction. It may include.

The first groove may be formed by: etching the second conductive semiconductor layer and the first conductive semiconductor substrate using the first mask pattern to form a first groove having a depth equal to or greater than a depth of the pn junction. To form; The first electrode is spaced apart from the second conductive semiconductor layer on the sidewall of the first groove to prevent direct contact between the second conductive semiconductor layer and the first electrode. Forming an insulating film spacer exposing the semiconductor substrate; The method may include forming an extension groove by additionally etching the first conductive semiconductor substrate using the first mask pattern and the insulating layer spacer.

Forming the second electrode comprises: forming a second mask pattern covering the first groove and exposing the anti-reflection film in a portion spaced from the first groove; The second anti-reflection film and the second conductive semiconductor layer may be etched using the second mask pattern to form second grooves shallower than a depth of the pn junction.

According to the present invention, since the P-type electrode and the N-type electrode is formed on the front surface to receive sunlight, the movement distance of the electrons can be minimized. Since no backside process is required, solar cells can be formed using conventional semiconductor processes and manufacturing costs can be reduced. Since the heterojunction between the amorphous silicon layer and the crystalline silicon substrate is used, light of a wider wavelength band can be absorbed and energy efficiency can be increased. On the other hand, since both the P-type electrode and the N-type electrode is provided on the front of the solar cell, the connection between the electrodes of the solar cells when the solar cell module configuration can be easier.

Objects, other objects, features and advantages of the present invention will be readily understood through the following preferred embodiments associated with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art.

In the present specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate or a third film may be interposed therebetween. In addition, in the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical contents. In addition, although various terms, films, and the like are used to describe various regions, films, and the like in various embodiments of the present specification, these regions and films should not be limited by these terms. . These terms are only used to distinguish any given region or film from other regions or films. Each embodiment described and illustrated herein also includes its complementary embodiment.

1 and 2, a solar cell according to embodiments of the present invention is described. The solar cell may include a first conductive semiconductor substrate 110 having a front surface receiving sunlight and a rear surface facing the front surface. The front surface of the semiconductor substrate 110 may be textured to have an uneven structure. The uneven structure may have various shapes including an inverted pyramid pattern regularly. Forming the uneven structure is to improve the absorption rate of the incident light compared to the flat structure. The solar cell may further include a second conductive semiconductor layer 120 opposite to the first conductive type on the semiconductor substrate 110 and an anti-reflection film 131 on the semiconductor layer 120.

 The semiconductor substrate 110 may be made of monocrystalline silicon, and the semiconductor layer 120 may be made of amorphous silicon. The first conductivity type may be P type, and the second conductivity type may be N type. The pn junction PN may be provided adjacent to an interface between the first conductive semiconductor substrate 110 and the second conductive semiconductor layer 120. The pn junction may be provided to the semiconductor substrate 110 adjacent to the interface. The pn junction may be a shallow junction (shallow junction), the depth is preferably several kV to 1000 kPa, for example 600 kPa. Because of this, the travel distance of the electrons is minimized and the loss of electrons by recombination can be reduced.

The semiconductor layer 120 may be doped with a high concentration of impurity ions of the second conductivity type, for example, phosphorus (P). The semiconductor layer 120 may have an impurity ion concentration of about 10 ¹⁹ to 10 ²¹ / cm 3. The first conductive semiconductor substrate 110 has an interface region 110a doped with a high concentration of impurity ions of the second conductivity type in an upper portion thereof in contact with the second conductive semiconductor layer 120. Can have The interface region 110a may be formed by diffusing impurity ions of the second conductive semiconductor layer 120 to the first conductive semiconductor substrate 110. Accordingly, the semiconductor substrate 110 may include a base region 110b of the first conductivity type in a lower portion thereof and an interface region 110a of the second conductivity type in an upper portion thereof. Can be. The pn junction may be provided between the interface region 110a of the second conductivity type and the base region 110b of the first conductivity type. The interface region 110a may have a lower impurity ion concentration than the semiconductor layer 120.

The interface region 110a and the semiconductor layer 120 may be referred to as a second conductive region 122. The concentration of the impurity in the second conductive region 122 may increase with height. Furthermore, since the present invention uses a heterojunction between the second conductive amorphous semiconductor layer 120 and the first conductive crystalline semiconductor substrate 110, light of a wider wavelength range can be received.

When the optical thickness of the anti-reflection film 131 becomes 1/4 wavelength of incident light, the antireflective coating may be performed, and the reflectance may be further reduced. The anti-reflection film 131 may be formed of a two-layer film to reduce the thickness error caused by a single film. The anti-reflection film 131 may be a silicon oxide film, a silicon nitride film, or a stacked film thereof. The anti-reflection film 131 may protect the entire surface of the solar cell.

The solar cell has a first electrode 141 and a second conductive semiconductor layer 120 electrically connected to a front surface of the semiconductor substrate 110 and to a base region 110b of the first conductive semiconductor substrate. It may further include a second electrode 143 electrically connected to). The first electrode 141 may be formed in a first trench 116 exposing the base region 110b of the first conductivity type semiconductor substrate 110. The second electrode 143 may be formed in the second groove 118 exposing the second conductive semiconductor layer 120 and having a depth smaller than that of the first groove 116. The bottom surface of the second groove may be higher than the top surface of the semiconductor substrate 110 so as not to expose the semiconductor substrate 110. The depth of the first groove is sufficient to be smaller than the thickness of the semiconductor substrate 110, but is preferably about 2/3 or less of the thickness. The grooves may have a width of about 1 μm or less, for example about 0.3 μm. Accordingly, since the widths of the electrodes formed in the grooves are narrowed, the shading loss for the sunlight incident on the front surface can be reduced.

The insulating layer spacer 115 may be provided on the sidewall of the upper 113 of the first groove 116 to expose the base region 110b of the first conductive semiconductor substrate 110. The insulating layer spacer 115 may be a silicon oxide layer, a silicon nitride layer, or a stacked layer thereof. The insulating layer spacer 115 is spaced apart from the second conductive semiconductor layer 120 to separate the first electrode 141 from the second conductive semiconductor layer 120 and the first electrode 141. Direct contact can be prevented. The bottom surface of the insulating film spacer 115 may be at least lower than the pn junction surface. The first groove 116 may have an extending groove 114 coplanar with the sidewall of the insulating film spacer 115 and extending toward the rear surface.

In order to reduce contact resistance between the first electrode 141 and the base region 110b of the first conductive semiconductor substrate 110, a first conductive impurity layer having a high concentration on the sidewall and the bottom surface of the first groove. 117 may be provided. The first conductivity type impurity layer 117 may be provided in the first conductivity type semiconductor substrate 110, that is, the extension groove 114, exposed by the insulating layer spacer 115.

The first electrode 141 and the second electrode 143 may be a laminated film of Al, Cu, Ni, W, Ti, TiN, WN, or a metal silicide film. Preferably, the first electrode 141 and the second electrode 143 may be Ti / TiN / Al or Ti / TiN / W. The first electrode and the second electrode may be arranged in a finger shape.

As the first electrode 141 is formed in the first groove 116, the contact area between the first electrode and the base region 110b of the semiconductor substrate 110 may be increased. Moreover, since the first groove has a long length, the contact area can be further increased. Contact resistance and sheet resistance can be reduced. Since electrons may be easily captured by the first electrode 141, energy efficiency may be increased.

The back surface impurity layer 111 may be provided on the back surface of the semiconductor substrate 110. The back surface impurity layer 111 may serve as a back surface field (BSF) to improve current collection. The back surface impurity layer 111 may be doped with a high concentration of impurities of a first conductivity type. According to the spirit of the present invention, since both the first electrode and the second electrode are provided on the front surface of the semiconductor substrate, the back field impurity layer 111 may not be formed. A protective insulating layer 132 may be provided to cover the entire back surface of the first conductivity type semiconductor substrate 110, for example, the entire back surface impurity layer 111. The protective insulating layer 132 may be made of the same material as the insulating layer spacer 115. The protective insulating layer 132 may be incident on the front surface of the semiconductor substrate 110 to prevent the light passing through the semiconductor substrate from being transmitted through the rear surface of the semiconductor substrate. That is, the protective insulating layer 132 may reflect the light to the front surface. Light reflected by the protective insulating layer 132 may be reflected back by the anti-reflection film 131 and may be confined within the semiconductor substrate. Unlike general solar cells, since the first electrode and the second electrode are provided on the front surface of the semiconductor substrate, a portion exposing the semiconductor substrate to the protective insulating layer 132 may not be generated. Since the light is reflected on the entire back surface of the semiconductor substrate, the reflectance can be increased more efficiently.

A solar cell forming method according to embodiments of the present invention is described. Referring to FIG. 3, impurity ions of the first conductivity type, for example boron, are heavily doped on the front and rear surfaces of the first conductivity type semiconductor substrate 110. The boron may be heat treated by a diffusion process using a furnace to form the back surface impurity layer 111.

Referring to FIG. 4, the front surface of the semiconductor substrate may be textured to have the uneven structure 112. By the same process, the back surface impurity layer 111 on the front surface of the semiconductor substrate may be removed. The uneven structure 112 may have various shapes including an inverse pyramid pattern. The uneven structure 112 may be formed by a well-known process including a plasma etching method, a mechanical scribing method, a photolithography method, and a chemical etching method. For example, an uneven structure of an inverted pyramid pattern may be formed on the entire surface of the semiconductor substrate 110 by a photolithography process. After forming an oxide film (not shown) to be used as a sacrificial layer on the entire surface of the semiconductor substrate 110, a photoresist pattern (not shown) is formed on the oxide film. After patterning the oxide film using the photoresist pattern as a mask and removing the photoresist pattern, the entire surface of the semiconductor substrate is textured using the patterned oxide film as a mask.

Referring to FIG. 5, an amorphous semiconductor layer 120 doped with a high concentration of impurity ions of a second conductivity type is formed on the semiconductor substrate 110 on which the uneven structure 112 is formed. The doping concentration may be approximately 10 ¹⁹ ~ 10 ²¹ / ㎤. It is preferable that the thickness of the amorphous semiconductor layer 120 is several kPa to 1000 kPa, for example, 600 kPa. For example, a thin, undoped amorphous semiconductor layer can be initially formed, and a successively doped amorphous semiconductor layer can be formed. The undoped amorphous semiconductor layer may be formed by, for example, PECVD or LPCVD using silane (SiH 4) and hydrogen gas. The doped amorphous semiconductor layer may be formed by, for example, PECVD or LPCVD using silane (SiH 4), phosphine (PH 4) and hydrogen gas.

Thereafter, a heat treatment process is performed to perform an impurity ion of the second conductivity type, for example, phosphorus (P), of the doped amorphous semiconductor layer and the semiconductor substrate of the first conductivity type below the doped amorphous semiconductor layer. May be diffused to 110. An interface region 110a doped with impurity ions of the second conductivity type may be formed on an upper portion of the semiconductor substrate 110. The lower portion of the semiconductor substrate 110 may be referred to as the base region 110b of the first conductivity type. A pn junction PN is formed adjacent to an interface between the first conductive semiconductor substrate 110 and the second conductive amorphous semiconductor layer 120. That is, the pn junction may be formed at an interface between the base region 110b of the first conductivity type and the interface region 110a of the second conductivity type. Since the amorphous semiconductor layer 120 is formed of an undoped amorphous semiconductor layer and a doped amorphous semiconductor layer thereon, the amorphous semiconductor layer 120 may have a difference in impurity concentration even after the heat treatment process.

Meanwhile, unlike the method described with reference to FIG. 4, the uneven structure 112 may be formed by growing the uneven structure 112 on the amorphous semiconductor layer 120. For example, the uneven structure 112 may be formed by growing an HSG film by a well-known process. Alternatively, the uneven structure 112 may be formed by growing a zinc oxide film ZnO on the amorphous semiconductor layer 120. The zinc oxide film may have a rough surface. Since the zinc oxide film is a transparent conductive film, a current can be uniformly spread from the second electrode to the entire upper surface of the second conductive semiconductor layer 120.

Referring to FIG. 6, an anti-reflection film 131 may be formed on the second conductive semiconductor layer 120. The anti-reflection film 131 may be a silicon oxide film, a silicon nitride film, or a stacked film thereof. The anti-reflection film 131 may be formed by a PECVD process.

Referring to FIG. 7, an upper portion 113 of the first groove is formed to expose the first conductive semiconductor substrate 110. The upper portion 113 of the first groove may be formed by forming a first mask pattern (eg, a photoresist layer pattern) covering the anti-reflection film 131 and performing a dry etching process. The width of the upper portion of the first groove 113 may be 1 μm or less, for example, 0.3 μm. The first groove may have a depth greater than or equal to the depth of the pn junction PN.

An insulating layer spacer 115 is formed on sidewalls of the upper side 113 of the first groove to expose the semiconductor substrate 110. The insulating layer spacer 115 may be a silicon oxide layer, a silicon nitride layer, or a stacked layer thereof. The insulating film spacer 115 may be formed by, for example, forming an insulating film that conformally covers the first groove by LPCVD and performing a well-known anisotropic etching process. A protective insulating layer 132 may be formed on the rear surface of the semiconductor substrate 110 during the formation of the insulating layer.

Referring to FIG. 8, an extension groove 114 may be formed by additionally etching the first conductive semiconductor substrate 110 using the first mask pattern (not shown) and the insulating layer spacer 115. . The first groove 116 may include an upper portion 113 of the first groove and the extension groove 114. The depth of the first groove 116 may be 2/3 or less of the thickness of the semiconductor substrate 110. An impurity layer 117 of the first conductivity type may be formed on the first conductivity type semiconductor substrate exposed to the extension groove 114.

Referring to FIG. 9, a second mask pattern (not shown) is formed to cover the first groove 116 and expose the anti-reflection film 131 in a portion spaced apart from the first groove. The anti-reflection film 131 may be etched using the second mask pattern to form a second groove 118 exposing the second conductive semiconductor layer 120 and shallower than a depth of the pn junction. . The second groove 118 may be deeper than or the same as an upper surface of the second conductive semiconductor layer 120 and shallower than an upper surface of the first conductive semiconductor substrate 110.

Referring to FIG. 1 again, a metal film (not shown) filling the first groove 116 and the second groove 118 is formed, and the metal film is patterned to form the first electrode 141 and the second electrode ( 143 may be formed. The metal film may be a laminated film of Al, Cu, Ni, W, Ti, TiN, WN, or a metal silicide film. Preferably, the metal film may be Ti / TiN / Al or Ti / TiN / W. After the formation of the first electrode and the second electrode, a hydrogen heat treatment process may be added. The insulating layer spacer 115 may prevent the direct contact between the second conductive semiconductor layer and the first electrode by separating the first electrode 141 from the second conductive semiconductor layer 120. .

Referring to Fig. 10, a solar power generation system using the solar cell of the present invention is described. Since the solar cell 100 according to the present invention generally outputs a voltage of about 0.5V, the solar cell module 200 may be connected to a plurality of solar cells in series and / or in parallel to obtain a voltage suitable for a use range. Configure The solar cell array 300 may be configured by installing a plurality of solar cell modules in a frame. The solar cell array 300 is fixed to a frame (not shown), it may be installed to have a constant angle toward the south to shine the sunlight well.

The photovoltaic power generation system may include a power control device 400 that receives power from the solar cell array 300 and the solar cell array 300 and transmits the power to the outside. The power control device 400 may include an output device 410, a power storage device 420, a charge and discharge control device 430, a system control device 440. The output device 410 may include a power converter 412 and a grid connect system 414. The power conditioning system (PCS) 412 may be an inverter that converts DC power from the solar cell array 300 to AC power. The grid linkage device 414 may mediate a connection with another power system 500. Since sunlight does not exist at night and shines less on cloudy days, the power generated may be reduced. The electrical storage device 420 may store electricity so that the generated power does not change with the weather. The charge / discharge control device 430 may store power from the solar cell array 300 in the power storage device 420, or output electricity stored in the power storage device 420 to the output device 410. have. The system controller 440 may control the output device 410, the power storage device 420, and the charge / discharge control device 430.

1 is a perspective view of a solar cell according to embodiments of the present invention.

FIG. 2 is an enlarged conceptual view of part A of FIG. 1.

3 to 9 are views illustrating a method of forming a solar cell according to embodiments of the present invention.

10 shows an example of a photovoltaic power generation system using a solar cell according to the present invention.

Claims (20)

A semiconductor substrate of a first conductivity type; A second conductive semiconductor layer on the first conductive semiconductor substrate; And And a pn junction adjacent to an interface between the first conductivity type semiconductor substrate and the second conductivity type semiconductor layer, wherein the depth of the pn junction is 1000 kW or less. The method according to claim 1, The semiconductor substrate is composed of monocrystalline silicon, and the semiconductor layer is composed of amorphous silicon. The method according to claim 1, And the pn junction is provided to the semiconductor substrate adjacent to the interface. The method according to claim 3, The semiconductor substrate has a second conductivity type interface region provided in an upper portion of the semiconductor substrate in contact with the semiconductor layer of the second conductivity type and a base of a first conductivity type provided in an upper portion of the semiconductor substrate. And a region, wherein the interface region has a lower impurity ion concentration than the semiconductor layer. The method according to claim 4, And the pn junction is formed at an interface between the interface region and the base region. A crystalline silicon substrate having a first region of a lower first conductivity type and a second region of an upper second conductivity type, the pn junction being formed at an interface therebetween; And And a second conductive amorphous silicon layer on the crystalline silicon substrate, wherein the second region has a lower impurity concentration than the amorphous silicon layer. A semiconductor substrate having a front surface for receiving sunlight and a rear surface facing the front surface; A pn junction formed in the semiconductor substrate; And A solar cell comprising a P-type electrode and an N-type electrode provided on the front surface of the semiconductor substrate, the height of the lower surface of the P-type electrode and the N-type electrode is different. The method according to claim 7, The P-type electrode has a structure recessed in a groove formed on the front surface of the semiconductor substrate. A first conductive semiconductor substrate having a front surface and a rear surface facing the front surface; A second conductive semiconductor layer on an entire surface of the first conductive semiconductor substrate; An anti-reflection film on the second conductive semiconductor layer; A pn junction adjacent to an interface between the first conductive semiconductor substrate and the second conductive semiconductor layer; A first electrode formed in a first groove exposing the first conductive semiconductor substrate; And And a second electrode formed in a second groove having a depth shallower than that of the first groove, exposing the second conductive semiconductor layer. The method according to claim 9, The lower surface of the second groove is higher than the upper surface of the semiconductor substrate of the first conductivity type. The method according to claim 10, The first electrode is spaced apart from the second conductive semiconductor layer on the sidewall of the first groove to prevent direct contact between the second conductive semiconductor layer and the first electrode. A solar cell further comprising an insulating film spacer for exposing a semiconductor substrate. The method according to claim 11, The bottom surface of the insulating film spacer is at least lower than the pn junction surface. The method according to claim 12, And the first groove has an extended groove extending toward the rear surface and coplanar with the sidewall of the insulating film spacer. The method according to claim 11, And a protective insulating film covering the entire rear surface of the first conductive semiconductor substrate, wherein the protective insulating film is made of the same material as the insulating film spacer. Forming an amorphous semiconductor layer of a second conductivity type on the semiconductor substrate of the first conductivity type; And Performing a heat treatment process to form a pn junction adjacent to an interface between the first conductive semiconductor substrate and the second conductive amorphous semiconductor layer. The method according to claim 15, The forming of the amorphous semiconductor layer includes forming an undoped amorphous semiconductor layer, and subsequently forming an amorphous semiconductor layer doped with impurities of a second conductivity type. Forming a second conductive semiconductor layer on the front surface of the first conductive semiconductor substrate having a front surface and a rear surface facing the front surface; Forming a pn junction adjacent to an interface between the first conductive semiconductor substrate and the second conductive semiconductor layer; Forming an anti-reflection film on the second conductive semiconductor layer; Forming a protective insulating film on a rear surface of the first conductive semiconductor substrate; Forming a first electrode in a first groove exposing the first conductive semiconductor substrate; And Exposing the second conductive semiconductor layer, and forming a second electrode in a second groove having a shallower depth than the first groove. The method according to claim 17, Forming the first electrode is: Forming a first mask pattern on the anti-reflection film; And Etching the anti-reflection film, the second conductive semiconductor layer, and the first conductive semiconductor substrate using the first mask pattern to form a first groove having a depth equal to or greater than a depth of the pn junction. Solar cell formation method. The method according to claim 18, The first groove is formed by: Etching the second conductive semiconductor layer and the first conductive semiconductor substrate using the first mask pattern to form a first groove having a depth equal to or greater than the depth of the pn junction; The first electrode is spaced apart from the second conductive semiconductor layer on the sidewall of the first groove to prevent direct contact between the second conductive semiconductor layer and the first electrode. Forming an insulating film spacer exposing the semiconductor substrate; And And forming an extension groove by additionally etching the first conductive semiconductor substrate using the first mask pattern and the insulating layer spacer. The method according to claim 17, Forming the second electrode is: Forming a second mask pattern covering the first groove and exposing the anti-reflection film in a portion spaced from the first groove; And And etching the anti-reflection film and the second conductive semiconductor layer using the second mask pattern to form second grooves shallower than the depth of the pn junction.

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