KR20090064932A - Electrostatic discharge protection element - Google Patents

Abstract

The present invention relates to an electrostatic discharge protection device, and to implement a new electrostatic discharge protection device of a silicon controlled rectifier structure applicable to a semiconductor device having a nano device-based high-speed input / output (I / O interface) circuit and low power supply voltage characteristics, By connecting a PMOSFET to an anode end on the semiconductor substrate, an NMOSFET to a cathode end on the semiconductor substrate, and connecting a plurality of RC networks each applying a bias to the gate end of the PMOSFET and the NMOSFET in an existing SCR structure. In addition, it is possible to implement a protection circuit that satisfies various ESD performance indicators, and to improve its safety and reliability by applying it to high speed, low voltage, and small and highly integrated VDSM (Very Deep Sub-Micron) class semiconductor chips.

Description

Electrostatic Discharge (ESD) protection device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the electrostatic discharge protection circuit technology of semiconductor device technology. In particular, a novel electrostatic discharge protection of a silicon controlled rectifier structure applicable to a semiconductor chip having a high power input / output (I / O interface) circuit and a low power supply voltage characteristic based on a nano device It relates to an element.

With the recent rapid development of semiconductor manufacturing process technology, the phenomenon of electrostatic discharge (Electrostatic Discharge, hereinafter referred to as ESD) in semiconductor chips which have been miniaturized and highly integrated is caused by the static electricity generated during the production process or use of electronic components and products. Discharge causes destruction of internal circuitry of the integrated circuit and metal wiring and malfunction of the circuit, which is a very important consideration in the field of integrated circuit design. In other words, as semiconductor manufacturing process technology is developed from the deep sub-micron (VDSM) level to the very deep sub-micron (VDSM) level, the gate oxide thickness is reduced (about 0.01 μm). And compactness and integration of the semiconductor chip. Since the electrical level of the ESD pulse (pulse) that can be applied to such a chip is very large, such as a few kilovolts (volts), a few amps (ampere), device destruction caused by ESD is more serious. As a result, in semiconductor chips that operate at very high speeds based on the Very Deep Sub-Micron (VDSM) technology, the ESD phenomenon is very damaging to internal circuitry and chip operation and yield. .

According to the present report, about 25% to 30% of chips destroyed by electrostatic phenomena account for a significant portion of the failure of the entire semiconductor chip. In addition, according to the National Technology Roadmap for Semiconductors (NTRS), one of the five most difficult challenges in the semiconductor industry is the problem with ESD, and research is becoming increasingly important.

Commonly known ESD protection circuit technologies include ESD protection devices having a silicon controlled rectifier (SCR) structure known as a thyristor. These common SCRs have much greater electrostatic discharge (ESD) protection than other popular devices such as gate grounded NMOS (ggNMOS).

 Accordingly, the SCR can achieve desired ESD protection with a small area consumption, and can also minimize parasitic capacitance components of the ESD protection circuit, which is suitable for high frequency analog and RF circuits.

However, the typical SCR has a trigger voltage of about 20V, which causes the internal wires to deteriorate due to the destruction of the gate oxide of the MOSFET in the semiconductor chip core circuit or the introduction of ESD current before the protection device operates. You can't stop it.

Therefore, the development and circuit of a protection device that satisfies several ESD performance indicators, such as fast discharge speed, transparency in normal operation, robustness of sufficient discharge current, and low trigger voltage characteristic, etc. Design is very important, and accordingly, various protection devices and circuits have recently been researched and developed to prevent the destruction of semiconductor devices and circuits by ESD.

In order to solve the problems as described above, an object of the present invention is to improve the high trigger voltage of the ESD protection device of the existing SCR structure, and to protect the existing protection when the ESD pulse is applied by connecting the RC-network. The present invention provides an ESD protection device with a silicon-controlled rectifier structure that can be applied to a new semiconductor chip that has a faster response time than a circuit.

In addition, an object of the present invention is to provide an ESD protection device having a novel structure for effective ESD protection in a small and highly integrated VDSM (Very Deep Sub-Micron) class of semiconductor chips having high speed and low voltage characteristics while satisfying all ESD performance indicators. Is in.

An electrostatic discharge protection device for achieving the above objects of the present invention, a semiconductor substrate; A P MOS field effect transistor (PMOSFET) having a drain terminal connected to an anode terminal on the semiconductor substrate; A first N-MOS field effect transistor (NMOSFET) having a source terminal coupled to the cathode terminal on the semiconductor substrate; And a plurality of RC networks connected to the gate terminals of the PMOSFET and the NMOSFET, respectively, to apply a bias, wherein the source terminal of the PMOSFET and the drain terminal of the NMOSFET are connected by metal.

Accordingly, the present invention forms a CMOS structure in a general SCR structure and implements a ESD protection device having a new structure, thereby enabling the implementation of a protection circuit that satisfies several ESD performance indicators. Low voltage and small ?? It is applied to highly integrated VDSM (Very Deep Sub-Micron) class semiconductor chip, which can increase the safety and reliability.

 In addition, the ESD protection device of the new structure of the present invention can be applied to almost all nano-device-based I / O interface circuit and integrated circuit semiconductor, etc., the field of application is very extensive, In this case, there is an effect of high safety and reliability, and the cost of one-chip can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, if it is determined that detailed descriptions of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In an embodiment of the present invention, a CMOS structure is formed in an existing SCR structure for lowering the trigger voltage of the SCR and for more organic operation of the protection circuit, thereby satisfying various ESD performance indicators without increasing an additional mask. The ESD protection device will be described. The ESD protection device according to the embodiment of the present invention is an ESD protection of the N / P type low voltage triggered silicon controlled rectifier (hereinafter referred to as NPLVTSCR) structure that is a silicon controlled rectifier applicable to a semiconductor chip. Element.

Such an ESD protection device according to an embodiment of the present invention is modified by the structure of a conventional low voltage trigger SCR (hereinafter referred to as LVTSCR) and referred to as an N MOS field effect transistor (hereinafter referred to as NMOSFET). ) And a P MOS field effect transistor (hereinafter referred to as a PMOS field effect transistor) to induce a trigger of the protection device at a lower voltage when an ESD pulse is applied. In addition, the ESD protection device prevents latch-up of the protection device that may occur in a steady state operation, and at the same time, to realize a response speed of the protection circuit faster when an ESD pulse is applied. As a general rule, configure an RC-network.

Before describing the structure of the ESD protection device according to the embodiment of the present invention, a general SCR and LVTSCR (or ZTSCR) will be described for convenience of description.

As described above, the general SCR has a property of changing from a high impedance state to a low impedance state and thus is used in power device applications. By using these characteristics, the desired ESD protection can be achieved with a small area consumption, and because of the small area, the parasitic capacitance component of the ESD protection circuit can be minimized so that it can be applied to radio-frequency (RF) and analog circuits. It is widely applicable. Therefore, the SCR protection device has much greater ESD protection tolerance than ggNMOS, that is, it has excellent robustness and is effective.

The structure of such a general SCR is composed of a simple lateral PNP 10 and an NPN 20 transistor, as shown in FIG. 1, and the P + of the SCR present in the n-type well 50. The diffusion region 51 is connected to the anode end 30, and the n + diffusion region 61 of the p-type well 60 is connected to the cathode end 40 of the SCR. do. In the ESD protection device, the SCR characteristic curve according to the change of the anode voltage is shown in FIG. 3. The operating principle is as follows.

Referring to FIG. 1, when the anode 30 voltage becomes greater than the collector voltage (Vc), the emitter-base junction of the pnp transistor 10 becomes the forward bias ( forward bias), and the pnp transistor 10 is turned on. At this time, the current flowing through the pnp transistor 10 flows to the p-type well 60, and the npn transistor 20 is turned on by this current. The current of the npn transistor 20 flowing from the n-type well 50 to the cathode 40 imposes a forward bias on the pnp transistor 10, resulting in a turn-on The SCR is triggered (A in FIG. 3) by the two transistors 10 and 20. As a result, since the bias of the pnp transistor 20 is no longer necessary, the voltage of the anode 30 is reduced to a minimum value, which is referred to as a holding voltage (B of FIG. 3).

Subsequently, the SCR performs a feedforward operation to effectively discharge the ESD current flowing through the anode 30.

 The SCR with two terminals can be simplified with the circuit of Figure 2 attached, where Rn-well and Rp-well are the resistance values of n-type well 50 and p-type well 60, respectively. The bias is provided to the pnp transistor 10 and the npn transistor 20.

In order to maintain the state when the SCR is in the latch mode, it is necessary to satisfy the following condition.

B _npn B _pnp ≥ 1

Here, B _npn and B _pnp are current gains of the npn transistor 20 and the pnp transistor 10.

  When the SCR structure is used as an ESD protection circuit, an avalanche breakdown at the junction of the n-type well 50 and the p-type well 60 is required for the protection element to trigger.

 In the next-generation CMOS process, the breakdown voltage between the n-type well and the p-type substrate is about 20V or more. Therefore, in order to construct an ESD protection device using the SCR described above, Trigger voltage must be lowered.

On the other hand, LVTSCR as shown in Figure 4 is a structure using the advantages of the general SCR and ggNMOS, n + (71) and p that spans the junction of the n- type well 50 and the p- type substrate (1) The trigger operation by the breakdown voltage in the -type substrate 1 is performed. That is, it can be seen that ggNMOS is formed in the SCR structure, and the base width of the lateral NPN 71 transistor Q1 is defined as the channel width of the N-channel metal-oxide semiconductor using the ggNMOS structure. By minimizing the channel width (a), the current gain can be increased to have a low trigger voltage. In addition, by minimizing the base width (b) of the horizontal PNP transistor (Q2) it is possible to implement a protection device having a trigger voltage of about 6V.

Meanwhile, as shown in Attached 5, Zenor Triggered SCR (ZTSCR) using the breakdown voltage of the Zener diode is n-type well 50 / p-type well in the typical SCR shown in FIG. Highly doped PN junction 80 may be formed at the junction of 60. In this case, due to the decrease in the depletion region width, a breakdown phenomenon due to tunneling occurs at a voltage as low as about 5.6V. This induces the turn-on of the ZTSCR ESD protection device, which effectively discharges the ESD current.

By the way, although the protection element of such a general SCR structure has a large ESD protection capability, the trigger voltage is high and thus cannot be applied to a VDSM class integrated circuit. In addition, LVTSCR (Low Voltage Triggered SCR) and Zenor Triggered SCR (ZTSCR) cannot be applied to VDSM (Very Deep Sub-Micron) class high speed / low voltage circuits. There are many difficulties in production.

Therefore, in the embodiment of the present invention to configure the ESD protection device of the new NPLVTSCR structure for lowering the trigger voltage, the structure of the ESD protection device of the NPLVTSCR structure will be described in detail with reference to the accompanying drawings. do.

6 is a diagram illustrating a structure of an ESD protection device having an NPLVTSCR structure according to an embodiment of the present invention.

 The ESD protection device of the NPLVTSCR structure is a modification of the existing LVTSCR structure, and additionally forms an NMOSFET at the cathode end of the LVTSCR.

Referring to FIG. 6, an ESD protection device having the NPLVTSCR structure forms a first NMOSFET at a cathode terminal 101 on a semiconductor substrate (p-type substrate) and an anode (on a semiconductor substrate (p-type substrate). PMOSFET is formed at the Anode end 102. The ESD protection device of the NPLVTSCR structure includes an RC-network (150a, 150b) composed of a resistor (R) and a capacitor (C) for applying a bias to the first NMOSFET and the PMOSFET, and a second NMOSFET to block a latchup phenomenon. It is configured outside the p-type substrate.

The source terminal 121 of the PMOSFET and the drain terminal 111 of the NMOSFET are connected to a metal 130 to induce a lower trigger voltage. In this case, the drain 122 of the PMOSFET is connected to an I / O pad as the anode 102 of the SCR, and the source 112 of the NMOSFET is connected to ground as the cathode terminal 101. This provides an ESD path.

 The RC-network 150a is connected to the gate end 123 of the PMOSFET and the gate end of the second NMOSFET, and the RC-network 150b is connected to the gate end 113 of the NMOSFET. The RC-networks 150a and 150b induce faster turn-on of the SCR by the operation of the two MOSFETs by applying bias to the gate ends 113 and 123 of the MOSFETs. do.

The ESD protection device of the NPLVTSCR structure configured as described above may operate as follows.

Upon application of an ESD pulse, the current flowing through the source 122 of the PMOSFET is discharged to the cathode stage 101 by the NMOSFET turned on by the gate 123 bias. At the same time, the potential of the p-type substrate 1 is increased by the operation of the PMOSFET, and the n-type source 112 in the NMOSFET is emitter and the p-substrate is increased. (1) is the base and n-well 103 / n + anode 7 is a horizontal npn transistor whose collector is turned on. As a result, the potential of the n-type well 103 is lowered by the turned-on npn transistor, so that the horizontal pnp transistor (p + source 122 in the PMOSFET is emitter, n well (n−). Lateral pnp transistors having a well 103 as a base and a P-Substrate (1) / p + cathode as collectors are turned on so that the SCR feedforward operation. This effectively discharges the ESD current.

On the other hand, in the steady state operation, the latch-up phenomenon of the SCR structure can be prevented by the RC-network 150a and the NMOSFET 160 that are externally connected. That is, when the ESD pulse is not applied, the bias is continuously applied to the gate terminal of the NMOSFET 160 connected to the outside. Thus, by the turned-on NMOSFET 160, P + 121 at the junction of p-type substrate 1 and N-type well 103 is connected to ground. As a result, the parasitic current flowing from the anode stage 102 of the SCR is easily discharged to the ground, thereby preventing the latch-up phenomenon of the NPLVTSCR protection element, which may occur in a normal state.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined not only by the scope of the following claims, but also by the equivalents of the claims.

1 is a circuit diagram showing a typical silicon controlled rectifier (SCR) used in an ESD protection circuit;

FIG. 2 is a circuit diagram briefly illustrating the SCR shown in FIG. 1;

3 is a graph showing the SCR characteristic curve according to the change of the anode voltage in the ESD protection device.

4 is a circuit diagram showing a typical LVTSCR;

5 is a circuit diagram illustrating a ZTSCR using a breakdown voltage of a general zener diode;

6 is a circuit diagram showing the structure of an ESD protection element of the NPLVTSCR structure according to the embodiment of the present invention;

Claims (8)

Semiconductor substrates; A P MOS field effect transistor (PMOSFET) having a drain terminal connected to an anode terminal on the semiconductor substrate; A first N-MOS field effect transistor (NMOSFET) having a source terminal coupled to the cathode terminal on the semiconductor substrate; And And a plurality of RC networks connected to the gate terminals of the PMOSFET and the NMOSFET, respectively, to apply a bias, wherein the source terminal of the PMOSFET and the drain terminal of the NMOSFET are connected by metal. The method of claim 1, A second N-MOS field effect transistor (NMOSFET) connected to the PMOSFET and the RC network and turned on to receive a bias from the RC network when the electrostatic discharge pulse is not applied to block the latch-up phenomenon Electrostatic discharge protection element characterized in that it further comprises). The method of claim 2, And the semiconductor substrate is a p-type substrate, and an n-type well is formed on the p-type substrate in the PMOSFET region. The method of claim 2, And wherein the second NMOSFET has a gate terminal connected to the gate terminal of the PMOS and the RC network, a drain terminal connected to the metal, and a source terminal connected to ground. The method of claim 3, The PMOS flows into the anode terminal when the drain terminal formed at the junction of the p-type substrate and the n-type well is connected to the ground connected to the second NMOSFET when the second NMOSFET is turned on. Electrostatic discharge protection element, characterized in that for discharging the parasitic current. The method of claim 1, The first NMOSFET is turned on by the bias applied from the RC network, when the electrostatic discharge pulse is applied to discharge the current flowing into the source terminal of the PMOSFET to the cathode stage, characterized in that . The method of claim 6, The PMOSFET is turned on by the bias applied from the RC network simultaneously with the operation of the first NMOSFET when the electrostatic discharge pulse is applied, thereby increasing the potential of the p-type substrate. device. The method of claim 7, wherein When the potential of the p-type substrate is increased, the PMOSFET turns on the connected lateral npn transistor to lower the potential of the n-type well, and turns on the connected lateral pnp transistor to perform a positive feedback operation. Electrostatic discharge protection element.

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