KR20090057645A - Array substrate of liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate of a liquid crystal display device and a method of manufacturing the same, wherein the protective film is selectively formed on a substrate including a source and a drain electrode, thereby simplifying the process and improving productivity. A data line crossing each other to define a pixel area; A gate electrode extending from the gate wiring, a gate insulating film on the gate electrode, a semiconductor layer on the gate insulating film, and a drain formed on the semiconductor layer and spaced apart from the source electrode and the source electrode extending from the data wiring; A thin film transistor including an electrode; A metal nitride layer formed on surfaces of the source and drain electrodes; And a pixel electrode electrically connected to the drain electrode through the metal nitride layer and formed in the pixel region.

Description

An Array Substrate of Liquid Crystal Display Device and the method for fabricating

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array substrate of a liquid crystal display device and a method of manufacturing the same. More specifically, an array substrate of a liquid crystal display device which simplifies a process and improves productivity by selectively forming a protective film on a substrate including a source and a drain electrode. And a method for producing the same.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, so that the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal. Therefore, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information. In addition, an active matrix liquid crystal display (AM-LCD) having a thin film transistor and pixel electrodes connected to the thin film transistors arranged in a matrix manner attracts the most attention because of its excellent resolution and video performance.

Hereinafter, an array substrate for a liquid crystal display device using four masks according to the related art will be described with reference to the accompanying drawings.

1A to 1I are cross-sectional views illustrating an array substrate of a liquid crystal display according to the related art.

As shown in FIG. 1A, the substrate 10 is defined as a switching region S, a pixel region P, a gate region G, and a data region D, and a gate metal layer (not shown) on the substrate 10 is illustrated. ) And the gate metal layer is patterned using the first mask to form the gate wiring 20 and the gate electrode 25 extending from the gate wiring 20 in the gate region G. The gate metal layer is used as one or two or more alloys of conductive metals such as copper (Cu), molybdenum (Mo), aluminum (Al), and chromium (Cr). The gate insulating layer 45 is formed of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) on the substrate 10 including the gate electrode 25 and the gate wiring 20.

As shown in FIG. 1B, the pure amorphous silicon layer 40a is formed on the substrate 10 including the gate insulating layer 45, and the group III or group 5 elements are doped with high or low concentration in the pure amorphous silicon layer 40a. An impurity amorphous silicon layer 41a is formed. The source and drain metal layers 75 are formed on the impurity amorphous silicon layer 41a using the same material as the gate metal layer. Pure and impurity amorphous silicon layers 40a and 41a and source and drain metal layers 75 are sequentially stacked on the gate insulating layer 45.

As shown in FIG. 1C, the photosensitive layer 80 is formed on the source and drain metal layers 75, and is formed of a transmissive portion A, a semi-transmissive portion B, and a blocking portion C on an upper portion spaced apart from the substrate 10. The halftone mask HTM is aligned as the second mask. The transflective portion B of the halftone mask HTM functions to form a translucent film to lower the intensity of light or to reduce the amount of light transmitted, thereby incompletely exposing the photosensitive layer 80. The semi-transmissive portion B may use a slit-shaped pattern to adjust the amount of light transmitted. The blocking part C functions to completely block light, and the transmitting part A transmits light so that the photosensitive layer 80 exposed to the light may cause a chemical change to completely expose the light. In the portion corresponding to the gate electrode 25 of the switching region S, the transflective portion B is arranged on both sides of the transflective portion B and the data region D, and the transflective portion ( In the entire area of the substrate 10 that does not correspond to B) and the blocking part C, the transmissive part A is positioned.

As shown in FIG. 1D, when the exposure process is performed using the second mask, the first photosensitive pattern 82 and the opposite side portions of the gate electrode 25 and the data region D are not exposed at the blocking portion C, respectively. A second photosensitive pattern 84 is formed, and a third photosensitive pattern 86 having a portion of the photosensitive layer 80 removed from the gate electrode 25 corresponding to the transflective portion B is formed. All of the photosensitive layers 80 except for the first, second, and third photosensitive patterns 82, 84, and 86 are removed to expose the source and drain metal layers 75.

As shown in FIG. 1E, when the source and drain metal layers 75 are patterned using the first, second, and third photosensitive patterns 82, 84, and 86 as an etching mask, the impurity amorphous silicon in the switching region S is formed. The data lines 30 are formed on the source and drain metal patterns 72 on the layer 41a and on the impurity amorphous silicon layer 41a of the data region D. FIG.

As shown in FIG. 1F, the impurity and the pure amorphous silicon layers 41a and 40a are sequentially etched using the first, second, and third photosensitive patterns 82, 84, and 86 as etching masks. The ohmic contact layer 41 and the active layer 40 having the same width as the source and drain metal patterns 72 are formed below the pattern 72, and the data wiring 30 and the data wiring 30 are formed below the data wiring 30. Impurities and pure amorphous silicon layers 41a and 40a remain in the same width. The semiconductor layer 42 may be referred to as an active layer and an ohmic contact layer 40 and 41.

The third photosensitive pattern 86 is removed to ash the first to second photosensitive patterns 82 and 84 until the source and drain metal patterns 72 are exposed. In the process of completely removing the third photosensitive pattern 86, the top and side surfaces of the first and second photosensitive patterns 82 and 84 are simultaneously removed, so that the first and second photosensitive patterns 82 and 84 have a thickness. As a result, it is about half lower than the original, and the side is reduced to a certain width.

As shown in FIG. 1G, the source and drain metal patterns 72 are patterned using the first and second photosensitive patterns 82 and 84 as etching masks, so that the source electrodes 32 spaced apart from each other in the switching region S. Referring to FIG. And a drain electrode 34 are formed. After the patterning process of the source and drain electrodes 32 and 34, the ohmic layer 41 and a part of the active layer 40 of the channel region ch positioned between the source and drain electrodes 32 and 34 are etched.

As shown in FIG. 1H, an inorganic insulating material or an acryl-based resin and benzocyclobutene including silicon nitride (SiNx) and silicon oxide (SiO ₂ ) on a substrate 10 including source and drain electrodes 32 and 34: The protective film 55 is formed of an organic insulating material including BCB. When the protective film 55 is etched using the third mask, a drain contact hole 90 in which a portion of the drain electrode 34 is exposed is formed.

As shown in FIG. 1I, a transparent metal layer (not shown) such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the passivation layer 55 including the drain contact hole 90. The transparent metal layer is etched using the fourth mask to form the pixel electrode 70 electrically connected to the drain electrode 34 through the drain contact hole 90. The pixel electrode 70 extends so as to overlap the gate wiring 20 of the previous stage, the gate wiring 20 of the front stage as the first electrode, the pixel electrode 70 as the second electrode, and the first and the second A storage capacitor Cst having a gate insulating film 45 and a protective film 55 interposed between the two electrodes as a dielectric layer is formed.

In the prior art, to manufacture an array substrate, a protective film formed on a substrate including a first mask for patterning a gate electrode, a second mask for patterning a source and drain electrode and an active layer, and a source and drain electrode A third mask for patterning and a fourth mask for patterning the pixel electrode are essentially used. However, the mask process involves a complicated process of applying the photosensitive film and exposing and developing the photosensitive film, which leads to an increase in manufacturing cost.

The present invention, in order to solve the above problems of the prior art, by selectively forming a protective film on the surface of the source and drain electrodes and the semiconductor layer, there is no need for a mask process for patterning the protective film, simplifying the process and productivity An object of the present invention is to provide an array substrate of an improved liquid crystal display device and a manufacturing method thereof.

The present invention provides an array substrate of a liquid crystal display device which protects the source and drain electrodes and the semiconductor layer by using a protective film selectively formed on the surface of the source and drain electrodes and the semiconductor layer as an etch resistive film in the patterning process of the pixel electrode. It is another object to provide a manufacturing method.

An array substrate of a liquid crystal display device according to the present invention for achieving the above object comprises: a data line defining a pixel region by crossing the gate line and the gate line on the substrate perpendicularly; A gate electrode extending from the gate wiring, a gate insulating film on the gate electrode, a semiconductor layer on the gate insulating film, and a drain formed on the semiconductor layer and spaced apart from the source electrode and the source electrode extending from the data wiring; A thin film transistor including an electrode; A metal nitride layer formed on surfaces of the source and drain electrodes; And a pixel electrode electrically connected to the drain electrode through the metal nitride layer and formed in the pixel region.

An array substrate of a liquid crystal display device as described above is characterized in that it comprises a silicon nitride layer formed on the surface of the semiconductor layer.

In the array substrate of the liquid crystal display device as described above, the metal nitride layer is selected from copper nitride (CuN), molybdenum nitride (MoN), aluminum nitride (NAl), and chromium nitride (CrN). do.

In the array substrate of the liquid crystal display device as described above, the silicon nitride layer is formed on the semiconductor layer between the source and the drain electrode, and the side of the semiconductor layer below the source and the drain electrode. .

In the array substrate of the liquid crystal display device as described above, the metal nitride layer has a thickness of 200 to 500 GPa, and the silicon nitride layer is formed to a thickness of 300 to 500 GPa.

An array substrate of a liquid crystal display as described above, comprising: a gate and a data pad respectively formed at one end of the gate and the data line; And a gate pad electrode and a data pad electrode electrically connected to the gate and the data pad through a second metal nitride film, respectively.

In the array substrate of the liquid crystal display device as described above, the semiconductor layer is positioned below the data pad, and the silicon nitride layer is formed on the side of the semiconductor layer.

Method of manufacturing an array substrate in a liquid crystal display device for achieving the above object comprises the steps of forming a gate wiring and a gate electrode on the substrate; Forming a gate insulating film on the substrate including the gate wiring; A semiconductor layer on the gate insulating layer, a drain electrode spaced apart from the source electrode, the source electrode on the semiconductor layer, and a data line connected to the source electrode and vertically crossing the gate line to define a pixel region; Forming; Forming a metal nitride layer and a silicon nitride layer on surfaces of the source and drain electrodes and the semiconductor layer, respectively; And forming a pixel electrode in the pixel region, the pixel electrode being electrically connected to the drain electrode through the metal nitride layer.

The method of manufacturing an array substrate in the liquid crystal display device as described above, characterized in that it comprises the step of removing the gate insulating film corresponding to the pixel region.

In the method of manufacturing an array substrate in the liquid crystal display device as described above, the source of the metal nitride layer and the silicon nitride layer supply a reaction gas containing nitrogen, and the temperature of the substrate is maintained at 250 to 400 ℃, the source And the drain electrode and the semiconductor layer are formed by reaction with the nitrogen.

In the method of manufacturing an array substrate in the liquid crystal display device as described above, the reaction gas is characterized in that NH ₃ or N ₂ .

In the method of manufacturing an array substrate in the liquid crystal display device as described above, when NH ₃ is used as the reaction gas, hydrogen gas decomposed from the NH ₃ is diffused into the semiconductor layer.

In the method of manufacturing an array substrate in the liquid crystal display device as described above, in the forming of the gate and the data line, a gate and a data pad are formed at one end of the gate and the data line, respectively, and a second metal nitride layer is formed. And forming a gate pad electrode and a data pad electrode electrically connected to the gate and the data pad, respectively.

In the method of manufacturing an array substrate in the liquid crystal display device as described above, to form a first mask, the semiconductor layer, the source and the drain electrode, and the data wiring to form the gate wiring and the gate electrode. A second mask and a third mask are used to form the pixel electrode.

An array substrate of a liquid crystal display device and a method of manufacturing the same according to an embodiment of the present invention have the following effects.

First, a protective film is selectively formed on the surfaces of the source and drain electrodes and the semiconductor layer, which does not require a mask process for patterning the protective film, and thus an array substrate can be manufactured using three masks. Compared to using two masks, the process can be simplified and the productivity can be improved.

Second, a protective film selectively formed on the surface of the source and drain electrodes and the semiconductor layer by a chemical reaction is used as an etch resistive film having superior characteristics to the conventional protective film in the patterning process of the pixel electrode. Protect the semiconductor layer.

Third, since the pixel electrode is electrically connected to the metal nitride layer of the conductive material selectively formed on the surfaces of the source and drain electrodes, the connection between the drain electrode and the pixel electrode is easier than in the conventional art of connecting through a contact hole. Do.

Fourth, the gate insulating film is removed on the pixel region and no protective film is formed, so that the transmittance of the liquid crystal display device can be improved.

Fifth, hydrogen gas generated in the process of forming the metal nitride layer and the silicon nitride layer may be diffused into the semiconductor layer to reduce the off current of the thin film transistor.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a plan view showing unit pixels of an array substrate of a liquid crystal display according to the present invention, FIGS. 3A to 3I are cross-sectional views of FIG. 2 taken from II-II, and FIGS. 4A to 4I are III in FIG. 5 is a cross-sectional view taken along the line IV-IV of FIG. 2.

As shown in FIG. 2, the array substrate of the liquid crystal display device includes a gate wiring 120, a data wiring 130, a thin film transistor T, and a pixel electrode 170 on the substrate 100. The gate line 120 includes a gate pad 152 formed at one end and a gate electrode 125 provided to the thin film transistor T at an intersection with the data line 130. The gate pad 152 is electrically connected to the gate pad electrode 154 through the gate pad contact CONT2. The gate line 120 and the data line 130 cross vertically to define the pixel area P. FIG.

The data line 130 includes a data pad 162 formed at one end thereof, and the drain electrode 134 extending from the data line 130 is connected to the thin film transistor T. The data pad 162 is electrically connected to the data pad electrode 164 through the data pad contact CONT3. The thin film transistor T is electrically connected to the gate electrode 125, the semiconductor layer 140 on the gate electrode 125, and the semiconductor layer 140, and spaced apart from each other with the gate electrode 125 interposed therebetween. And an electrode 132 and a drain electrode 134.

Although not shown in FIG. 2, the semiconductor layer 140 includes an active layer of pure amorphous silicon (a-Si: H), and an impurity amorphous silicon doped with pure or amorphous group III or Group 5 elements at high or low concentration on the active layer. and an ohmic contact layer of (n + a-Si: H). The ohmic contact layer corresponding to the gate electrode 125 is removed between the source and drain electrodes 132 and 134 to form a channel region by exposing the active layer.

The pixel electrode 170 is electrically connected to the drain region 134 through the drain contact CONT1. The pixel electrode 170 is extended to overlap the gate wiring 120 of the previous stage, the gate wiring 120 of the preceding stage is the first electrode, and overlaps the gate wiring 120 via an insulating film (not shown). The storage capacitor Cst having the pixel electrode 170 as the second electrode is configured.

Referring to FIGS. 3A to 3I, 4A to 4I, and 5A to 5I, a method of manufacturing an array substrate of a liquid crystal display according to a three mask process according to the present invention will be described below. The present invention can be applied to liquid crystal display devices such as a transverse electric field method (IPS), a TN method, and a vertical alignment (VA) method using thin film transistors.

3A through 5A, the substrate 100 is defined as a switching region S, a pixel region P, a gate region G, and a data region D. As shown in FIG. Although not shown in detail in the drawings, a gate metal layer is formed on the substrate 100, the first photosensitive layer is coated on the gate metal layer, and then the first photosensitive layer is exposed and developed with a first mask to expose the first photosensitive layer. Form a layer pattern. The gate metal layer is patterned using the first photoresist layer pattern as an etch mask, so that the gate wiring 120, the gate electrode 125 extending from the gate wiring 120, and the gate wiring 120 of the gate region 120 are formed. The gate pad 152 is formed at one end.

The gate metal layer is used as one or two or more alloys of conductive metals such as copper (Cu), molybdenum (Mo), aluminum (Al), and chromium (Cr). The gate insulating layer 145 is formed of silicon nitride (SiNx) or silicon oxide (SiO ₂ ) on the substrate 100 including the gate electrode 125, the gate wiring 120, and the gate pad 152.

3B to 5B, a pure amorphous silicon layer 140a is formed on the substrate 100 including the gate insulating layer 145, and high or low concentrations of Group 3 or 5 elements are formed in the pure amorphous silicon layer 140a. The doped amorphous silicon layer 141a is formed. The source and drain metal layers 175 are formed on the impurity amorphous silicon layer 141a. The source and drain metal layers 175 may be formed of the same material as the gate metal layer. In other words, the pure and impurity amorphous silicon layers 140a and 141a and the source and drain metal layers 175 are sequentially stacked on the gate insulating layer 145.

3C to 5C, the second photosensitive layer 180 is formed on the source and drain metal layers 175, and the transmissive portion A, the transflective portion B, and the blocking portion C are formed on the substrate 100. A half mask (HTM) is aligned as a second mask composed of The transflective portion B of the halftone mask HTM serves to expose only a portion of the second photosensitive layer 180 by forming a translucent film to lower light intensity or lower light transmittance. The semi-transmissive portion B may use a slit-shaped pattern to adjust the amount of light transmitted. The blocking part C functions to completely block light, and the transmitting part A transmits light so that the second photosensitive layer 180 exposed to the light may cause a chemical change to completely expose the light.

The transflective portion B is formed at the portion corresponding to the gate electrode 125 of the switching region S, and the blocking portion is formed at both sides of the transflective portion B and the portion corresponding to the data region D and the gate wiring 120. The transmissive portion A is positioned in the entire region of the substrate 100 where C) is aligned and does not correspond to the transflective portion B and the blocking portion C.

3D to 5D, when the exposure process is performed using the second mask, first photosensitive patterns 182 are formed on both sides of the gate electrode 125 not exposed by the blocking unit C. The second photosensitive pattern 184 and the fourth photosensitive pattern 188 are formed on the data region D and the gate wiring 120, respectively. The third photosensitive pattern 186 from which a part of the second photosensitive layer 180 is removed is formed on the gate electrode 25 corresponding to the transflective portion B. The second photosensitive layer 180 in the entire region except for the gate electrode 125, both regions of the gate electrode 125, the gate wiring 120, and the portion corresponding to the data region D is removed, and the second photosensitive layer is removed. The source and drain metal layer 175 is exposed by the removal of layer 180.

3E through 5E, the source and drain metal layers 175 are patterned using the first, second, third, and fourth photosensitive patterns 182, 184, 186, and 188 as etch masks to form a switching region. The source and drain metal patterns 172 may be formed on the impurity amorphous silicon layer 141a of (S), and the data lines 130 and the data pads 162 may be formed on the impurity amorphous silicon layer 141a of the data region D. Form. For the patterning of the source and drain metal layers 175, a wet etching process using an etchant may be used. The impurity amorphous silicon layer 141a is exposed in regions except for the shielding portions of the source and drain metal patterns 172, the data lines 130, the data pads 162, and the fourth photosensitive pattern 188. In addition, the source and drain metal patterns 172 are electrically connected to the data lines 130.

3F to 5F, the substrate 100 is moved to a process chamber (not shown) to dry etch pure and impurity amorphous silicon 140a and 141a. Using the first, second, third, and fourth photosensitive patterns 182, 184, 186, and 188 as etching masks, the impurities and the pure amorphous silicon layers 141a and 140a are etched to form source and drain metal patterns ( An ohmic contact layer 141 and an active layer 140 having the same width as the source and drain metal patterns 172 are formed below the 172, respectively. Impurities and pure amorphous silicon layers 140a and 141a remain in the same width as the data wire 130 and the data pad 162 under the data wire 130 and the data pad 162.

In addition, the fourth photosensitive pattern 188 may be provided on the gate insulating layer 145 corresponding to the gate wiring 120 to form pure and impurity amorphous silicon layers 140a and 141a having the same width as that of the fourth photosensitive pattern 188. This remains. In the switching region S, the active layer 140 and the ohmic contact layer 141 are formed by patterning the pure and impurity amorphous silicon layers 140a and 141a, respectively. The active layer 140 and the ohmic contact layer 141 are referred to as a semiconductor layer 42. The pure and impurity amorphous silicon layers 140a and 141a on the substrate 100 except for the first, second, third and fourth photosensitive patterns 182, 184, 186 and 188 are removed.

The third photosensitive pattern 186 is removed to ash the first to second photosensitive patterns 182 and 184 until the source and drain metal patterns 172 are exposed. In the process of completely removing the third photosensitive pattern 186, the top and side surfaces of the first, second, and third photosensitive patterns 182, 184, and 188 are simultaneously removed to remove the first, second, and third photosensitive photos. Patterns 182, 184, and 188 are about half lower in thickness as compared to the first, and by F width on the side. Therefore, the width of the blocking part C corresponding to the gate electrode 125 and the channel region ch is formed in consideration of the width in which the side surface of the first photosensitive pattern 182 is removed and reduced in the second mask. do.

3G to 5G, the source and drain metal patterns 172 are patterned using the first, second, and third photosensitive patterns 182, 184, and 188 as etching masks, and spaced apart from each other in the switching region S. Referring to FIGS. The source electrode 132 and the drain electrode 134 are formed. After the patterning process of the source and drain electrodes 132 and 134, a portion of the ohmic contact layer 141 and the active layer 140 of the channel region ch positioned between the source and drain electrodes 132 and 134 are etched. When forming the channel region ch, a portion of the ohmic contact layer 141 and the active layer 140 corresponding to the F width is also removed at the same time. After the channel region ch is formed, the first, second and third photosensitive patterns 182, 184 and 188 are removed. In the process of etching the source and drain metal patterns 172, the ohmic contact layer 141, and the active layer 140, the gate insulating layer 145 of the pixel region P is removed by performing overetching. The gate insulating layer 145 is removed except for the switching region S, the data region D, and the gate wiring region. The light transmittance of the pixel region P is improved by removing the gate insulating layer 145.

The substrate 100 is moved to a process chamber (not shown) for generating a plasma, and a reaction gas containing nitrogen, for example, NH ₃ or N ₂ gas, is supplied into the process chamber as shown in FIGS. 3H to 5H. In addition, the substrate 100 is maintained at a temperature at which nitrogen can be decomposed, for example, 250 to 400 ° C., preferably 350 ° C., so that the metal nitride layer 190 and the silicon nitride layer (SiN) 191 are selectively disposed. Form. Since the source and drain electrodes 132 and 134 select one of copper (Cu), molybdenum (Mo), aluminum (Al), and chromium (Cr), the metal nitride layer 190 is formed of copper nitride (CuN). , Molybdenum nitride (MoN), aluminum nitride (NAl), and chromium nitride (CrN). The metal nitride layer 190 has a thickness of 200 to 500 GPa, and the silicon nitride layer 191 is formed to have a thickness of 300 to 500 GPa.

The metal nitride layer 190 is formed on the surfaces of the source and drain electrodes 132 and 134, the gate pad 152 exposed by the gate pad contact CONT2, the data wire 130 and the data pad 162, and nitrided. The silicon layer 191 may include sidewalls of the pure and impurity amorphous silicon layers 140a and 141a disposed under the source and drain electrodes 132 and 134, the data line 130, and the data pad 162, and the channel region ( and the active layer 140 corresponding to ch) and the pure and impurity amorphous silicon layers 140a and 141a remaining on the gate insulating layer 145 corresponding to the gate wiring 120. The metal nitride layer 190 and the silicon nitride layer 191 are formed in a process chamber by thermal decomposition or plasma of a reaction gas containing nitrogen.

When NH ₃ is used as a reaction gas for forming the metal nitride layer 190 and the silicon nitride layer 191, hydrogen generated by the decomposition of NH ₃ is diffused into the semiconductor layer 142 to form a protective film as in the prior art. As compared with the case where the oxide film is used, the OFF current of the thin film transistor is reduced. The reason why the off current is reduced is that hydrogen is diffused into the semiconductor layer, and the off current is estimated to be reduced by combining with dangling bonds to maintain the stable structure of the semiconductor layer 142.

Although not shown in detail in the drawing, a transparent metal layer such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the substrate 100 including the metal nitride layer 190 and the silicon nitride layer 191. It forms, and apply | coats a 3rd photosensitive layer on a transparent metal layer. The third photosensitive layer is exposed and developed by a third mask to form a third photosensitive layer pattern. 3I to 5I, the transparent metal layer is patterned using the third photosensitive layer pattern as an etching mask. By patterning the transparent metal layer, in the region of the drain contact CONT1, the pixel electrode 170 electrically connected to the drain electrode 134, and the gate and data pad electrically connected to the gate and data pads 152 and 162, respectively. Electrodes 154 and 164 are formed. The pixel electrode 170 is extended so as to overlap the gate wiring 120 at the front end, the gate wiring 120 at the front end is used as the first electrode, and the pixel electrode 170 is the second electrode. A storage capacitor Cst having a gate insulating film 145 and a protective film 155 interposed between the two electrodes as a dielectric layer is formed.

The patterning of the pixel electrode 170 is to deposit a transparent metal layer on the conductive metal nitride layer 190 formed on the surfaces of the source and drain electrodes 132 and 134 and selectively etch the transparent metal layer. There is no need for a patterning process for forming a contact hole, so that the drain electrode and the pixel electrode can be easily aligned and electrically connected. In addition, by selectively forming the metal nitride layer 190 and the silicon nitride layer 191 on the surfaces of the source and drain electrodes 132 and 134 and the semiconductor layer 142 as a protective film, a separate mask process for patterning the protective film is performed. Not required, the process can be simplified and productivity can be improved. In addition, when the transparent metal layer is etched, the metal nitride layer 190 and the silicon nitride layer 191 are not etched, and the source and drain electrodes 132 and 134, the active layer 140, and the ohmic contact layer disposed thereunder are not etched. 141) to protect the function.

1A to 1I are cross-sectional views of an array substrate of a liquid crystal display according to the related art.

2 is a plan view illustrating unit pixels of an array substrate of a liquid crystal display according to an exemplary embodiment of the present invention.

3A to 3I are cross-sectional views of FIG. 2 taken along II-II.

4A to 4I are cross-sectional views taken along line III-III of FIG. 2.

5A to 5I are cross-sectional views taken along line IV-IV of FIG. 2.

Claims (14)

A data line defining a pixel region by crossing the gate line on the substrate and perpendicular to the gate line; A gate electrode extending from the gate wiring, a gate insulating film on the gate electrode, a semiconductor layer on the gate insulating film, and a drain formed on the semiconductor layer and spaced apart from the source electrode and the source electrode extending from the data wiring; A thin film transistor including an electrode; A metal nitride layer formed on surfaces of the source and drain electrodes; A pixel electrode electrically connected to the drain electrode through the metal nitride layer and formed in the pixel region; Array substrate of a liquid crystal display device comprising a. The method of claim 1, And a silicon nitride layer formed on the surface of the semiconductor layer. The method of claim 1, And the metal nitride layer is selected from copper nitride (CuN), molybdenum nitride (MoN), aluminum nitride (NAl), and chromium nitride (CrN). The method of claim 2, And the silicon nitride layer is formed on the side of the semiconductor layer between the source and drain electrodes and on the side of the semiconductor layer below the source and drain electrodes. The method of claim 2, And the metal nitride layer has a thickness of 200 to 500 GPa, and the silicon nitride layer has a thickness of 300 to 500 GPa. The method of claim 1, A gate and a data pad formed at one end of the gate and the data line, respectively; A gate pad electrode and a data pad electrode electrically connected to the gate and the data pad through a second metal nitride film; Array substrate of a liquid crystal display device comprising a. The method of claim 6, And the semiconductor layer is positioned below the data pad, and a silicon nitride layer is formed on a side surface of the semiconductor layer. Forming a gate wiring and a gate electrode on the substrate; Forming a gate insulating film on the substrate including the gate wiring; A semiconductor layer on the gate insulating layer, a drain electrode spaced apart from the source electrode, the source electrode on the semiconductor layer, and a data line connected to the source electrode and vertically crossing the gate line to define a pixel region; Forming; Forming a metal nitride layer and a silicon nitride layer on surfaces of the source and drain electrodes and the semiconductor layer, respectively; Forming a pixel electrode in the pixel region, the pixel electrode being electrically connected to the drain electrode through the metal nitride layer; Method of manufacturing an array substrate in a liquid crystal display comprising a. The method of claim 8, And removing the gate insulating layer corresponding to the pixel region. The method of claim 8, The metal nitride layer and the silicon nitride layer supply a reaction gas containing nitrogen, and maintain the temperature of the substrate at 250 to 400 ° C., so that the source, the drain electrode, and the semiconductor layer react with the nitrogen. A method of manufacturing an array substrate in a liquid crystal display device, characterized in that formed by. The method of claim 8, And the reaction gas is NH ₃ or N ₂ . The method of claim 11, When using NH ₃ as the reaction gas, hydrogen gas decomposed from the NH ₃ is diffused into the semiconductor layer. The method of claim 8, In the forming of the gate and the data line, a gate and a data pad are formed at one end of the gate and the data line, respectively, and are electrically connected to the gate and the data pad via a second metal nitride layer. Forming a pad electrode and a data pad electrode comprising the steps of manufacturing an array substrate in a liquid crystal display device. The method of claim 8, A first mask to form the gate wiring and the gate electrode, a second mask to form the semiconductor layer, the source and drain electrodes, and the data wiring, and a third mask to form the pixel electrode Method of manufacturing an array substrate in a liquid crystal display, characterized in that using.

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