KR20090054606A - Frame Synchronization Device and Method - Google Patents

Abstract

The present invention relates to an apparatus and method for frame synchronization of satellite data. In accordance with another aspect of the present invention, a frame synchronization method includes storing first to fourth FSM bit strings obtained by converting a predetermined bit pattern into 0 °, 90 °, 180 °, and 270 ° phases in a first register, and input data bits. Repeating the string four times and storing it in the second register, and storing the bit string corresponding to the result of performing an exclusive OR on the bit strings stored in the first register and the second register in the third register; Obtaining a Hamming distance value between the input data bit string and the first to fourth FSM bit strings from the bit string stored in the third register, and determining whether the input data bit string is FSM based on the obtained Hamming distance value. do. According to the present invention, it is possible to detect the FSM quickly and minimize data loss.

Description

FRAME SYNCHRONIZATION APPARATUS AND METHOD}

The present invention relates to an apparatus and method for frame synchronization, and more particularly, to an apparatus and method for frame synchronization capable of quickly detecting a frame synchronization marker (FSM) from input data and preventing loss of input data.

Satellite communication is a communication that relays communication by an artificial satellite that has been launched in the air outside the atmosphere, and satellite communication has a wider communication range and enables ultra-fast transmission using high frequency radio waves.

Satellite communications use microwaves to enable high-speed, high-capacity communications, and can set up specific areas throughout the country.

As such, due to various functions of satellite communication, current satellite communication transmits a large amount of data to a ground station, and satellite communication between the satellite and the ground station is being replaced by a digital method in the existing analog method.

Therefore, digital communication used for satellite communication also requires a large amount of data processing.

Here, a frame corresponds to a data transmission unit, and is a unit including an address and essential protocol control information in addition to actual information, and data is transmitted in units of frames between the satellite and the ground station.

The frame is transmitted in bits and includes header fields and trailer fields before and after the data, and includes information representing actual data.

When data is transmitted frame by frame between a transmitter and a receiver using different clocks, the receiver may lose data included in the frame due to a clock phase difference.

If data is lost due to inconsistent data transmission / reception, the receiving end cannot decode the frame and must discard the data.

In general, frame synchronization may be performed through a process of recombining data included in a frame into bytes or words by identifying a frame word indicating a starting point at a receiving end.

Conventionally, frame synchronization processing of a large amount of data is performed using hardware or data is stored and then processed by software.

However, in the case of hardware processing, data loss occurs according to the characteristics of the hardware. In the case of software processing, data loss can be prevented, but the speed is slowed.

Accordingly, an object of the present invention is to provide a frame synchronization apparatus and method capable of increasing the speed of frame synchronization processing and minimizing data loss.

According to an aspect of the present invention, there is provided a frame synchronization apparatus according to an embodiment of the present invention, wherein (a) first to fourth FSM bit strings in which a predetermined bit pattern is converted by 0 °, 90 °, 180 °, and 270 °, respectively. Is stored in the first register, (b) repeating the input data bit string four times and storing the second data in the second register, and (c) an exclusive logical sum of the bit strings stored in the first register and the second register. Storing a bit string corresponding to a result of performing (XOR) in a third register; and (d) between the input data bit string and the first to fourth FSM bit strings from a bit string stored in the third register. Obtaining a Hamming distance value, and (e) determining whether the input data bit string is FSM based on the obtained Hamming distance value.

If there is a value smaller than a predetermined threshold value among the obtained hamming distance values, it may be determined that the input data bit string is an FSM.

Determining that the input data bit string is not an FSM if none of the obtained Hamming distance values is smaller than a predetermined threshold; and if it is determined that the input data bit string is not an FSM, the input in the input data buffer. The method may further include repeating the bit string shifted one bit back four times and storing the data in the second register.

If the bit string shifted one bit back is the same as the input data bit string, the method may further include determining that the bit string shifted one bit back is not an FSM.

When the bit string shifted one bit back is not the same as the input data bit string, steps (c) to (e) may be repeated for the bit string shifted one bit back.

If the input data bit string is determined to be an FSM, the method may further include copying a frame including the input data bit string to a pending buffer.

According to another aspect of the present invention, there is provided a frame synchronization apparatus for storing first to fourth FSM bit strings obtained by converting a predetermined bit pattern into phases of 0 °, 90 °, 180 °, and 270 °, respectively. A first register, a second register for repeatedly storing the input data bit string four times, and a bit string corresponding to a result of performing an exclusive OR (XOR) on the bit strings stored in the first register and the second register. Obtaining a Hamming distance value between the input data bit string and the first to fourth FSM bit strings from a third register to store and a bit string stored in the third register, and the input data bit through the obtained Hamming distance value. And a controller for determining whether the column is FSM.

The controller may determine that the input data bit string is an FSM when there is a value smaller than a predetermined threshold value among the obtained hamming distance values.

The controller determines that the input data bit string is not FSM when there is no value smaller than a predetermined threshold value among the obtained hamming distance values, and when it is determined that the input data bit string is not FSM, The bit string shifted one bit back to the input data bit string may be repeated four times to be stored in the second register.

The controller may determine that the bit string shifted one bit back is not an FSM when the bit string shifted one bit back is the same as the input data bit string.

The controller may perform FSM detection on the bit string shifted one bit back when the bit string shifted one bit back is not the same as the input data bit string.

When the input data bit string is determined to be an FSM, the controller may copy a frame including the input data bit string to a pending buffer.

As described above, according to the present invention, since the FSM is detected by simultaneously comparing the input data with respect to the four phase-converted frame synchronization bit patterns, the FSM can be detected quickly.

In addition, by using the pending buffer, the FSM stores the detected frames in the search state and the check state, and transfers them to the next processing stage when the locked state is reached later, thereby reducing data loss.

In addition, it is possible to prevent the FSM detection operation unnecessarily in the absence of the actual data input.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

Frame synchronization indicates a start and end of a frame and synchronizes transmission / reception using a special bit combination in data connection. First, the frame synchronization processor will be described with reference to FIG. 1.

1 is a diagram illustrating a processing state of frame synchronization of satellite data according to an embodiment of the present invention.

As shown in FIG. 1, the processing state of frame synchronization includes a search state, a check state, a lock state, and a flywheel state.

The search state is a step of searching for a frame synchronization code (Frame Synchronization Marker, hereinafter referred to as "FSM") in the input data.

In the search state, the input data is moved in units of bits, and the FSM according to the demodulation method is detected. When the FSM is detected, the data is moved to the check state.

Unlike the check state, lock state, and flywheel state, which moves data in units of frames and detects the FSM using a pre-calculated phase, the search state moves data in bits to detect the FSM, which results in the highest data throughput. There is also a lot of time.

The process of detecting the FSM in the search state will be described in detail with reference to FIGS. 2 to 4.

The check state detects the FSM in units of frames by using the FSM detected in the search state. If the FSM is detected by the check count set by the user, the controller moves to the locked state, but if the FSM fails, it returns to the search state.

Like the check state, the lock state detects the FSM in units of frames, and when the FSM is detected, the frame is stored or transmitted to the next processing stage. On the other hand, if the detection of the FSM fails, it moves to the flywheel state.

The flywheel condition also detects the FSM frame by frame. If the FSM fails, the flywheel count is incremented by one.

When the flywheel count exceeds the user-set value, the search returns to the search state, and the frame until the search state is moved is stored or transmitted to the next processing stage. When the FSM is detected, the controller moves to the locked state.

Prior to describing a frame synchronization device according to an embodiment of the present invention, a single-instruction multiple-data method (hereinafter referred to as " SIMD ") applied to an embodiment of the present invention will be briefly described. do.

2 is a diagram illustrating a data processing method of a SIMD.

As shown in FIG. 2, it can be seen that according to the SIMD method, a plurality of data are processed in parallel by one instruction to output a plurality of results.

Hereinafter, a frame synchronization device according to an embodiment of the present invention will be described as implemented using a processor supporting SSE2.

3 is a diagram illustrating a configuration of a frame synchronization device according to an embodiment of the present invention.

As shown in FIG. 3, the frame synchronization apparatus 100 includes an input data buffer 110, a register unit 120, a controller 130, and an operation unit 140.

The input data buffer 110 temporarily stores a bit string of input data received from the satellite.

Although not shown in FIG. 3, a pending buffer may be further included in order to prevent loss of input data. The pending buffer will be described with reference to FIG. 6.

The register unit 120 includes a first register 122, a second register 124, and a third register 126, each of which may store a 128-bit bit string.

In the first register 122, four bit strings (hereinafter, referred to as 'FSM bit strings for detecting FSM'), in which the bit strings used as the frame synchronization bit pattern are phase-shifted 0 °, 90 °, 180 °, and 270 °, respectively, are sequentially formed. Can be stored as.

Input data may be repeatedly stored in the second register 124 four times in units of 32 bits (4 bytes). A bit string of 4 bytes first received from the bit string received from the outside and temporarily stored in the input data buffer 110 may be repeated four times and stored in the second register 124. If it is determined that the FSM is not an FSM after the FSM detection operation is performed on the corresponding bit string, the bit string shifted one bit back may be repeatedly stored in the second register 124 four times. The bit string received from the outside and input to the second register 124 with a size of 4 bytes will be referred to as an input data bit string.

The third register 126 may store a bit string corresponding to a result of performing an exclusive OR operation on the bit string stored in the first register 122 and the bit string stored in the second register 124.

The first register 122, the second register 124, and the third register 126 correspond to the XMM1 register, the XMM2 register, and the XMM0 register, respectively, for SIMD operations in a processor supporting SSE2.

The controller 130 previously stores four FSM detection bit strings obtained by phase shifting the bit strings used as the frame synchronization bit pattern, respectively, by 0 °, 90 °, 180 °, and 270 °, in the first register 122. For example, the controller 130 may sequentially store the phase shifted bit string for detecting the FSM in the third register 126.

The bit pattern used as the FSM is divided into five types as shown in Table 1 below, which is recommended by the CONSultative Committee for Space Data Systems (CCSDS).

Name Value For non-turbo coded data 1ACFFC1D For rate-1 / 2 turbo coded data 034776C7272895B0 For rate-1 / 3 turbo coded data 25D5C0CE8990F6C9461BF79C For rate-1 / 4 turbo coded data 034776C7272895B0 FCB88938D8D76A4F For rate-1 / 6 turbo coded data 25D5C0CE8990F6C9461BF79C DA2A3F31766F0936B9E40863

In the embodiment of the present invention, 32-bit " 1ACFFC1D " which is non-turbo coded data is used as a bit pattern for the FSM. 4 shows "1ACFFC1D" in a bit string.

Meanwhile, in the embodiment of the present invention, the 32-bit bit string 1ACFFC1D is used as the FSM. However, another bit pattern may be set to the FSM according to the type of processor to be implemented.

The operation unit 140 may perform an exclusive OR operation on the data stored in the first register 122 and the data stored in the second register 124.

The operation unit 140 stores the bit string obtained through the XOR process in the third register 126 and between the four FSM detection bit strings and the input data bit string through the bit string stored in the third register 126. Get Hamming distance value.

Here, the controller 130 detects the FSM by comparing the hamming distance value with a predetermined bit threshold. In more detail, when a hamming distance value smaller than the bit threshold value exists, the input data bit string stored in the second register 124 is determined as the FSM.

When the input data bit string is determined to be an FSM in the search state, the controller 130 copies the frame including the input data bit string to the pending buffer. After that, the controller 130 continuously performs the FSM detection in the checked state. When the FSM is detected, the controller 130 copies the frame to the pending buffer as in the search state and stores the frame in which the FSM is detected until the lock state is reached. After that, when the lock state is reached, both the frames stored in the pending buffer and the frame when the lock state is reached are moved to the next processing stage (not shown). As a result, according to the present invention, data corresponding to a frame before the lock state is lost can be processed without loss.

On the other hand, if there is no hamming distance value smaller than the bit threshold value, it is determined that FSM detection has failed.

At this time, if the FSM is not detected, the controller 130 reads the bit string shifted one bit back from the input data buffer 110 with respect to the input data bit string in which the FSM detection has failed, and repeats it four times to the second register 124. Save and continue to detect the FSM.

Hereinafter, an FSM detection method using SSE2 will be described with reference to FIG. 5.

5 is an exemplary diagram illustrating a bit string stored in a register during an FSM detection process according to an embodiment of the present invention.

As shown in FIG. 5, the XMM1 register, the XMM2 register, and the XMM0 register corresponding to the first register 122, the second register 124, and the third register 126, respectively, are displayed.

Similarly, a 32-bit bit pattern 1ACFFC1D is assumed to be a frame synchronization bit pattern.

The controller 130 stores the first to fourth FSM bit strings (0x1ACFFC1D, 0x4F9AA948, 0xB06556B7, 0xE53003E2) in which the bit patterns 0x1ACFFC1D are phase-transformed into 0 °, 90 °, 180 °, and 270 °, respectively, in the XMM1 register. do.

The 32-bit input data bit string 4F9AA948 is repeatedly stored four times from the input data buffer 110 in the XMM2 register.

That is, the FSM bit string corresponding to each phase is stored in the XMM1 register, and the input data bit string, which is the actual FSM detection target data, is repeatedly stored four times in the XMM2 register.

Here, the operation unit 140 stores the XOR logic operation result of the XMM1 register and the XMM2 register in the XMM0 register.

The Hamming distance values of each group of 32 bits are 16, 0, 32, and 16, respectively, according to the operation result.

In this case, assuming that the set bit threshold value is 2, 32 bits corresponding to 0 having a hamming distance value smaller than 2 become FSM.

Therefore, in the example shown in FIG. 4, the value of the FSM is “0x4F9AA948” and the phase is 90 °.

As such, the controller 130 determines that the FSM detection is successful when a hamming distance value smaller than the bit threshold value appears, and otherwise, determines that the FSM detection has failed.

If it is determined that the FSM detection has failed, the bit string shifted one bit back from the input data buffer 110 with respect to the input data bit string that has failed the FSM detection is stored four times in the XMM2 register.

According to an embodiment of the present invention, an FSM bit string corresponding to four phases is compared with input data in one instruction by using a 128-bit XXM register to detect the FSM. As a result, FSM can be obtained four times faster than arithmetic-free SSE2.

Meanwhile, the speed of FSM detection may be increased by using a pattern search method.

6 is a view showing a pattern search process according to an embodiment of the present invention.

Pattern search is a method of checking whether input data is repeated with the same value.

If no actual data is received from the satellite, the input data of frame synchronization will be a "00" or "FF" byte value. In this case, there is no input data, so there is no need to find the FSM in the search state.

As described above, according to the pattern search method, when the second register 124 stores 4 bytes of input data and the 4 bytes after the 1-bit shift are the same as the stored input data, the controller 130 receives actual data from the satellite. It is regarded as not received.

Then, as shown in FIG. 5, the controller 130 moves to the search state for detecting the FSM from when the bit of the input data corresponding to “1” is input to the second register 124.

Therefore, since the actual satellite data is transmitted from the satellite to the search state, high-speed FSM detection can be efficiently performed.

 On the other hand, since data is often lost during FSM detection on hardware, a pending buffer may be used to prevent data loss.

7 is a diagram illustrating a data storage process using a pending buffer according to an embodiment of the present invention.

As shown in FIG. 7, the input data buffer 110 stores input data in the form of a frame.

Here, the FSM is detected with respect to the frame of the input data, and if a frame of the search state S is found, the FSM is copied and stored in a separate pending buffer 115.

Similarly, if the FSM is detected for a subsequent frame, the detected frame is placed in the checked state C, and the frame of the checked state C is copied to the pending buffer 115 and stored.

In this way, the FSM is detected for the subsequent frame, and then copied and stored in the pending buffer 115.

FIG. 7 illustrates a state in which the frame of the search state S and the frame of the check state C that are input to the input data buffer 110 are copied and stored in the pending buffer 115. It is assumed that the data is input to the input data buffer 110 in units of frames.

In this manner, the frame in the check state C and the frame in the lock state L may be stored in the pending buffer 115 by a check count set by the user.

Therefore, the pending buffer 115 stores the frames of the search state S and the frames of the plurality of check states C, and when the lock state L is reached, the data can be transferred to the next processing stage and processed. Can minimize the loss.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

1 is a diagram illustrating a processing state of frame synchronization of satellite data according to an embodiment of the present invention.

2 is a diagram illustrating a data processing method of a SIMD.

3 is a diagram illustrating a configuration of a frame synchronization device according to an embodiment of the present invention.

Fig. 4 is a diagram showing " 1ACFFC1D " in a bit string.

5 is an exemplary diagram illustrating a bit string stored in a register during an FSM detection process according to an embodiment of the present invention.

6 is a view showing a pattern search process according to an embodiment of the present invention.

7 is a diagram illustrating a data storage process using a pending buffer according to an embodiment of the present invention.

Claims (12)

(a) storing first to fourth FSM bit strings having the predetermined bit patterns phase shifted by 0 °, 90 °, 180 °, and 270 °, respectively, in a first register; (b) repeating the input data bit string four times and storing it in a second register; (c) storing a bit string corresponding to a result of performing an exclusive OR on the bit strings stored in the first register and the second register in a third register; (d) obtaining a Hamming distance value between the input data bit string and the first to fourth FSM bit strings from the bit string stored in the third register, respectively; And  and (e) determining whether the input data bit string is an FSM based on the obtained Hamming distance value. The method of claim 1, And determining that the input data bit string is an FSM when there is a value smaller than a predetermined threshold value among the obtained hamming distance values. The method of claim 1, Determining that the input data bit string is not an FSM if none of the obtained Hamming distance values is smaller than a predetermined threshold; And, If it is determined that the input data bit string is not an FSM, repeating the bit string shifted one bit back to the input data bit string in the input data buffer four times and storing it in the second register; Frame synchronization method characterized in that it further comprises. The method of claim 3, wherein If the bit string shifted one bit back is the same as the input data bit string, determining that the bit string shifted one bit back is not an FSM; Frame synchronization method characterized in that it further comprises. The method of claim 4, wherein And repeating steps (c) to (e) with respect to the bit string shifted one bit back if the bit string shifted one bit back is not the same as the input data bit string. The method of claim 1, If the input data bit string is determined to be an FSM, copying a frame including the input data bit string to a pending buffer; Frame synchronization method characterized in that it further comprises. A first register for storing first to fourth FSM bit strings obtained by converting a predetermined bit pattern into 0 °, 90 °, 180 °, and 270 ° phases, respectively; A second register for repeatedly storing the input data bit string four times; A third register configured to store a bit string corresponding to a result of performing an exclusive OR between the bit strings stored in the first register and the second register; And, A control unit which obtains a Hamming distance value between the input data bit string and the first to fourth FSM bit strings from the bit string stored in the third register, and determines whether the input data bit string is FSM based on the obtained Hamming distance value ; Frame synchronization apparatus comprising a. The method of claim 7, wherein The control unit, And if there is a value smaller than a predetermined threshold value among the obtained hamming distance values, determine that the input data bit string is an FSM. The method of claim 7, wherein The control unit, If there is no smaller value than a predetermined threshold value among the obtained hamming distance values, it is determined that the input data bit string is not FSM, If it is determined that the input data bit string is not the FSM, the frame synchronization is repeated such that the bit string shifted one bit backward with respect to the input data bit string in the input data buffer is stored four times. Device. The method of claim 9, The control unit, And if the bit string shifted one bit back is the same as the input data bit string, determining that the bit string shifted one bit back is not an FSM. The method of claim 10, The control unit, And if the bit string shifted back one bit is not the same as the input data bit string, performing FSM detection on the bit string shifted one bit back. The method of claim 7, wherein The control unit, And when the input data bit string is determined to be an FSM, copying a frame including the input data bit string to a pending buffer.

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