KR20090041196A - Nonvolatile Memory Device, Method and System for Manufacturing the Same - Google Patents

Abstract

The present invention relates to a nonvolatile memory device including a charge trap layer, a method of manufacturing the same, and a system including the same. A nonvolatile memory device according to an embodiment of the present invention may include a semiconductor substrate including first and second source / drain regions and a channel region between the source / drain regions; A lower insulating film having a first dielectric constant sequentially stacked on the channel region of the semiconductor substrate, a charge trap film, an upper insulating film having a second dielectric constant smaller than the first dielectric constant, and a control gate electrode; The trapping center within is distributed near the interface of the upper insulating film / charge trap film.

Description

Nonvolatile memory device, method and fabrication method thereof Non-volatile memory device, method of fabricating the same and system incorporating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, a method and system for manufacturing the same, and more particularly, to a nonvolatile memory device including a charge trap layer, a method for manufacturing the same, and a system including the same.

A nonvolatile memory device is a memory device capable of retaining stored information even when a power supply is cut off. Recently, as the demand for small electronic products such as a portable multimedia playback device, a digital camera, and a PD increases, a large capacity and high integration of a nonvolatile memory device applied thereto is rapidly progressing.

BACKGROUND OF THE INVENTION As a nonvolatile memory device, a flash memory device in which erase and rewrite operations are performed in block units at a time is widely used. As an example of a flash memory device, a charge trap type nonvolatile memory using a silicon-oxide-nitride-oxide-silicon (SONOS) gate stack is representative. In the SONOS type memory device, the nitride film provides a nonvolatile memory function by trapping electrons or holes to change the threshold voltage Vth of the transistor. The SONOS memory device is widely replacing the conventional floating gate type nonvolatile memory device due to its low programming voltage, smaller cell size, and excellent data retention.

In general, these nonvolatile memory devices require excellent data retention characteristics such that the threshold voltage does not decrease with time even after repeated programming / erase operations. In the case of a flash memory, a relatively high voltage is required to perform a programming / erase operation. Therefore, deterioration may occur in various material layers including a tunneling oxide layer constituting a flash memory cell, which may degrade data retention characteristics. have.

In addition, in the flash memory device, charge trapped in the tunneling oxide film or the interface trap between the silicon substrate and the tunneling oxide film may be gradually accumulated by repeated programming / erase operations. These trapped charges generate stress-induced leakage current (SILC) by trap-assisted tunneling (TAT), which degrades data retention characteristics. In particular, as the integration degree of the flash memory device is increased and the cell size is reduced, the generation and destruction of the interface trap is a significant factor in deterioration of data retention characteristics.

FIG. 1 is a graph showing a relationship between a drain current Id and a gate voltage Vg for explaining a deterioration phenomenon of data retention characteristics in a nonvolatile memory device having a conventional SONOS structure. The graphs are for flash memory cells that repeat at least 10 ³ cycles of programming operations performed at about 17.1 V for 100 μS and erase operations for about 25 ms at about −19.0 V, each at 200 ° C. for 2 hours. Measurement results for programmed flash memory cells before and after a bake. In Fig. 1, the Id-Vg curve indicated by the curve I represents the measured value before baking, and the Id-Vg curve indicated by the curve F represents the measured value after the baking.

The charge trapped in the charge trap film by the bake process and the charge trapped in the interface trap between the tunneling insulating film / semiconductor substrate are de-trapping so that the programmed information is lost. The dashed line L is a straight line with a slope for qualitatively evaluating the midgap voltage shift for a current of 10 ^-12 A. The shift ΔV _{th1 of the midgap} voltage due to the bake process is about _0.66V . The decrease in V _th1 is due to the leakage of charge trapped in the charge trap film.

In comparison, ΔV _th2 for a current of 10 ⁻⁷ A is about 1.08 V. The difference ΔV _thx between the dotted line and the curve F in ΔV _th2 is due to the leakage of charge trapped in the charge trap film, as in the case of ΔV _th1 . Thus, the difference ΔV _thy of the voltage value between the dashed line and the curve I can be interpreted as due to the loss of the interface trap by baking. Considering the magnitudes of ΔV _thx and ΔV _thy , it can be seen that the reduction of V _th2 is more affected by the contribution due to the loss of the interface trap than the leakage of the charge trapped in the charge trap film. In particular, as the channel width decreases as the density of flash memory devices increases, a decrease in V _th value due to the loss of the interface trap over time must be considered to improve data retention characteristics of flash memory cells. Is considered.

Therefore, the technical problem to be achieved by the present invention is a ratio that can improve the degradation of data retention characteristics due to the loss of the interface trap charge between the tunneling insulating film and the channel region, which becomes more important as the integration degree of the nonvolatile memory device increases. To provide a volatile memory device and a system including the same.

Another object of the present invention is to provide a method of manufacturing the nonvolatile memory device described above.

From the experiments, the inventors confirmed that electrons tunneling through the tunneling oxide film continuously damage the interface between the semiconductor substrate and the tunneling insulating film while losing energy. This damage increases the interfacial trap site at the interface between the semiconductor substrate and the tunneling insulating film, thereby increasing the number of charges trapped at the interfacial trap site and decreasing Vth due to the loss of trapped charge over time, It was confirmed that data retention characteristics deteriorated. The nonvolatile memory device according to various embodiments of the present disclosure provides a gate structure capable of modifying a conventional programming / erase operation method that causes generation of an interface trap site.

A nonvolatile memory device according to an embodiment of the present invention may include a semiconductor substrate including first and second source / drain regions and a channel region between the source / drain regions; A lower insulating film having a first dielectric constant sequentially stacked on the channel region of the semiconductor substrate, a charge trap film, an upper insulating film having a second dielectric constant smaller than the first dielectric constant, and a control gate electrode; The trapping center within is distributed near the interface of the upper insulating film / charge trap film.

In some embodiments, the charge trap layer may include a silicon nitride layer having an oxide layer near an interface between the upper insulating layer and the charge trap layer. In another embodiment, the charge trap layer may include a silicon-rich oxynitride (SRON) near an interface between the upper insulating layer and the charge trap layer. In another embodiment, the charge trap layer may include nanocrystals near an interface between the upper insulating layer and the charge trap layer.

In some embodiments, the nonvolatile memory device may be programmed and erased by tunneling through an upper insulating layer. In some embodiments, the nonvolatile memory device may be programmed by hot carrier injection through a lower insulating layer, and an erase operation may be performed by tunneling through the upper insulating layer.

In another embodiment of the present invention, a system according to an embodiment of the present invention includes a memory array comprising the nonvolatile memory cells of claims 1 to 9 arranged in a plurality of rows and columns; Memory interface; And a control circuit coupled between the memory interface and the memory array; And a host coupled with the memory device. In some embodiments, the host can be a processing device or a memory controller.

In still another aspect of the present invention, a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention includes providing a semiconductor substrate including an active region; Forming a lower insulating film having a first dielectric constant sequentially on the active region; Forming a charge trap layer on the lower insulating layer; Forming an upper insulating film having a second dielectric constant less than the first dielectric constant; Forming a control gate electrode on the upper insulating film; And forming first and second source / drain regions spaced apart by a control gate electrode in an active region of the semiconductor substrate, wherein an effective charge trap site in the charge trap layer is formed of the upper insulating film / charge trap layer. It is distributed near the interface.

In the nonvolatile memory device of the present invention, an erase operation can be easily performed by tunneling through the upper insulating film using the upper insulating film having a dielectric constant smaller than that of the lower insulating film. Since the erase operation takes place between the charge trap film and the control gate electrode, the interface trap site resulting from the interface damage between the semiconductor substrate and the lower insulating film is suppressed, and the deterioration of the data retention characteristic by the interface trap site is improved. In addition, since the trapping center in the charge trap film is distributed near the interface between the upper insulating film and the charge trap film, the efficiency and speed of the erase operation are increased, and the deterioration stored in the semiconductor substrate is not de-trapped so that the data retention characteristics can be improved.

In addition, according to an embodiment of the present invention, a system having improved data retention characteristics and an efficiency and speed of an erase operation may be provided. In addition, the method of manufacturing a nonvolatile memory device according to an embodiment of the present invention can provide a method of manufacturing a nonvolatile memory device having the above characteristics.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art, and the following examples can be modified in various other forms, and the scope of the present invention is It is not limited to an Example. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

In the following description, when a layer is described as being on top of another layer, it may be directly on top of another layer, and a third layer may be interposed therebetween. In addition, the thickness or size of each layer in the drawings is exaggerated for convenience and clarity, the same reference numerals in the drawings refer to the same elements. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" may include the plural forms as well, unless the context clearly indicates otherwise. Also, as used herein, "comprise" and / or "comprising" specifies the presence of the shapes, numbers, steps, actions, members, elements and / or groups mentioned. It is not intended to exclude the presence or addition of one or more other shapes, numbers, acts, members, elements and / or groups.

Although the terms first, second, etc. are used herein to describe various members, parts, regions, layers, and / or parts, these members, parts, regions, layers, and / or parts are defined by these terms. It is obvious that not. These terms are only used to distinguish one member, part, region, layer or portion from another region, layer or portion. Thus, the first member, part, region, layer or portion, which will be discussed below, may refer to the second member, component, region, layer or portion without departing from the teachings of the present invention.

Embodiments of the present invention will now be described with reference to the drawings, which schematically illustrate ideal embodiments of the present invention. In the figures, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to the specific shapes of the regions shown herein, but should include, for example, changes in shape resulting from manufacturing. As used herein, a nonvolatile memory device refers to a memory device having a charge trap film, and is not limited by such terms as flash memory or EEPROM.

2 is a cross-sectional view illustrating a unit cell 1000 of a nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 2, a cell 1000 of a nonvolatile memory device includes a channel region between a first source / drain region 101 and a second source / drain region 102 and a source / drain regions 101 and 102. The semiconductor substrate 100 including the 103 and the lower insulating film 200, the charge trap film 300, the upper insulating film 400 and the control gate electrode 500 sequentially stacked on the semiconductor substrate 100 are included. do. The cell 1000 of the nonvolatile memory device sequentially stacks and patterns the lower insulating material layer, the charge trap material layer, the upper insulating material layer, and the control gate conductive layer on the active region of the semiconductor substrate 100 in order. After the gate stack 600 including the insulating film 200, the charge trap film 300, the upper insulating film 400, and the control gate electrode 500 is formed, the first and first portions are formed in the active region of the semiconductor substrate 102. By forming two source / drain regions 101 and 102.

The control gate electrode 500 according to the embodiment of the present invention may be formed of aluminum, tungsten, polysilicon, or another conductive material, and may be electrically connected to a word line or a control line. One of the first and second source / drain regions 101 and 102 may be connected to a source line and the other may be connected to a bit line. The lower insulating film 200, the charge trap film 300, and the upper insulating film 400 according to the exemplary embodiment of the present invention will be described later with reference to FIGS. 3 and 4A to 4C.

In the conventional SONOS device, the semiconductor substrate 100 acts as a charge sink during an erase operation. However, in the nonvolatile memory device of the present invention, the control gate electrode 500 acts as a charge sink. For example, when an erase voltage is applied between the control gate electrode 500 and the semiconductor substrate 100, the charge stored in the charge trap layer 300 is controlled by the Fowler-Nordheim tunneling method through the upper insulating layer 400. The gate electrode 500 is extracted. Therefore, according to the embodiment of the present invention, since the extraction of the charge occurs between the charge trap layer 300 and the control gate electrode 500, the interface between the semiconductor substrate 100 and the lower insulating film 100 even if the erase operation is repeated. Does not cause damage.

Further, in some embodiments, the control gate electrode 500 can be driven to act as a charge source during programming operations. For example, when a programming voltage is applied between the control gate electrode 500 and the semiconductor substrate 100, the charge trap film (at the control gate electrode 500) through the upper insulating film 400 by the Fowler-Nordheim tunneling method. Charge 300 is injected into 300. Optionally, the semiconductor substrate 100 may be driven to act as a charge source in consideration that the programming operation does not affect the interface damage between the semiconductor substrate 100 and the lower insulating film 200. For example, a predetermined voltage is applied between the first source / drain region 101 and the second source / drain region 102 and the channel is formed through the lower insulating layer 200 by a hot carrier injection method. A programming scheme in which charge is injected into the charge trap film 300 from the region 103 may be adopted.

As described above, in the embodiment of the present invention, the erase operation is performed by tunneling through the upper insulating film 400. Hereinafter, embodiments of the present invention that can improve the tunneling efficiency through the upper insulating film 400 will be described in more detail.

3 is an energy band model for explaining an erase operation of a nonvolatile memory device according to an exemplary embodiment of the present invention. Referring to FIG. 3 along with FIG. 2, the dielectric constant ε 2 of the upper insulating layer 400 in the gate stack 600 is smaller than the dielectric constant ε 1 of the lower insulating layer 200. In an embodiment of the present invention, the lower insulating film 200 may be a silicon oxide film or another high dielectric constant insulating film. The high dielectric constant insulating film is, for example, made of any one of silicon oxynitride film, aluminum oxide film, lanthanum oxide film, lanthanum aluminum oxide film, hafnium oxide film, hafnium aluminum oxide film, lanthanum hafnium oxide film, zirconium oxide film and tantalum oxide film or a combination thereof. It may also include a multilayer film. The high dielectric constant insulating film is disclosed as an example, and the present invention is not limited by these materials. These films may be formed by chemical vapor deposition, atomic layer deposition, or the like, as is well known in the art.

The upper insulating film 400 may be formed of a silicon oxide film, and the silicon oxide film may be formed by a chemical vapor deposition method as is well known in the art. Since the silicon oxide film provides a relatively high energy barrier of 3.2 eV and 4.7 eV for electrons and holes, the programming voltage and the driving power can be large. The silicon oxide film is disclosed as an example, and the present invention is not limited thereto. For example, instead of the silicon oxide film as the upper insulating film 400, other high dielectric constant materials having a dielectric constant ε 2 smaller than the dielectric constant ε 1 of the lower insulating film 200, for example, silicon oxynitride film, aluminum oxide film, and lanthanum. High dielectric constant materials such as an oxide film, a lanthanum aluminum oxide film, a hafnium oxide film, a hafnium aluminum oxide film, a lanthanum hafnium oxide film, a zirconium oxide film and a tantalum oxide film may be selected and used. The low tunneling barrier of the high dielectric constant material has the advantage of providing high tunneling current even under low programming / erase voltages. In addition, the upper insulating film 400 may be formed as a single film or a multilayer film in which at least two or more of the above-described films are stacked as necessary. These films may be formed by chemical vapor deposition, atomic layer deposition, or the like as is well known in the art.

As described above, when the dielectric constant ε2 of the upper insulating film is smaller than the dielectric constant ε1 of the lower insulating film, the erase voltage applied between the control gate electrode 500 and the semiconductor substrate 100 is mostly the upper insulating film 400. ) May be coupled to. As a result, as shown in FIG. 3, the energy band of the upper insulating layer 400 is more distorted than the energy band of the lower insulating layer 200. Therefore, tunneling occurs more easily through the upper insulating film 400 than the lower insulating film 200 when the erase voltage is applied. If a high dielectric constant insulating film is used as the lower insulating film 200 and the high dielectric constant insulating film is physically thick, tunneling of electrons and holes that may occur between the channel region 103 and the charge trap film 300 is suppressed during the erase operation. And data retention characteristics can be improved.

The charge trap layer 300 is formed such that the trapping center TC of electrons or holes is distributed near the interface between the upper insulating layer 400 and the charge trap layer 300. In the charge trap layer 300, as the trapping center TC is distributed toward the upper insulating layer 400, tunneling or leakage current through the lower insulating layer 200 may be reduced. On the other hand, when an erase voltage is applied between the control gate electrode 500 and the semiconductor substrate 100, tunneling of the charge through the upper insulating film 400 can easily occur, the erase efficiency and the erase speed can be improved. have. However, in view of the data retention characteristic, it is preferable that the trapped charge is not easily de-wrapped from the trapping center TC to the control gate electrode 500 over time. In some embodiments, as the upper insulating film 400, a multilayer film in which at least two or more films are stacked may be applied to suppress charge leakage to the control gate electrode. Optionally, a method of forming a trapping center capable of providing deep potential wells to suppress detrapping can be considered. Hereinafter, a charge trap film according to various embodiments of the present invention having excellent detrapping suppression force for improving data retention characteristics will be described in detail.

4A through 4C are cross-sectional views illustrating nonvolatile memory devices 2000, 3000, and 4000 including charge trap layers 310, 320, and 330 according to various embodiments of the present disclosure. In these figures, components having the same reference numerals as those shown in FIG. 2 are the same as those described above with reference to FIG.

Referring to FIG. 4A, the charge trap layer 310 may be formed of a silicon nitride layer. In this case, in order to provide a trapping center TC near the interface between the upper insulating film / charge trap film, the surface of the silicon nitride film may be oxidized to form a silicon oxynitride film (SiOxNy) 310a. For example, the silicon nitride layer 310 may be formed on the lower insulating layer 200, and then the upper surface of the silicon nitride layer 310 may be oxidized to a predetermined depth. The oxidation treatment may be performed by, for example, exposing a semiconductor substrate on which the silicon nitride film 310 is formed to an oxygen plasma or annealing in an oxygen atmosphere.

Referring to FIG. 4B, the charge trap layer 320 may include an insulating layer 320a such as a silicon nitride layer or a silicon oxide layer and a silicon-rich oxynitride (SRON) 320b formed thereon. The SRON film 320b may provide an excellent trapping center TC near the interface between the charge trap film 320 and the upper insulating film 400. For example, the SRON film 320b may be formed on the silicon nitride film or the silicon oxide film 320a by using a silicon-containing gas, such as O2, O3, N2, NH3, N2O, or the like, for example, oxygen-containing gas and nitrogen-containing gas. For example, it may be formed by chemical vapor deposition which provides a source gas so that the partial pressure ratio of the SiH 4 gas is greater.

Referring to FIG. 4C, the charge trap layer 330 may include nanocrystals 330b near an interface between the upper insulating layer 400 and the charge trap layer 330. The nanocrystals 330b may be formed of at least one of a metal, a semiconductor, or a high dielectric constant material, as is well known in the art. The metal may be, for example, any one of Pt, Pd, Ni, Ru, Co, Cr, Mo, W, Mn, Fe, Ru, Os, Ph, Ir, Ta, Au, and Ag or an alloy thereof. . In addition, the semiconductor is a single element such as Si and Ge or SiC, SiGe, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeS It may be a compound of two or more elements such as HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS and HgZnSe. In addition, the high dielectric constant material may be HfO ₂ , ZrO ₂ , Al ₂ O ₃ , HfSiO, HfSiON, HfON and HfAlO. The materials of the above-described nanocrystals are merely exemplary, and the present invention is not limited thereby.

The nanocrystal 330b may be provided in a form inserted into the matrix 330a constituting the charge trap layer 330, and the matrix 330a may be formed of silicon nitride or silicon oxynitride. Nanocrystals 330b may be formed by methods known in the art. For example, after forming the matrix 330a and implanting ions of the material to be nanocrystal into the matrix 330a, the implanted ions may be grown to a predetermined size by appropriate heat treatment. Alternatively, a thin layer may be formed on the material layer to be the matrix 330a by chemical vapor deposition or atomic layer deposition, and then the material layer or another material layer to be the matrix 330a is grown on the thin layer, followed by heat treatment. Crystal 330b may be formed. Nanocrystal 330b has a high work function and thus provides a deep potential well, preventing leakage of trapped charges and improving data retention characteristics.

5 is a block diagram illustrating a system 10 including a nonvolatile memory device 5000 of the present invention.

Referring to FIG. 5, semiconductor memory cells according to various embodiments of the present disclosure may be arranged in “NAND” and “NOR” architecture arrays corresponding to a logic gate design as is well known in the art. Memory arrays arranged in a plurality of rows and columns constitute one or more array banks 5100. A sense amplifier is disposed in the array bank 5100. As is well known in the art, the nonvolatile memory device 5000 may include a row decoder 5200, a column decoder 5300, I / O buffers 5310 and 5320, and a controller for driving the memory bank 5100. 5400, the control register 5500 is further included.

The nonvolatile memory device 5000 is generally coupled to a host 6000 that is a memory controller or processing device such as a microprocessor. The nonvolatile memory device 5000 may further include an address interface 5610, a control interface 5620, and a data interface 5630 for memory read and write access of the host 6000. The above-described interfaces 5610, 5620, and 5630 may be modified in various ways as is well known in the art. For example, it may be a synchronous interface such as an SDRAM or DDR-SDRAM interface.

Those skilled in the art will see from the present disclosure that the nonvolatile memory device of the embodiments of the present invention is not limited to a 2-bit flash memory device, but also a multi-bit flash memory device in which an erase operation is performed through a control gate electrode. It will be understood that it belongs to the scope of the invention.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and alterations are possible within the scope without departing from the technical spirit of the present invention, which are common in the art. It will be apparent to those who have knowledge.

FIG. 1 is a graph showing a relationship between a drain current Id and a gate voltage Vg for explaining a deterioration phenomenon of data retention characteristics in a nonvolatile memory device having a conventional SONOS structure.

2 is a cross-sectional view illustrating a unit cell of a nonvolatile memory device according to an exemplary embodiment of the present invention.

3 is an energy band model for explaining an erase operation of a nonvolatile memory device according to an exemplary embodiment of the present invention.

4A through 4C are cross-sectional views illustrating a nonvolatile memory device including a charge trap layer according to various embodiments of the present disclosure.

5 is a block diagram showing a system including the nonvolatile memory device of the present invention.

Explanation of symbols on the main parts of the drawings

100: semiconductor substrate 101, 102: first and second source / drain regions

103: channel region 200: lower insulating film

300, 310, 320, 330: charge trapping film

400: upper insulating film 500: control gate electrode

Claims (16)

A semiconductor substrate comprising first and second source / drain regions and a channel region between the source / drain regions; A lower insulating film having a first dielectric constant sequentially stacked on the channel region of the semiconductor substrate, a charge trap film, an upper insulating film having a second dielectric constant smaller than the first dielectric constant, and a control gate electrode, The trapping center in the charge trap film is distributed near the interface between the upper insulating film and the charge trap film. The method of claim 1, And the charge trap film includes a silicon nitride film having an oxide layer near an interface between the upper insulating film and the charge trap film. The method of claim 1, The charge trap layer includes a silicon-rich oxynitride (SRON) near an interface between the upper insulating layer and the charge trap layer. The method of claim 1, And the charge trap layer includes nanocrystals near an interface between the upper insulating layer and the charge trap layer. The method of claim 1, The nanocrystal includes at least one of a metal, a semiconductor, and a high-k material. The method of claim 1, The lower insulating layer may include at least one of silicon oxide film, silicon oxynitride film, aluminum oxide film, lanthanum oxide film, lanthanum aluminum oxide film, hafnium oxide film, hafnium aluminum oxide film, lanthanum hafnium oxide film, zirconium oxide film, and tantalum oxide film, or a combination thereof. Memory elements. The method of claim 1, The upper insulating film includes any one or both of a CVD oxide film and a thermal oxide film. The method of claim 1, The nonvolatile memory device may be programmed and erased by tunneling through an upper insulating layer. The method of claim 1, The nonvolatile memory device may include a programming operation by hot carrier injection through a lower insulating layer, and an erase operation by tunneling through the upper insulating layer. A memory array comprising a nonvolatile memory cell of claim 1 arranged in a plurality of rows and columns; Memory interface; And a control circuit coupled between the memory interface and the memory array; And And a host coupled with the memory device. The method of claim 8, The host is a processing device or memory controller The method of claim 10, And the array is a NOR architecture or a NAND architecture array. Providing a semiconductor substrate comprising an active region; Forming a lower insulating film having a first dielectric constant sequentially on the active region; Forming a charge trap layer on the lower insulating layer; Forming an upper insulating film having a second dielectric constant less than the first dielectric constant; Forming a control gate electrode on the upper insulating film; And Forming first and second source / drain regions spaced apart by a control gate electrode in an active region of the semiconductor substrate, The effective charge trap site in the charge trap film is distributed near the interface between the upper insulating film and the charge trap film. The method of claim 13, wherein the forming of the charge trap layer comprises: Depositing a silicon nitride film on the lower insulating film; And And oxidizing a surface of the silicon nitride film. The method of claim 13, wherein the forming of the charge trap layer comprises: Depositing a silicon nitride film or a silicon oxide film on the lower insulating film; And And depositing a silicon over-oxygen nitride film on the deposited silicon nitride film or silicon oxide film. The method of claim 15, And the silicon over-oxygen nitride film is formed by adjusting the partial pressure ratio of the silicon-containing gas to any one or both of the oxygen-containing gas and the nitrogen-containing gas.

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