KR20090034137A - Array board for transverse electric field type liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

An array panel for a liquid crystal display and a manufacturing method thereof in a plane switching mode minimizing the parasitic capacitance are provided to implement high aperture ratio by minimizing parasitic capacitance between the vertical of data line and the common wire. A gate line is comprised in the top of the substrate task. A data line defines the gate line and a pixel region by vertically crossing the gate line. A TFT(Thin Film Transistor) is comprised in the crossing point of data line and gate line. A horizontal unit is parallel located in the gate line. A vertical unit is extended to the top or the lower part overlapped with data line. An organic film pattern(288) is interposed between the common line and data line. The pixel electrode and common electrode are connected to TFT and common wire. It corresponds to the pixel region and the pixel electrode and common electrode are comprised. The gate line and common line are comprised of the same material in the same layer.

Description

An array substrate for a transverse electric field type liquid crystal display device and a method of manufacturing the same {An Array Substrate of In-Plane Switching Mode Liquid Crystal Display Device and the method for fabricating example}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to a high aperture ratio in an array substrate for a transverse electric field type liquid crystal display device in which a common electrode and a pixel electrode are formed on the same surface.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization property of the liquid crystal. The liquid crystal has a long and thin structure, and thus has a directivity in the arrangement of molecules. Can be controlled.

Accordingly, when the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, active matrix LCDs (AM-LCDs) in which thin film transistors and pixel electrodes connected to the thin film transistors are arranged in a matrix manner are attracting the most attention because of their excellent resolution and video performance.

The liquid crystal display has a structure in which a pixel electrode is formed on a lower substrate and a common electrode is formed on an upper substrate, and the liquid crystal molecules are driven by an electric field in a direction perpendicular to the substrate applied between the two electrodes. Excellent characteristics, such that the common electrode of the upper substrate serves as a ground can prevent the destruction of the liquid crystal cell due to static electricity.

However, such a liquid crystal display device has a disadvantage that the viewing angle characteristics are not excellent. Various methods have been proposed to overcome these disadvantages, one example of which is an in-plane switching mode liquid crystal display device.

Hereinafter, a transverse electric field type liquid crystal display device according to the related art will be described with reference to the accompanying drawings.

1 is a plan view illustrating a unit pixel of an array substrate for a transverse electric field type liquid crystal display according to an exemplary embodiment.

As shown in the drawing, the gate line 20 is formed on one side of the substrate 10, and the data line 30 is formed in a direction perpendicular to the gate line 20. In addition, the common wiring 50 is formed to be spaced apart in parallel with the gate wiring 20.

In this case, an area defined by the gate line 20 and the data line 30 perpendicular to each other is referred to as a pixel area P. FIG. The thin film transistor T is formed at the intersection point of the gate line 20 and the data line 30.

The thin film transistor T extends from a gate electrode 25 extending from the gate line 20, a semiconductor layer (not shown) on the gate electrode 25, and extending from the data line 30 and in contact with the semiconductor layer. A source electrode 32 and a drain electrode 34 spaced apart from the source electrode 32.

The semiconductor layer (not shown) includes an active layer 40 made of pure amorphous silicon (a-Si: H) and an ohmic contact layer (not shown) made of amorphous silicon (n + a-Si: H) containing impurities. Include.

The pixel electrode 70 in contact with the drain electrode 34 through the drain contact hole CH1 exposing a portion of the drain electrode 34 is configured to correspond to the pixel region P. Referring to FIG.

In this case, the pixel electrode 70 includes a plurality of extension parts 70a contacting the drain electrode 34 and vertically branched into the pixel area P in parallel with the data line 30 in the extension part 70a. It includes a vertical portion 70b. In general, the pixel electrode 70 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The pixel region P includes a plurality of common electrodes 60 that are alternately spaced apart from each other in parallel with the pixel electrode 70.

In this case, the common electrode 60 is formed in the same pattern as the common wiring 50, and a plurality of common electrodes 60 are vertically branched from the common wiring 50 to the pixel region P. Although not shown in the drawings, the plurality of common wires 50 may be designed to have only one of an upper side and a lower side according to the pixel design.

In this case, the common electrode 60 corresponding to the pixel areas P on both sides of the data line 30 is parallel to the data line 30 at a predetermined interval from the data line 30.

The direction of the liquid crystal may be controlled through a horizontal electric field between the pixel electrode vertical parts 70b and the common electrode 60 that are alternately arranged in parallel in the pixel area P.

However, the above-described configuration is a situation where not only the common electrode 60 is made of an opaque conductive metal material, but also the drop of the aperture ratio due to the separation between the data line 30 and the common electrode 60 is inevitable.

In order to solve this problem, a method of configuring the common electrode 60 and the pixel electrode 70 with a transparent conductive metal material is mainly used, which will be described in detail with reference to the accompanying drawings.

FIG. 2 is a plan view showing unit pixels of an array substrate for a transverse electric field liquid crystal display device according to another exemplary embodiment. In detail, FIG. 2 is an array for a transverse electric field liquid crystal display device in which a common electrode and a pixel electrode are made of a transparent conductive metal material. It relates to a substrate.

As illustrated, the gate line 120 is formed in one direction on the substrate 102, and the data line 130 is formed in a direction perpendicular to the gate line 120.

The common wiring 150 is spaced apart from the gate wiring 120, and the common wiring 150 includes a plurality of horizontal parts 150a spaced in parallel with the gate wiring 120 and the plurality of horizontal parts. And a plurality of vertical portions 150b extending vertically at 150a. The plurality of common wire vertical parts 150b are spaced apart from each other so as to be parallel to the data wire 130.

In this case, the region defined by the vertical intersection of the gate line 120 and the data line 130 is referred to as a pixel area P. The thin film transistor T is formed at an intersection point of the gate line 120 and the data line 130.

The thin film transistor T may include a gate electrode 125 extending from the gate wiring 120, a semiconductor layer (not shown) on the gate electrode 125, and extending from the data wiring 130 and in contact with the semiconductor layer. The source electrode 132 and the drain electrode 134 spaced apart from the source electrode 132.

The semiconductor layer (not shown) includes an active layer 140 made of pure amorphous silicon (a-Si: H) and an ohmic contact layer (not shown) made of amorphous silicon (n + a-Si: H) containing impurities. Include.

The pixel electrode 170 in contact with the drain electrode 134 through the drain contact hole CH2 exposing a part of the drain electrode 134 is configured to correspond to the pixel region P. Referring to FIG.

In this case, the pixel electrode 170 includes a plurality of extensions 170a which are in contact with the drain electrode 134 and vertically branched into the pixel region P in parallel with the data line 130 at the extension 170a. It includes a vertical portion (170b).

The pixel region P includes a plurality of common electrodes 160 that are alternately spaced apart from each other in parallel with the pixel electrode 170. The common electrode 160 is in contact with the common wire 150 through the common contact hole CH3 exposing a part of the common wire 150, and the pixel area (eg, in the extension part 160a). And a plurality of vertical portions 160b vertically branched in the direction P). In this case, the pixel electrode 170 and the common electrode 160 are made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In the array substrate for a transverse electric field type liquid crystal display device having the above-described configuration, the aperture ratio is one of important factors influencing the panel characteristics, which will be described in detail with reference to the accompanying drawings.

FIG. 3 is a cross-sectional view taken along the line II-II of FIG. 2 and illustrates a state in which an array substrate and a color filter substrate are opposed to each other.

As illustrated, the color filter substrate 105 and the array substrate 107 divided into the display area AA and the non-display area NAA face each other with a constant cell gap, and the color filter and the array substrate 105 are bonded to each other. , 107 is interposed between the liquid crystal layer 109. In this case, the color filter, the array substrates 105 and 107, and the liquid crystal layer 109 may be referred to as a liquid crystal panel 110.

The lower surface of the transparent substrate 101 of the color filter substrate 105 is sequentially patterned with a black matrix 112 for shielding light incident to the non-display area NAA and the black matrix 112. The color filter layer 114 including the red, green, and blue sub color filters 114a, 114b (not shown), and the upper alignment layer 116 formed under the color filter layer 114 are sequentially disposed.

Meanwhile, the common wiring vertical portion 150b is disposed on both sides of the array substrate 107 and spaced apart from the data region D, and the inorganic insulating material is disposed on the common wiring vertical portion 150b. The gate insulating layer 145 is configured as one selected from the group.

The data line 130 is formed on the gate insulating layer 145 to correspond to the data area D, and an inorganic insulating material including silicon oxide (SiO ₂ ) and silicon nitride (SiNx) on the data line 130. The protective film 155 is formed of one selected from the group.

In addition, the common electrode vertical portion 160b is formed on both sides of the passivation layer 155 spaced apart from the data line 130 at a predetermined interval so that the common wiring vertical portion 150b and a part of the area overlap each other. The lower alignment layer 118 is positioned on the electrode vertical portion 160b.

In this case, as shown in FIG. 2, the common electrode vertical part 160b and the common wiring vertical part 150b are connected to each other through a common contact hole (CH3 of FIG. 2) and a common voltage generator (not shown). The common signal from the (common signal) is received.

Therefore, in order to prevent parasitic capacitance between the common wiring vertical portion 150b or the common electrode vertical portion 160b and the data wiring 130, the capacitors are designed to be spaced apart from each other at regular intervals. The common electrode vertical portion 160b is designed to be close to the data wiring 130 for the purpose of improving the aperture ratio, and is designed such that a part of the area overlaps with the common wiring vertical portion 150b.

In this case, when the data wiring 130 and the common wiring vertical part 150b are designed to overlap, the aperture ratio can be improved more drastically, but the quality of the film is between the data wiring 130 and the common wiring vertical part 150b. Is interposed with a gate insulating film 145 made of an inorganic insulating material having a high dielectric constant, and thus crosstalk due to a distortion of the data signal due to parasitic capacitance between the data line 130 and the common line vertical portion 150b. There is a high possibility of poor image quality.

For this reason, the data line 130 and the common electrode vertical portion 160b and the data line 130 and the common electrode vertical portion 160b and the common wiring vertical portion 150b are designed to be spaced apart at a predetermined interval. It is inevitable that the aperture ratio is inevitable due to the black matrix 112 having sufficient margin to shield the light incident to the common wiring vertical part 150b.

The present invention has been made to solve the above-described problem, and an object of the present invention is to realize a high opening ratio through minimizing parasitic capacitance between the data line and the common line vertical part.

An array substrate for a transverse electric field type liquid crystal display device according to the present invention for achieving the above object is a gate wiring formed in one direction on the substrate, a data wiring defining a pixel region perpendicular to the gate wiring, and the gate wiring A common wiring including a thin film transistor configured at an intersection point of the data wiring, a horizontal portion spaced in parallel with the gate wiring, and a vertical portion extending from the horizontal portion to an upper portion or a lower portion overlapping the data wiring; And a pixel electrode and a common electrode connected to the organic layer pattern interposed between the vertical line and the data line, the thin film transistor and the common wiring, respectively, and configured to correspond to the pixel area.

In this case, the gate wiring and the common wiring are made of the same layer and the same material, and the organic layer pattern is made of one selected from the group of organic insulating materials including photoacryl and benzocyclobutene.

The common wiring and the common electrode are connected to each other through a common contact hole exposing a portion of the common wiring. The common electrode may include an extension part contacting the common contact hole and a plurality of vertical parts vertically branched from the extension part to the pixel area.

The pixel electrode may include an extension part in contact with the thin film transistor, and a plurality of vertical parts vertically branched from the extension part to the pixel area, wherein the pixel electrode vertical part and the common electrode vertical part are mutually different in the pixel area. Alternately spaced in parallel.

A storage capacitor further includes a pixel electrode extension part as a first electrode, and a common wiring horizontal part overlapping the first electrode as a second electrode.

In this case, the thin film transistor includes a semiconductor layer including the gate electrode and the gate insulating layer, an active layer made of pure amorphous silicon, and an ohmic contact layer made of amorphous silicon including impurities, and source and drain electrodes spaced apart from both sides. do.

And further comprising first and second semiconductor patterns respectively extending from the active and ohmic contact layers below the data lines, wherein the common electrode vertical portion is configured to allow light from a backlight unit to be incident on the first and second semiconductor patterns. It functions to block.

The common electrode and the pixel electrode are made of one selected from a group of transparent conductive metals such as indium tin oxide or indium zinc oxide. In this case, a gate pad and a gate pad electrode in contact with the gate pad are further configured at one end of the gate wiring, and a data pad and a data pad electrode in contact with the data pad are further included at one end of the data wiring. do.

According to an aspect of the present invention, there is provided a method of fabricating an array substrate for a transverse electric field type liquid crystal display device, the method comprising: preparing a substrate defined by a switching region, a common region, a gate region, and a data region; Forming a gate wiring and a gate electrode, a common wiring including a horizontal portion spaced in parallel with the gate wiring, a vertical portion corresponding to the data region vertically crossing the horizontal portion, and the common wiring vertical portion A first mask process step of forming an organic film pattern on the substrate, a gate insulating film on the substrate on which the gate electrode and the wiring and the common wiring are formed, and a data wiring on the upper portion overlapping the common wiring vertical portion on the gate insulating film And forming a thin film transistor at an intersection point of the gate line and the data line. Norilsk process step;

Forming a passivation layer including a contact hole exposing a portion of the thin film transistor on the thin film transistor and the data line; and forming a pixel electrode and a common electrode on the passivation layer including the contact hole. 4 mask process steps.

In this case, the organic layer pattern is formed of one selected from the group of organic insulating materials including photoacryl and benzocyclobutene. The common line and the common electrode are connected to each other through a common contact hole exposing a portion of the common line.

The common electrode includes an extension part in contact with the common contact hole, and a plurality of vertical parts vertically branched from the extension part to the pixel area.

The pixel electrode includes an extension part in contact with the thin film transistor and a plurality of vertical parts vertically branched from the extension part to the pixel area, wherein the pixel electrode vertical part and the common electrode vertical part are parallel to each other in the pixel area. Alternately spaced.

A storage capacitor further includes a pixel electrode extension part as a first electrode, and a common wiring horizontal part overlapping the first electrode as a second electrode.

The thin film transistor includes the gate electrode, an active layer made of pure amorphous silicon, an ohmic contact layer made of amorphous silicon including impurities, and source and drain electrodes spaced apart from both sides.

The semiconductor device may further include first and second semiconductor patterns extending from the active and ohmic contact layers, respectively. The common electrode vertical part may block light incident to the first and second semiconductor patterns.

The common electrode and the pixel electrode are formed of one selected from a group of transparent conductive metals such as indium tin oxide or indium zinc oxide.

Further, a gate pad and a gate pad electrode in contact with the gate pad are further formed at one end of the gate wiring, and a data pad and a data pad electrode in contact with the data pad are further formed at one end of the data wiring. do.

The first mask process may include forming a gate metal layer and a photosensitive layer on a substrate, arranging a mask including a transmissive part, a transflective part, and a blocking part on the gate metal layer and the photosensitive layer, and separating the mask from the mask. The first and third photosensitive patterns having the thickness of the photosensitive layer lowered by about half in correspondence to the switching area and the common area, and the thickness change of the photosensitive layer corresponding to the data area. Forming a fourth photosensitive pattern that is absent;

In the pattern process using the first to fourth photosensitive patterns as a mask, forming a common wiring including a gate wiring and a gate electrode, a horizontal portion and a vertical portion, and ashing the first to fourth photosensitive patterns The method may further include forming an organic layer pattern on the common wiring vertical part corresponding to the data area.

In the present invention, first, the aperture ratio may be maximized by designing a common wiring vertical part corresponding to the pixel areas on both sides with the data wiring as a lower portion overlapping with the data wiring.

Second, through interposing an organic film pattern between the data wiring and the common wiring vertical portion, it is possible to prevent a poor image quality due to parasitic capacitance.

Third, the common wiring vertical portion may serve to block light from the backlight unit incident on the first semiconductor pattern under the data wiring.

Fourth, the production yield can be improved by reducing the number of mask processes.

Fifth, the organic film pattern can be manufactured only by adding the ashing process, thereby simplifying the production process.

--- Example ---

The present invention is characterized in that an organic film pattern having a small dielectric constant is interposed between the data line and the common line vertical part while the common wiring vertical part is designed to overlap the lower portion of the data line. In particular, it is characterized in that the array substrate for a transverse electric field type liquid crystal display device having a high opening ratio is produced by a four mask process.

Hereinafter, a transverse electric field type liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.

4 is a plan view illustrating unit pixels of an array substrate for a transverse electric field type liquid crystal display device according to an exemplary embodiment of the present invention.

As shown in the drawing, a gator wiring 220 having a gate pad 252 at one end on a substrate 200 is configured in a horizontal direction, and a data pad at one end in a direction perpendicular to the gate wiring 220. The data line 230 having 262 is configured in the longitudinal direction.

In addition, the common wiring 250 is spaced apart from the gate wiring 220 in parallel. The common wire 250 includes a plurality of horizontal parts 250a spaced apart from each other and parallel to the gate wire 220, and a plurality of vertical parts extending downward from the plurality of horizontal parts 250a and overlapping the data wires 230. Section 250b.

In this case, the region defined by the vertical intersection of the gate line 220 and the data line 230 is referred to as a pixel area P. A thin film transistor T is formed at an intersection point of the gate line 220 and the data line 230.

The thin film transistor T may include a gate electrode 225 extending from the gate wiring 220, a semiconductor layer (not shown) positioned on the gate electrode 225, and extending from the data wiring 230. A source electrode 232 in contact with the layer, and a drain electrode 234 spaced apart from the source electrode 232.

The semiconductor layer includes an active layer 240 made of pure amorphous silicon (a-Si: H) and an ohmic contact layer (not shown) made of amorphous silicon (n + a-Si: H) including impurities. In this case, in order to reduce the number of mask processes, the semiconductor layer, the source and drain electrodes 232 and 234, and the data lines 230 are patterned in one mask process, and the lower portion of the data lines 230 and the data pads 262 are used. The first semiconductor pattern 248 and the second semiconductor pattern (not shown) extend.

The first semiconductor pattern 248 and the second semiconductor pattern (not shown) respectively extend from the active layer 240 and the ohmic contact layer (not shown), and in particular, the first semiconductor pattern extending from the active layer 240. A portion 288 of the lower portion of the data line 230 is exposed to the outside.

In this case, an organic layer pattern is formed between the data line 230 including the first semiconductor pattern 248 and the second semiconductor pattern and the common wire vertical portion 250b disposed below the data line 230. The organic layer pattern may include one selected from the group of organic insulating materials including photoacryl and benzocyclobutene having a low dielectric constant.

In this case, the organic layer pattern may have a low dielectric constant, which may significantly reduce the parasitic capacitance between the data line 230 and the common line vertical part 250b. As a result, even when the data line 230 and the common line vertical part 250b are designed to overlap, the parasitic capacitance is less affected.

In addition, the common wiring vertical portion 250b may fundamentally block light from a backlight unit (not shown) disposed on the rear surface of the array substrate 200 from entering the first semiconductor pattern 248.

On the other hand, the pixel electrode 270 in contact with the drain electrode 234 through the drain contact hole CH4 exposing the drain electrode 234 is configured to correspond to the pixel region P. The pixel electrode 270 is an extension part 270a in contact with the drain electrode 234 and a plurality of vertical branches vertically branched into the pixel region P in parallel with the data line 230 at the extension part 270a. Section 270b.

In this case, the storage capacitor Cst includes the pixel electrode extension 270a as the first electrode and the common wiring horizontal part 250a overlapping the first electrode as the second electrode.

In addition, the pixel region P includes a plurality of common electrodes 260 that are alternately spaced apart from each other in parallel with the pixel electrode 270. The common electrode 260 is in contact with the common wire 250 through the common contact hole CH5 exposing a part of the common wire 250, and the pixel region (eg, in the extension part 260a). And a plurality of vertical portions 260b vertically branched in the direction P).

The above-described configuration has an advantage of significantly improving the aperture ratio by interposing an organic film pattern between the common wiring vertical portion and the data wiring designed to overlap.

Hereinafter, a method of manufacturing an array substrate for a transverse electric field type liquid crystal display device according to the present invention will be described with reference to the accompanying drawings.

5A to 5J, 6A to 6J, 7A to 7J, and 8A to 8J are cut along the lines V-V, VI-VI, V-V, and V-V of FIG. It is a process cross section shown by.

5A to 5D, 6A to 6D, 7A to 7D, and 8A to 8D are process cross-sectional views illustrating a first mask process step.

5A to 8A, defining the switching region S, the pixel region P, the common region C, the gate region G, and the data region D on the substrate 200. Proceed. Copper (Cu), molybdenum (Mo), molybdenum alloy (MoTi), aluminum (Al), aluminum alloy (AlNd) on the substrate 200 on which the plurality of regions S, P, C, G, and D are defined And a gate metal layer 220a stacked with one or more alloys selected from a conductive metal group including chromium (Cr) and the like, and applying a photoresist on the gate metal layer 220a to form a first photosensitive layer 280. ).

In general, the first photosensitive layer 280 is formed of one selected from the group of organic insulating materials including photo acryl and benzocyclobutene, which are sensitive to photoreaction and have a low dielectric constant.

Next, a process of aligning the halftone mask HTM including the transmissive portion A, the transflective portion B, and the blocking portion C on the substrate 200 on which the first photosensitive layer 280 is formed is performed. .

The halftone mask HTM has a function of forming a translucent film on the transflective portion B so that the first photosensitive layer 280 may be incompletely exposed by lowering light intensity or lowering light transmission amount. In this case, in addition to the halftone mask HTM, a slit mask may be used to control the amount of light transmitted by placing a slit shape on the transflective portion B.

In addition, the blocking unit C serves to completely block light, and the transmitting unit A transmits light so that the photosensitive layer 280 exposed to light is completely exposed.

In this case, the transflective portion B is positioned to correspond to the switching region S, the gate region G, and the common region C, and the cutoff portion C is positioned to correspond to the data region D. FIG. In addition, the entire region except for the permeable portion (A) is located.

Next, as shown in FIGS. 5B to 8B, the process of exposing and developing the upper half spaced from the above-described halftone mask (HTM of FIGS. 5A to 8A) is common to the switching region S. The first to fourth photosensitive patterns 282, 283, 284, and 285 having a thickness lowered by about half corresponding to the region C and the gate region G are formed, respectively, and have a thickness change corresponding to the data region D. FIG. The fifth photosensitive pattern 286 is formed. The first photosensitive layer (280 in FIGS. 5A to 8A) corresponding to the entire region except for the first photosensitive layer 286 is removed to expose the lower gate metal layer 220a.

Next, as shown in FIGS. 5C to 8C, the first to fifth photosensitive patterns 282, 283, 284, 285, and 286 are used as masks, and the exposed gate metal layer (FIGS. 5B to 8B) may be used. 220a is patterned to form a gate wiring (220 in FIG. 4) having a gate pad 252 at one end corresponding to the gate region G on the substrate 200, and the gate wiring (220 in FIG. 4). ) Is formed to correspond to the switching region (S).

At the same time, the common wiring 250 of FIG. 4 is formed corresponding to the common region C and the data region D. The common wiring 250 of FIG. 4 is formed of the gate wiring 220 of FIG. 4. A plurality of horizontal parts 250a spaced apart in parallel and a plurality of vertical parts 250b vertically branched from the horizontal parts 250a are included.

Next, as shown in FIGS. 5D to 8D, ashing the remaining first to fifth photosensitive patterns (282 to 286 in FIGS. 5C to 7C) is performed to be common to the switching area S. FIG. All of the first to fourth photosensitive patterns (282 to 285 in FIGS. 5C to 7C) corresponding to the region C and the gate region G are removed, and the fifth photosensitive pattern (FIG. 6C) is disposed in the data region D. 286, an organic film pattern 288 having a thickness lowered by about half is formed.

Therefore, in the present invention, by applying the halftone mask or the slit mask, the organic film pattern 288 may be formed without a large difference from the general mask process by only adding the ashing process.

Next, an inorganic material including silicon oxide and silicon nitride on the substrate 200 on which the gate electrode 225, the gate wiring (220 of FIG. 4), the gate pad 252, and the common wiring (250 of FIG. 4) are formed. The gate insulating layer 245 is formed of one selected from the group of insulating materials.

5E to 5H, 6E to 6H, 7E to 7H, and 8E to 8H are cross-sectional views illustrating a second mask process step.

5E to 8E, on the substrate 200 on which the gate insulating layer 245 is formed, a pure amorphous silicon layer 240a made of pure amorphous silicon (a-Si: H) and an amorphous including impurities. An impurity amorphous silicon layer 241a made of silicon (n + a-Si: H) is sequentially stacked.

Next, the source and drain metal layers 275 are formed by depositing one or more of the above-described conductive metal groups on the substrate 200 on which the pure and impurity amorphous silicon layers 240a and 241a are formed. Subsequently, a photoresist is applied on the substrate 200 on which the source and drain metal layers 275 are formed to form a second photosensitive layer 290, and the above-mentioned portion is spaced apart from the second photosensitive layer 290. Aligning the halftone mask HTM is performed.

In this case, the transflective portion B is positioned between the blocking portions C on both sides of the switching region S, and the blocking portion C is positioned in the data region D. The transmissive portion A is positioned.

As shown in FIGS. 5F to 8F, when the exposure and development processes are performed on the upper part spaced apart from the above-described halftone mask (HTM of FIGS. 5E to 8E), both blocking portions of the switching region S (FIG. In C) of 5e, there is no change in thickness, and in the transflective portion (B in FIG. 5E) between the two blocking portions (C in FIG. 5E), a sixth photosensitive pattern 292 whose thickness is about half lowered is formed.

At the same time, the seventh and eighth photosensitive patterns 293 and 294 having no thickness change corresponding to the data area D are formed, respectively, and the second photosensitive layers of all regions except for the thicknesses 290 of FIGS. 5E to 8E. ) Are removed to expose the underlying source and drain metal layers (275 of FIGS. 5E-8E).

Next, the sixth to eighth photosensitive patterns 292, 293, and 294 are used as masks, and the exposed source and drain metal layers (275 of FIGS. 5E to 8E) are patterned as a second mask, and the switching is performed. The active layer 240, the ohmic contact layer 241, the source and drain patterns 272 are formed in correspondence with the region S, and the first and second semiconductor patterns 240b, corresponding to the data region D, are formed. Data lines 230 and data pads 262 including 241b are formed, respectively.

In this case, the first and second semiconductor patterns 240b and 241b extend from the active and ohmic contact layers 240 and 241, respectively, and the data line 230 and the data pad 262 may be used to reduce the number of processes of the mask. It is composed at the bottom of the.

In this case, the active layer 240 and the ohmic contact layer 241 may be referred to as a semiconductor layer 242.

5G to 8G, when the ashing of the sixth to eighth photosensitive patterns 292, 293, and 294 is performed, the thicknesses of the sixth to eighth photosensitive patterns 292 to 294 are half. Lowers to a degree. In particular, all of the sixth photosensitive patterns (292 of FIG. 5F) corresponding to the transflective portion (B of FIG. 5E) of the switching region S are removed to expose the source and drain patterns 272 below.

In this case, a portion of the sixth to eighth photosensitive patterns 292, 293, and 294 covering the both ends of the data line 230, the data pad 262, and the source and drain patterns 272 may be removed together. The data line 230, the data pad 262, and the source and drain patterns 272 corresponding to the portions are exposed.

Next, as shown in FIGS. 5H to 8H, the sixth to eighth photosensitive patterns (292 to 294 of FIGS. 5G to 8G) are used as masks, and the exposed source and drain patterns (see FIG. 5G). 272 is patterned by a wet etching process to form source and drain electrodes 232 and 234 spaced apart from both sides.

Next, the ohmic contact layer 241 exposed between the source and drain electrodes 232 and 234 spaced apart from each other is formed on both sides, and the active layer corresponding to the ohmic contact layer 241 separated from both sides ( 240 is overetched to utilize this portion as a channel (ch).

In the process of forming the channel and the source and drain electrodes 232 and 234, the exposed data line 230 and the data pad 262 and the lower portion of the data line and the pad 230 and 262 are formed. The second semiconductor pattern 241b is removed together to expose the data line 230 and a part of the first semiconductor pattern 240b under the data pad 262 to the outside.

In this case, the gate electrode 225, the gate insulating layer 245, the semiconductor layer 242, and the source and drain electrodes 232 and 234 form a thin film transistor T serving as a switching function.

Next, the sixth to eighth photosensitive patterns (292 to 294 of FIGS. 5G to 8G) are removed through a strip process.

The second mask process step is finally completed through the above process steps.

5I to 8I are process cross-sectional views illustrating a third mask process step.

5I to 8I, an inorganic insulating material group including silicon oxide and silicon nitride on the substrate 200 on which the thin film transistor T, the data line 230, the data pad 262, etc. are formed. The passivation layer 255 is formed by one selected from among the above.

Next, a drain contact hole exposing the drain electrode 234 and the data pad 262 by patterning the passivation layer 255 corresponding to a part of the drain electrode 234 and the data pad 262 with a third mask. CH4 and data pad contact holes CH7 are formed, respectively.

At the same time, the common contact hole CH5 and the gate pad contact hole are patterned by sequentially patterning the passivation layer 255 corresponding to a part of the common wiring horizontal part 250a and the gate pad 252 and the gate insulating layer 245 thereunder. Each of (CH6) is formed.

5J to 8J are process cross-sectional views illustrating a fourth mask process step.

As illustrated in FIGS. 5J to 8J, the substrate 200 includes the drain contact hole CH4, the common contact hole CH5, the gate pad contact hole CH6, and the data pad contact hole CH7. A transparent metal layer (not shown) is formed of one selected from the group of conductive metals including indium tin oxide (ITO) and indium zinc oxide (IZO) and patterned with a fourth mask to form the drain electrode 234. The pixel electrode 270 in contact (270 in FIG. 4), the common electrode (260 in FIG. 4) in contact with the common wiring horizontal part 250a, the gate pad electrode 254 in contact with the gate pad 252, and the data pad Data pad electrodes 264 in contact with 262 are formed, respectively.

In this case, the pixel electrode 270 of FIG. 4 includes an extension part 270a in contact with the drain electrode 234, and a plurality of vertical parts vertically branched so as to be parallel to the data line 230 in the extension part 270a. 270b). The common electrode 260 of FIG. 4 has an extension 260a in contact with the common wiring horizontal part 250a, and is parallel to the pixel electrode vertical part 270b and the pixel area P in the extension part 260a. A plurality of vertical parts 260b alternately spaced apart.

In this case, a storage capacitor Cst is formed using the common wiring horizontal part 250a as the first electrode and the pixel electrode extension part 270a overlapping the common wiring horizontal part 250a as the second electrode.

Accordingly, in the present invention, since the organic film pattern 288 having a small dielectric constant is interposed between the data line 230 and the common wiring vertical portion 250b positioned below the data line 230, the data line 230 is interposed therebetween. It can be minimized from the influence of the parasitic capacitance between the 230 and the common wiring vertical portion 250b, and thus the opening ratio can be maximized.

As described above, the array substrate for the high-aperture transverse electric field type liquid crystal display device according to the present invention may be manufactured in four mask process steps through the above process.

FIG. 9 is a cross-sectional view taken along the line VII-VII of FIG. 4 and illustrates a state where the array substrate and the color filter substrate are opposed to each other. In this case, the same name as that of FIG. 4 is represented by adding 100 to the drawing number.

As illustrated, the color filter substrate 305 and the array substrate 307, which are divided into the display area AA and the non-display area NAA, face each other with a constant cell gap, and the substrates 305 and 307 are bonded to each other. The liquid crystal layer 309 is interposed between them. The color filter, the array substrate 305 and 307, and the liquid crystal layer 309 are referred to as a liquid crystal panel 310.

In this case, a backlight unit 315 serving as a light source is disposed on the rear surface of the array substrate 307.

On the lower surface of the transparent substrate 301 of the color filter substrate 305 is a black matrix 312 for shielding the light incident to the non-display area (NAA), and the pattern is sequentially patterned around the black matrix 312 The color filter layer 314 including the red, green, and blue sub color filters 314a, 314b (not shown), and the upper alignment layer 316 formed under the color filter layer 314 are sequentially disposed.

On the other hand, a common wiring vertical portion 350b is positioned on the transparent substrate 302 upper surface of the array substrate 307 corresponding to the data region D, and an organic film having a small dielectric constant is disposed on the common wiring vertical portion 350b. Pattern 388 is located. In addition, the gate insulating layer 345 is formed on the common wiring vertical part 350b and the organic layer pattern 388 as one selected from the group of inorganic insulating materials.

On the gate insulating layer 345, a data line 330 including first and second semiconductor patterns 340b and 341b is formed corresponding to the data region D, and a silicon oxide layer is formed on the data line 330. The protective film 355 is formed of one selected from the group of inorganic insulating materials including SiO ₂ ) and silicon nitride (SiNx).

In addition, a plurality of common electrode vertical parts 360b are formed on both sides of the passivation layer 355 and spaced apart from the data line 330, and a lower alignment layer 318 is positioned on the common electrode vertical parts 360b of both sides. .

At this time, in the present invention, unlike the prior art, the common wiring vertical portion 350b, which is divided into the pixel areas P on both sides of the data line 330, is integrated into one lower portion overlapping the data line 330. The organic layer pattern 388 may be interposed between the common wire vertical part 350b and the data wire 330 to be free from the influence of parasitic capacitance. As a result, there is an advantage that the aperture ratio can be significantly improved.

In addition, the common wiring vertical part 350b serves as an auxiliary role to fundamentally block light from the backlight unit 315 positioned on the rear surface of the array substrate 307 from entering the first semiconductor pattern 340b. .

Therefore, in the present invention, the high opening ratio can be realized by designing the common wiring vertical portion and the data wiring to overlap each other.

However, it will be apparent to those skilled in the art that the present invention is not limited to the above embodiments and various modifications and changes can be made without departing from the spirit and spirit of the present invention.

1 is a plan view illustrating a unit pixel of an array substrate for a transverse electric field type liquid crystal display device according to an exemplary embodiment.

2 is a plan view illustrating a unit pixel of an array substrate for a transverse electric field type liquid crystal display device according to another exemplary embodiment of the prior art;

3 is a cross-sectional view taken along the line II-II of FIG.

4 is a plan view showing unit pixels of an array substrate for a transverse electric field type liquid crystal display device according to the present invention;

5A to 5J are cross-sectional views illustrating a process sequence by cutting along the line VV of FIG. 4.

6A to 6J are cross-sectional views taken along the VI-VI line of FIG. 4 and according to the process sequence.

7A to 7J are cross-sectional views illustrating a process sequence by cutting along the line VII-VII of FIG. 4.

8A to 8J are cross-sectional views illustrating a process sequence by cutting along the line VII-VII of FIG. 4.

9 is a cross-sectional view taken along the line VII-VII of FIG. 4.

* Explanation of symbols for the main parts of the drawings *

200: substrate 230: data wiring

240b: first semiconductor pattern 241b: second semiconductor pattern

245: gate insulating film 250a: common wiring horizontal portion

250b: common wiring vertical part 255: protective film

260a: common electrode extension 260b: common electrode vertical

270b: vertical portion of pixel electrode 288: organic film pattern

CH5: common contact hole

Claims (24)

A substrate; A gate wiring formed in one direction on the substrate; A data line defining a pixel area vertically crossing the gate line; A thin film transistor configured at an intersection point of the gate line and the data line; A common wiring including a horizontal portion spaced apart in parallel with the gate wiring, and a vertical portion extending from the horizontal portion to an upper portion or a lower portion overlapping with the data wiring; An organic film pattern interposed between the common wiring vertical portion and the data wiring; A pixel electrode and a common electrode connected to the thin film transistor and the common wiring, respectively, and configured to correspond to the pixel area; Array substrate for a transverse electric field type liquid crystal display device comprising a. The method of claim 1, And the gate wiring and the common wiring are formed of the same material as the same layer. The method of claim 1, And the organic layer pattern is selected from a group of organic insulating materials including photoacryl and benzocyclobutene. The method of claim 1, And the common wiring and the common electrode are connected to each other through a common contact hole exposing a part of the common wiring. The method of claim 1, And the common electrode includes an extension part in contact with the common contact hole, and a plurality of vertical parts vertically branched from the extension part to the pixel area. The method according to claim 1 and 5, The pixel electrode includes an extension part in contact with the thin film transistor, and a plurality of vertical parts vertically branched from the extension part to the pixel area, wherein the pixel electrode vertical part and the common electrode vertical part are parallel to each other in the pixel area. An array substrate for a transverse electric field type liquid crystal display device, characterized in that alternately spaced. The method of claim 1, And a storage capacitor including the pixel electrode extension as a first electrode, and the common wiring horizontal portion superimposed on the first electrode as a second electrode. The method of claim 1, The thin film transistor includes a semiconductor layer including the gate electrode and the gate insulating layer, an active layer made of pure amorphous silicon, and an ohmic contact layer made of amorphous silicon including impurities, and source and drain electrodes spaced apart from both sides. An array substrate for a transverse electric field type liquid crystal display device. The method of claim 8, And a first and a second semiconductor pattern extending from the active and ohmic contact layers to the lower portion of the data line, respectively. The method according to claim 1 and 9, And the common electrode vertical portion prevents light from the backlight unit from being incident on the first and second semiconductor patterns. The method of claim 1, And the common electrode and the pixel electrode are selected from a group of transparent conductive metals such as indium tin oxide or indium zinc oxide. The method of claim 1, A gate pad and a gate pad electrode in contact with the gate pad are further configured at one end of the gate wiring, and one end of the data wiring further includes a data pad and a data pad electrode in contact with the data pad. An array substrate for a transverse electric field type liquid crystal display device. Preparing a substrate defined by a switching region, a common region, a gate region, and a data region; Forming a gate wiring and a gate electrode in one direction on the substrate; A common wiring including a horizontal portion spaced apart in parallel with the gate wiring, a vertical portion corresponding to the data region vertically crossing the horizontal portion, and a first mask process of forming an organic layer pattern on the common wiring vertical portion Steps; Forming a gate insulating film on the substrate on which the gate electrode and the wiring and the common wiring are formed, and a data wiring on an upper portion of the gate insulating film, the upper portion overlapping the common wiring vertical portion; Forming a thin film transistor at an intersection point of the gate line and the data line; A third mask process step of forming a passivation layer including a contact hole exposing a portion of the thin film transistor on the thin film transistor and the data line; A fourth mask process step of forming a pixel electrode and a common electrode on the passivation layer including the contact hole; Method of manufacturing an array substrate for a transverse electric field type liquid crystal display device comprising a. The method of claim 13, And the organic layer pattern is formed of one selected from the group of organic insulating materials including photoacryl and benzocyclobutene. The method of claim 13, And the common wiring and the common electrode are connected to each other through a common contact hole exposing a part of the common wiring. The method of claim 13, The common electrode may include an extension part in contact with the common contact hole, and a plurality of vertical parts vertically branched from the extension part to the pixel area. The method according to claim 13 and 16, The pixel electrode includes an extension part in contact with the thin film transistor and a plurality of vertical parts vertically branched from the extension part to the pixel area, wherein the pixel electrode vertical part and the common electrode vertical part are parallel to each other in the pixel area. A method of manufacturing an array substrate for a transverse electric field type liquid crystal display device, characterized in that formed alternately spaced apart. The method of claim 17, And a storage capacitor including the pixel electrode extension as a first electrode and the common wiring horizontal portion superimposed on the first electrode as a second electrode. . The method of claim 13, The thin film transistor includes a gate electrode, an active layer made of pure amorphous silicon, an ohmic contact layer made of amorphous silicon containing impurities, and a source and drain electrode spaced apart from both sides. Method of manufacturing an array substrate for an apparatus. The method of claim 19, And first and second semiconductor patterns extending from the active and ohmic contact layers, respectively, below the data line. The method of claim 13 and 20, And the common electrode vertical portion blocks light incident on the first and second semiconductor patterns. The method of claim 13, And said common electrode and said pixel electrode are formed of one selected from a group of transparent conductive metals such as indium tin oxide or indium zinc oxide. The method of claim 13, A gate pad and a gate pad electrode in contact with the gate pad are further formed at one end of the gate wiring, and a data pad and a data pad electrode in contact with the data pad are further formed at one end of the data wiring. A method of manufacturing an array substrate for a transverse electric field type liquid crystal display device. The method of claim 13, The first mask process step Forming a gate metal layer and a photosensitive layer on the substrate; Arranging a mask including a transmissive part, a transflective part, and a blocking part on the gate metal layer and the photosensitive layer; Exposure and development processes are performed on the upper part spaced apart from the mask, and the first to third photosensitive patterns having the thickness of the photosensitive layer lowered by about half in correspondence with the switching area and the common area, and the photosensitive corresponding to the data area. Forming a fourth photosensitive pattern having no change in thickness of the layer; Forming a common wiring including a gate wiring, a gate electrode, a horizontal portion, and a vertical portion by a pattern process using the first to fourth photosensitive patterns as a mask; Ashing the first to fourth photosensitive patterns to form an organic layer pattern on the common wiring vertical part corresponding to the data region. Method of manufacturing an array substrate for a transverse electric field type liquid crystal display device comprising a.

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