KR20090031128A - Semiconductor memory device and refresh method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a refresh method thereof, and discloses a technique for improving data retention characteristics by performing a refresh operation in a phase change memory device having a nonvolatile characteristic. The present invention utilizes a cell array including read / write of data including a phase change resistance cell, a register for storing information of the cell array, and information stored in a register to improve retention characteristics of data stored in the cell array. Refresh control means for performing a refresh operation at a specific refresh cycle.

Description

Semiconductor memory device and method for refreshing {{Semiconductor memory device and method for refresh}

1 is a view showing a cell array of a DRAM according to the prior art.

2A and 2B are diagrams for explaining a conventional phase change resistance element.

3A and 3B are diagrams for explaining the principle of a conventional phase change resistance element.

4 is a diagram for explaining a write operation of a conventional phase change resistance cell.

5 illustrates a memory cell array of a semiconductor memory device according to the present invention.

6A and 6B are diagrams for describing a data write operation of the semiconductor memory device according to the exemplary embodiment of FIG. 5.

FIG. 7 is a diagram for describing a data read operation of the semiconductor memory device according to the exemplary embodiment of FIG. 5. FIG.

8A and 8B are diagrams for describing a data refresh operation of the semiconductor memory device according to the exemplary embodiment of FIG. 5.

9 is another embodiment of a cell array of a semiconductor memory device according to the present invention;

10A and 10B are diagrams for describing a data write operation of the semiconductor memory device according to the exemplary embodiment of FIG. 9.

FIG. 11 is a diagram for describing a data read operation of the semiconductor memory device according to the exemplary embodiment of FIG. 9. FIG.

12A and 12B are diagrams for describing a data refresh operation of the semiconductor memory device according to the exemplary embodiment of FIG. 9.

Fig. 13 shows another embodiment of a cell array of a semiconductor memory device according to the present invention.

14A and 14B are circuit diagrams of the semiconductor memory device according to the exemplary embodiment of FIG. 13 and waveform diagrams of operations in a read mode.

15A and 15B are circuit diagrams of the semiconductor memory device according to the embodiment of FIG. 13 and operational waveform diagrams in the write mode.

FIG. 16 is a diagram illustrating an entire cell array of the semiconductor memory device according to the exemplary embodiment of FIG. 13. FIG.

17 is an overall configuration diagram of a semiconductor memory device according to the present invention.

18 is a timing diagram of a read operation of the semiconductor memory device according to the present invention.

19 is a timing diagram of a write operation of the semiconductor memory device according to the present invention.

20 is a detailed configuration diagram of the row address register of FIG. 17;

21 is an operation timing diagram relating to a refresh method of a semiconductor memory device according to the present invention.

22 and 23 are flowcharts illustrating a refresh method of a semiconductor memory device according to the present invention.

24 is a diagram for explaining a refresh method of a semiconductor memory device according to the present invention;

25 is a view for explaining a timer control operation in a refresh method of a semiconductor memory device according to the present invention;

26 is a graph for explaining data retention characteristics of a semiconductor memory device according to the present invention;

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a refresh method thereof, and is a technique for improving data retention by performing a refresh operation on a phase change memory device having a nonvolatile characteristic.

With the rapid spread of computers in recent years, the demand for semiconductor devices has also increased greatly. Such semiconductor devices require high speed operation while having high storage capacity in terms of their functions. To this end, semiconductor devices are being manufactured with manufacturing techniques for improving integration, response speed, and reliability.

As such a semiconductor element, a DRAM (DRAM) element having a high capacity and free input and output of information is freely used. The DRAM device is composed of a memory cell area storing information data in the form of charge and a peripheral area for input and output of the information data. In addition, the DRAM device includes one access transistor and one accumulation capacitor.

Such DRAM is a volatile memory, and power supply must be continued to store data. If power is lost momentarily, data held in RAM can be lost. This is because DRAM memory cells are designed around small chargers that hold the charged power. These chargers are like very small rechargeable batteries that don't continue to be recharged and lose precharged power.

A refresh operation refers to a process of recharging a memory cell in such a memory chip, and a row of memory cells may be charged in one refresh cycle. This refresh operation is performed by the memory control of the system, but some chips are designed to perform a self refresh operation.

For example, a DRAM chip has a self-refreshing circuit, and thus a technology for autonomous refreshing without intervention of a central processing unit (CPU) or an external refresh circuit has been disclosed. This self-refreshing method significantly reduces power consumption and is often used in portable computers.

1 is a view showing a cell array of a DRAM according to the prior art.

In the DRAM, a plurality of bit lines BL are arranged in a row direction, and a plurality of word lines WL are arranged in a column direction. A plurality of unit cells are formed in regions where the plurality of word lines WL and the plurality of bit lines BL cross each other.

Each unit cell has one switching element T for switching bit line BL and capacitor C by switching operation according to the state of word line WL, and one capacitor C connected between one end of switching element T and plate line PL. Is done. Here, the switching element mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

A sense amplifier S / A is connected to each bit line BL to sense and amplify cell data applied from the bit line BL. In addition, the sense amplifier S / A is shared by two bit lines BL.

The DRAM stores charge in the capacitor C and senses a change in the voltage applied to the sense amplifier S / A through the bit line BL to distinguish data “1” from data “0”. Since the DRAM needs to read minute changes in the voltage across the bitline BL, capacitor C requires about fF of capacitance.

However, since the conventional DRAM is volatile and has a short refresh period, the refresh operation is frequently performed. That is, in the case of DRAM, the charge stored in the capacitor C leaks with time. Accordingly, the read and write refresh operation is performed periodically at a predetermined period (for example, 64 msec). Therefore, power consumption due to the refresh operation is large and operation performance is lowered.

On the other hand, nonvolatile memories such as magnetic memory and phase change memory (PCM) have data processing speeds of about volatile random access memory (RAM), and preserve data even when the power is turned off. Has the property of being.

2A and 2B are diagrams for explaining a conventional phase change resistor (PCR) element 4.

When the phase change resistance element 4 applies a voltage and a current by inserting a phase change material (PCM) 2 between the top electrode 1 and the bottom electrode 3, a phase is applied. The high temperature is induced in the change layer 2 to change the state of electrical conduction according to the change in resistance. Here, AglnSbTe is mainly used as the material of the phase change layer 2. In addition, the phase change layer 2 uses a chalcogenide (chalcogenide) mainly composed of chalcogen elements (S, Se, Te), specifically, a germanium antimony tellurium alloy material consisting of Ge-Sb-Te (Ge2Sb2Te5). ).

3A and 3B are diagrams for explaining the principle of a conventional phase change resistance element.

As shown in FIG. 3A, when a low current of less than or equal to a threshold flows through the phase change resistance element 4, the phase change layer 2 is at a temperature suitable for crystallization. As a result, the phase change layer 2 is in a crystalline phase to become a material having a low resistance state.

On the other hand, as shown in FIG. 3B, when a high current of more than a threshold flows through the phase change resistance element 4, the temperature of the phase change layer 2 becomes higher than the melting point. As a result, the phase change layer 2 is in an amorphous state and becomes a material of a high resistance state.

As described above, the phase change resistive element 4 can non-volatilely store data corresponding to the states of the two resistors. That is, when the phase change resistance element 4 is in the low resistance state, the data "1" is referred to as data "0" in the high resistance state, and the logic state of the two data can be stored.

4 is a view for explaining the write operation of a conventional phase change resistance cell.

When a current flows between the top electrode 1 and the bottom electrode 3 of the phase change resistance element 4 for a predetermined time, high heat is generated. Thereby, the state of the phase change layer 2 changes into a crystalline phase and an amorphous phase by the temperature state applied to the top electrode 1 and the bottom electrode 3.

At this time, when a low current flows for a predetermined time, a crystal phase is formed by a low temperature heating state, and the phase change resistance element 4, which is a low resistance element, is set. On the contrary, when a high current flows for a predetermined time, an amorphous phase is formed by a high temperature heating state, and the phase change resistance element 4, which is a high resistance element, is reset. Thus, these two phase differences are represented by electrical resistance change.

Accordingly, a low voltage is applied to the phase change resistance element 4 for a long time to write the set state in the write operation mode. On the other hand, in the write operation mode, a high voltage is applied to the phase change resistance element 4 for a short time to write the reset state.

By the way, such a conventional phase change memory device has a non-volatile characteristic, but the deterioration condition of the cell data occurs over time in an actual situation, and thus the data retention life is limited.

As a result, the current of the bit line BL corresponding to the cell data "1" and "0" decreases over time. Therefore, the data retention characteristics are degraded, making it difficult to permanently maintain the best nonvolatile cell storage characteristics for a long time.

The present invention has the following object.

First, an object of the present invention is to reduce the size of a cell by applying a phase change resistor (PCR) element to a DRAM to improve the structure of the cell.

Second, an object of the present invention is to implement a semiconductor memory device having one switching element and one phase change resistance element and perform a refresh operation to improve data retention characteristics.

Third, an object of the present invention is to improve data retention characteristics by restoring deteriorated cell data by refreshing data at a specific cycle while preserving data when power is turned off in a phase change memory device. There is this.

Fourth, an object of the present invention is to maintain the refresh information even when the power supply is turned off by performing the refresh operation according to the parameter information stored in the nonvolatile register when the power supply is turned off.

Fifth, an object of the present invention is to set the total data holding time by adding the on / off time of the power source so that the refresh operation is not frequently performed, thereby reducing power consumption and improving operation performance.

According to one aspect of the present invention, there is provided a semiconductor memory device including a cell array including a phase change resistance cell to read / write data; A register for storing information of the cell array; And refresh control means for performing a refresh operation at a specific refresh cycle by using information stored in a register to improve retention characteristics of data stored in the cell array.

In addition, the present invention provides a cell array including read / write of data, including a phase change resistance cell; And refresh control means for performing a refresh operation at a specific refresh cycle using information stored in a register to improve retention characteristics of data stored in the cell array, wherein the cell array comprises: a read / write bit line for supplying a cell driving voltage; A select switch connected to the read / write bit line and controlled by the word line; A plurality of phase change resistance cells connected in series between the selection switch and the source line to read / write data according to the cell driving voltage; And a plurality of switching elements connected in parallel with each of the plurality of phase change resistance cells and selectively controlled by the plurality of bit lines.

In addition, the refresh method of the semiconductor memory device of the present invention, the cell array including a phase change resistance element for detecting the crystallization state changes according to the magnitude of the current applied through the bit line to store data corresponding to the change in resistance Reading / writing data to the; And refreshing the data in the cell array at specific refresh cycles to improve retention characteristics of the data stored in the cell array.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

5 is a diagram illustrating a memory cell array of a semiconductor memory device according to the present invention.

In the semiconductor memory device of the present invention, a plurality of bit lines BL are arranged in the row direction, and a plurality of word lines WL and a plurality of source lines SL are arranged in the column direction. A plurality of unit cells UC are formed in regions where the plurality of word lines WL, the plurality of source lines SL, and the plurality of bit lines BL intersect.

Each unit cell UC includes one switching element T and one resistive element. Here, the resistive element may be made of a magnetic tunnel junction (MTJ) or a resistive switch device (RSD) of a resistive random access memory device (ReRAM). In the present invention, the resistive element is made of a phase change resistive element PCR Will be described by way of example.

However, the present invention is not limited thereto, and the resistive element may be made of any element that discriminates data in response to a resistance value changed according to the magnitude of the current or the voltage.

The switching element T selectively switches between the source line SL and the phase change resistance element PCR by switching according to the state of the word line WL. The phase change resistance element PCR is connected between one end of the switching element T and the bit line BL. Here, the switching element mainly uses an NMOS transistor whose switching operation is controlled by a gate control signal.

One-to-one corresponding sense amplifier S / A is connected to each bit line BL to sense and amplify cell data applied from the bit line BL. Accordingly, the cell data "1" and the data "0" can be distinguished.

In addition, the write driver W / D is connected in one-to-one correspondence with the bit line BL. When writing data to a memory cell, the write driver W / D generates a driving voltage according to the write data and supplies the driving voltage to the bit line BL. In addition, the register REG is a temporary storage device for temporarily storing the data of the sense amplifier S / A and is connected to each bit line BL.

6A is a diagram for describing a high data write operation of the semiconductor memory device according to the present invention.

First, in the write operation mode of the data "1", a high voltage (power supply voltage or pumping voltage), which is a cell activation voltage, is applied to the word line WL, a pumping voltage VPP, which is a reset write voltage, is applied to the bit line BL, and a source line SL. Apply ground voltage GND.

In this case, the switching element T is turned on according to the high voltage applied to the word line WL so that the source line SL and the phase change resistance element PCR are connected to each other. In this state, when the voltage of the bit line BL becomes higher than the voltage of the source line SL, the phase change resistance element PCR is reset according to the pumping voltage VPP applied to the bit line BL. Thus, data "1" can be stored in the phase change resistance element PCR.

6B is a view for explaining a low data write operation of the semiconductor memory device according to the present invention.

First, a high voltage (power supply voltage or pumping voltage) is applied to the word line WL in the write operation mode of the data "0", and the ground voltage GND is applied to the source line SL. Then, a set write voltage having a low voltage level is applied to the bit line BL step by step from the pumping voltage VPP level.

In this case, the switching element T is turned on according to the high voltage applied to the word line WL so that the source line SL and the phase change resistance element PCR are connected to each other. In this state, the phase change resistance element PCR is in a set state according to the set write voltage in the form of a stepwise pulse applied to the bit line BL. Thus, data "0" can be stored in the phase change resistance element PCR.

7 is a view for explaining a data read operation of the semiconductor memory device according to the present invention.

First, in the data read operation mode, a high voltage (power supply voltage or pumping voltage) is applied to the word line WL, a read voltage Vread is applied to the bit line BL, and a ground voltage GND is applied to the source line SL.

In this case, the switching element T is turned on according to the high voltage applied to the word line WL so that the source line SL and the phase change resistance element PCR are connected to each other. Accordingly, data "0" or data "1" stored in the phase change resistance element PCR can be sensed.

8A is a diagram for describing a high data refresh operation of the semiconductor memory device according to the present invention.

First, in the refresh operation mode of the data "1", a high voltage (power supply voltage or pumping voltage) is applied to the word line WL in the read period t0, the read voltage Vread is applied to the bit line BL, and the ground voltage GND to the source line SL. Is applied.

In this case, the switching element T is turned on according to the high voltage applied to the word line WL so that the source line SL and the phase change resistance element PCR are connected to each other. Accordingly, the data "1" stored in the phase change resistance element PCR can be sensed.

Subsequently, a high voltage (power supply voltage or pumping voltage) is applied to the word line WL in the resave period t1, and a pumping voltage VPP for writing the data "1" read in the bit line BL is applied to the source line SL. Apply ground voltage GND.

In this case, the switching element T is turned on according to the high voltage applied to the word line WL so that the source line SL and the phase change resistance element PCR are connected to each other. In this state, when the voltage of the bit line BL becomes higher than the voltage of the source line SL, the phase change resistance element PCR is reset according to the pumping voltage VPP applied to the bit line BL. As a result, data "1" can be restored in the phase change resistance element PCR.

8B is a view for explaining a row data refresh operation of the semiconductor memory device according to the present invention.

First, in the refresh operation mode of the data "0", a high voltage (power supply voltage or pumping voltage) is applied to the word line WL in the read period t0, the read voltage Vread is applied to the bit line BL, and the ground voltage GND to the source line SL. Is applied.

In this case, the switching element T is turned on according to the high voltage applied to the word line WL so that the source line SL and the phase change resistance element PCR are connected to each other. Accordingly, the data "0" stored in the phase change resistance element PCR can be sensed.

Subsequently, in the restoring period t1, a high voltage (power supply voltage or pumping voltage) is applied to the word line WL, and in the form of a pulse that is gradually lowered from the pumping voltage VPP to write the data "0" read to the bit line BL. The set write voltage is applied, and the ground voltage GND is applied to the source line SL.

In this case, the switching element T is turned on according to the high voltage applied to the word line WL so that the source line SL and the phase change resistance element PCR are connected to each other. In this state, the phase change resistance element PCR is in a set state according to the set write voltage in the form of a stepwise pulse applied to the bit line BL. As a result, data "0" can be restored in the phase change resistance element PCR.

9 is another embodiment of a cell array of a semiconductor memory device according to the present invention.

In the present invention, a plurality of bit lines BL are arranged in a row direction, and a plurality of word lines WL are arranged in a column direction. The unit cell UC is formed in an area where the plurality of bit lines BL and the plurality of word lines WL cross each other.

Here, the unit cell UC includes a phase change resistance element PCR and a diode D. The diode D is preferably made of a PN diode element. One electrode of the phase change resistance element PCR is connected to the bit line BL, and the other electrode is connected to the P-type region of the diode D. The N-type region of diode D is connected to wordline WL. The phase of the phase change resistance element PCR is changed according to the set current Iset and the reset current Ireset flowing in the bit line BL, so that data can be written.

One-to-one corresponding sense amplifier S / A is connected to each bit line BL to sense and amplify cell data applied from the bit line BL. Accordingly, the cell data "1" and the data "0" can be distinguished.

In addition, the write driver W / D is connected in one-to-one correspondence with the bit line BL. When writing data to a memory cell, the write driver W / D generates a driving voltage according to the write data and supplies the driving voltage to the bit line BL. In addition, the register REG is a temporary storage device for temporarily storing the data of the sense amplifier S / A and is connected to each bit line BL.

10A is a diagram for describing a high data write operation of the semiconductor memory device according to the exemplary embodiment of FIG. 9.

First, in the write operation mode of the data "1", a low voltage (ground voltage or ground voltage) is applied to the word line WL, and the pumping voltage VPP is applied to the bit line BL.

In this case, a current path is formed between the bit line BL and the diode D and the phase change resistance element PCR according to the low voltage applied to the word line WL. In this state, the phase change resistance element PCR is reset according to the pumping voltage VPP applied to the bit line BL. Thus, data "1" can be stored in the phase change resistance element PCR.

10B is a view for explaining a low data write operation of the semiconductor memory device according to the present invention.

First, in the write operation mode of the data "0", a low voltage (ground voltage or ground voltage) is applied to the word line WL, and a set write voltage having a voltage level gradually lowered from the pumping voltage VPP level is applied to the bit line BL. do.

In this case, a current path is formed between the bit line BL and the diode D and the phase change resistance element PCR according to the low voltage applied to the word line WL. In this state, the phase change resistance element PCR is in a set state according to the set write voltage in the form of a stepwise pulse applied to the bit line BL. Thus, data "0" can be stored in the phase change resistance element PCR.

11 is a view for explaining a data read operation of the semiconductor memory device according to the present invention.

First, in the data read operation mode, a low voltage (ground voltage or ground voltage) is applied to the word line WL, and a read voltage Vread is applied to the bit line BL.

In this case, a current path is formed between the bit line BL and the diode D and the phase change resistance element PCR according to the low voltage applied to the word line WL. Accordingly, data "0" or data "1" stored in the phase change resistance element PCR can be sensed.

12A is a diagram for describing a high data refresh operation of the semiconductor memory device according to the present invention.

First, in the refresh operation mode of the data "1", a low voltage (ground voltage or ground voltage) is applied to the word line WL in the read period t0, and the read voltage Vread is applied to the bit line BL.

In this case, a current path is formed between the bit line BL and the diode D and the phase change resistance element PCR according to the low voltage applied to the word line WL. Accordingly, the data "1" stored in the phase change resistance element PCR can be sensed.

Subsequently, a low voltage (ground voltage or ground voltage) is applied to the word line WL in the resave period t1, and a pumping voltage VPP for writing the read data "1" is applied to the bit line BL.

In this case, a current path is formed between the bit line BL and the diode D and the phase change resistance element PCR according to the low voltage applied to the word line WL. In this state, the phase change resistance element PCR is reset according to the pumping voltage VPP applied to the bit line BL. As a result, data "1" can be restored in the phase change resistance element PCR.

12B is a view for explaining a row data refresh operation of the semiconductor memory device according to the present invention.

First, in the refresh operation mode of the data "0", a low voltage (ground voltage or ground voltage) is applied to the word line WL in the read period t0, and the read voltage Vread is applied to the bit line BL.

In this case, a current path is formed between the bit line BL and the diode D and the phase change resistance element PCR according to the low voltage applied to the word line WL. Accordingly, the data "0" stored in the phase change resistance element PCR can be sensed.

Subsequently, in the restoring period t1, a low voltage (ground voltage or ground voltage) is applied to the word line WL, and a set write voltage in the form of a pulse which is gradually lowered from the pumping voltage VPP to write the read data "0" is applied. Applies to bit line BL.

In this case, a current path is formed between the bit line BL and the diode D and the phase change resistance element PCR according to the low voltage applied to the word line WL. In this state, the phase change resistance element PCR is in a set state according to the set write voltage in the form of a stepwise pulse applied to the bit line BL. As a result, data "0" can be restored in the phase change resistance element PCR.

13 is another embodiment of a cell array of a semiconductor memory device according to the present invention.

The present invention includes a selection switch N1, a plurality of phase change resistance cells PCR1 to PCRn and a plurality of switching elements N2 to N5.

Here, it is preferable that the selection switch N1 and the plurality of switching elements N2 to N5 consist of NMOS transistors. The select switch N1 is connected between the read / write bitline RWBL and the unit cell UC1 so that the gate terminal is connected to the wordline WL.

In each unit cell UC1, one phase change resistance cell PCR1 and one switching element N2 are connected in parallel. One electrode of the phase change resistance cell PCR1 is connected to the source terminal of the switching element N2, and the other electrode of the phase change resistance cell PCR1 is connected to the drain terminal of the switching element N2. In addition, the gate terminals of the switching elements N2 to N5 are connected one-to-one to the plurality of bit lines BL1 to BLn.

In addition, the plurality of phase change resistance cells RCR1 to RCRn are connected in series with each other between the select switch N1 and the source line SL. That is, the source terminal of one phase change resistance cell PCR1 is connected to the drain terminal of the adjacent phase change resistance cell PCR2. The first phase change resistance cell PCR1 of the plurality of phase change resistance cells RCR1 to PCRn connected in series is connected to the selection switch N1, and the last phase change resistance cell PCRn is connected to the source line SL.

Herein, the present invention has been described in the embodiment that the selection switch N1 and the plurality of switching elements N2 to N5 are NMOS transistors. However, the present invention is not limited thereto, but the PMOS transistor, the bipolar junction transistor, or the PNPN diode switch is used. It may be.

14A and 14B are circuit diagrams of the semiconductor memory device according to the exemplary embodiment of FIG. 13 and operational waveform diagrams in a read mode.

In the present invention, it is assumed that the first unit cell including the phase change resistance cell PCR1 and the switching element N2 is selected in the read mode. In this case, a low voltage is applied to the bit line BL1 connected to the selected cell to maintain the selected unit cell in an off state. In addition, a high voltage is applied to the bit lines BL2 to BLn connected to the remaining unselected cells so that all unselected unit cells remain on.

First, in the t0 period, the word line WL, the read / write bit line RWBL, the source line SL, and the plurality of bit lines BL1 to BLn all maintain the low level. As a result, the selection switch N1 is maintained in the turn-off state, thereby disconnecting the unit cell from the read / write bit line RWBL.

Subsequently, upon entering the read period t1, the word line WL transitions to a high level. Accordingly, the select switch N1 is turned on to connect the phase change resistance cell PCR1 of the selected unit cell with the read / write bit line RWBL.

At this time, the source line SL maintains the ground voltage level. In addition, the ground voltage is applied to the bit line BL1 connected to the selection cell to maintain the switching element N2 in the turn-off state.

Then, the remaining bit lines BL2 to BLn connected to the unselected cell transition to the high voltage level. As a result, all of the switching elements N3 to N5 connected to the remaining bit lines BL2 to BLn are turned on to be in series connection between the phase change resistance cell PCR1 and the source line SL.

In addition, a sensing voltage Vsense for sensing data among cell driving voltages is applied to the read / write bit line RWBL. Accordingly, the current read in the phase change resistance cell PCR1 corresponding to the selected unit cell flows between the read / write bit line RWBL and the source line SL.

15A and 15B are circuit diagrams of the semiconductor memory device according to the exemplary embodiment of FIG. 13 and operational waveform diagrams in a write mode.

In the present invention, it is assumed that all unit cells connected between the selection switch N1 and the source line SL are selected in the write mode. In this case, the voltages applied to the bit lines BL1 to BLn connected to all the unit cells are selectively adjusted to simultaneously write the corresponding data to the plurality of phase change resistance cells PCR1 to PCRn.

First, in the t0 period, the word line WL, the read / write bit line RWBL, the source line SL, and the plurality of bit lines BL1 to BLn all maintain the low level. As a result, the selection switch N1 is maintained in the turn-off state, thereby disconnecting the unit cell from the read / write bit line RWBL.

Thereafter, the word line WL transitions to a high level when the write period t1 is entered. Accordingly, the select switch N1 is turned on so that the phase change resistance cell PCR1 of all the unit cells is connected to the read / write bit line RWBL.

At this time, the source line SL maintains the ground voltage level. The write voltage Vwrite for writing data among the cell driving voltages is applied to the read / write bit line RWBL. As a result, data corresponding to all the phase change resistance cells PCR1 to PCRn can be written at the same time.

For example, when the set state, that is, data "0", is written to the phase change resistance cell PCR1, the bit line BL1 connected to the phase change resistance cell PCR1 transitions to a high voltage level. Thus, the switching element N2 is turned on and the write voltage Vwrite applied through the selection switch N1 is applied to the phase change resistance cell PCR1 and the switching element N2.

Therefore, the write current flows into the phase change resistance cell PCR1 and the switching element N2. In this case, the current flowing through the phase change resistance cell PCR1 becomes smaller than the total current, and data "0" is written to the phase change resistance cell PCR1. That is, assuming that the total current flowing through the select switch N1 is a reset current, a set current lower than the reset current flows through the phase change resistance cell PCR1.

When the reset state, that is, data "1", is written to the phase change resistance cell PCR2, the bit line BL2 connected to the phase change resistance cell PCR2 maintains the low voltage level. Accordingly, the switching element N3 is turned off and the write voltage Vwrite applied through the selection switch N1 is applied to the phase change resistance cell PCR2 and the switching element N3.

Therefore, the write current flows only in the phase change resistance cell PCR2. In this case, the current flowing through the phase change resistance cell PCR2 corresponds to the total current, and data "1" is written to the phase change resistance cell PCR2. That is, assuming that the entire current flowing through the selector switch N1 is a reset current, the reset current flows through the phase change resistance cell PCR2.

When the set state, that is, data "0", is written to the phase change resistance cell PCRn-1, the bit line BLn-1 connected to the phase change resistance cell PCRn-1 transitions to a high voltage level. Thus, the switching element N4 is turned on and the write voltage Vwrite applied through the selection switch N1 is applied to the phase change resistance cell PCRn-1 and the switching element N4.

Therefore, the write current flows into the phase change resistance cell PCRn-1 and the switching element N4. In this case, the current flowing in the phase change resistance cell PCRn-1 becomes smaller than the total current, and data "0" is written in the phase change resistance cell PCRn-1. That is, assuming that the total current flowing through the selection switch N1 is a reset current, a set current lower than the reset current flows in the phase change resistance cell PCRn-1.

When the reset state, that is, data "1", is written to the phase change resistance cell PCRn, the bit line BLn connected to the phase change resistance cell PCRn maintains the low voltage level. As a result, the switching element N5 is turned off and the write voltage Vwrite applied through the selection switch N1 is applied to the phase change resistance cell PCRn and the switching element N5.

Therefore, the write current flows only in the phase change resistance cell PCRn. In this case, the current flowing through the phase change resistance cell PCRn corresponds to the total current, and data "1" is written to the phase change resistance cell PCRn. That is, assuming that the total current flowing through the selection switch N1 is a reset current, the reset current flows through the phase change resistance cell PCRn.

In this way, the total current flowing through the selector switch N1 is the same, and a small set current flows in the phase change resistance cells PCR1 and PCRn-1 in which the set state is written, and the phase change resistance cells PCR2 and PCRn in which the reset state is written. Large reset current flows through it.

According to the present invention, data can be simultaneously written to a plurality of phase change resistance cells PCR1 to PCRn without increasing the write current according to the series-connected phase change resistance cells PCR1 to PCRn. Accordingly, the present invention can reduce the size of the write current for writing data to the cell to 1 / N, compared with the prior art. According to the present invention, the write time for writing data into a cell can be reduced to 1 / N, compared with the related art.

16 illustrates a cell array of a semiconductor memory device according to the present invention.

In the present invention, a plurality of read / write bit lines RWBL1 to RWBLn are arranged in the row direction. The plurality of bit lines BL1 to BLn are arranged in the row direction. Further, a plurality of word lines WL1 to WLn are arranged in the column direction.

Further, the selection switch N1 is arranged in an area where the plurality of read / write bit lines RWBL1 to RWBLn and the plurality of word lines WL1 to WLn intersect. A plurality of such selection switches N1 are arranged in the row and column directions.

The unit cell UC is arranged in an area where the plurality of bit lines BL1 to BLn and the plurality of word lines WL1 to WLn intersect. A plurality of such unit cells UC are arranged in the row and column directions. Here, one read / write bitline RWBL is shared by the plurality of select switches N1. One source line SL is shared by a plurality of unit cells UC.

In addition, the read / write bit line RWBL is connected to the sense amplifier S / A and the global write driver GWD. Accordingly, the sense amplifier S / A senses and amplifies the sensing voltage Vsense applied through the read / write bit line RWBL in the read operation mode. The global write driver GWD supplies the write voltage Vwrite to the read / write bit line RWBL in the write operation mode.

Each bit line BL is connected to the write driver W / D. Accordingly, the unit cell UC is selected by selectively controlling the voltage applied to the bit line BL according to the voltage of the write driver W / D in the read or write operation mode.

In addition, the source line SL is connected to the source driver SD. Accordingly, the voltage applied to the source line SL may be selectively adjusted according to the voltage (ground voltage) of the source driver SD in the read or write operation mode.

17 is an overall configuration diagram of a semiconductor memory device according to the present invention.

The present invention provides the pad array 100, the refresh control means 110, the row address register 120, the row timing logic 130, the row decoder 140, the cell array 150, the read / The write control unit 160, the column decoder 170, the column address register 180, the column timing logic 190, the refresh register 200, the sense amplifier S / A, the register REG, and the write driver W / D, input / output logic 210, I / O register 220, I / O buffer 230 and I / O pins 240.

Here, the refresh control means 110 includes a refresh controller 111 and a refresh counter 112. The cell array 150 of the present invention is configured to include a plurality of structures of one of the phase change resistance cells according to the embodiments of FIGS. 5 to 15a.

The pad array 100 includes a plurality of pad PADs, and receives a row address and a column address through one pad and outputs them with a time difference. The refresh control unit 111 outputs the refresh signal REF and the refresh enable signal REF_EN for controlling the refresh operation according to the ras signal / RAS, the cas signal / CAS, the read / write command R, / W and the refresh control signal REF_CON. do. The refresh counter 112 counts the refresh period according to the refresh signal REF applied from the refresh control unit 111 and the refresh control signal REF_CON applied from the refresh register 200, and outputs a count address CA.

The row address register 120 receives a row address applied from the pad array unit 100 and temporarily stores the row address. The row address register 120 outputs the activated row address RADD to the row decoder 140 according to the output of the row timing logic 130 and the read / write control signal RWCON applied from the read / write control unit 160. . The row timing logic 130 controls the storage operation and the address output timing of the row address register 120 according to the ras signal / RAS. The row decoder 140 decodes the activated row address RADD applied from the row address register 120 and outputs the decoded row address RADD to the cell array 150.

The read / write control unit 160 also controls read / write control signals to the row address register 120 in response to the ras signal / RAS, cas signal / CAS, and read / write commands R and / W. The RWCON is output, and the operations of the column decoder 170, the sense amplifier S / A, the register REG, and the write driver W / D are controlled.

The column decoder 170 decodes the column address applied from the column address register 180 under the control of the read / write controller 160 and outputs the decoded column address to the input / output logic 210. The column address register 180 receives a column address applied from the pad array 100 and temporarily stores the column address, and outputs the column address to the column decoder 170 under the control of the column timing logic 190.

In addition, the column timing logic 190 controls the storage operation and the address output timing of the column address register 180 according to the cas signal / CAS. The column address register 180 provides the refresh data to the memory cell under the control of the column timing logic 190 when the refresh signal REF is activated.

The refresh register 200 is a nonvolatile register for storing parameters related to refresh. The refresh register 200 stores refresh count information, information on power-off time of the system or internal memory, and various other parameter information. The refresh register 200 outputs a refresh control signal REF_CON based on the parameter information during the refresh operation. .

The sense amplifier S / A is configured to detect and amplify cell data to distinguish data "1" from data "0". The write driver W / D is configured to generate a driving voltage according to the write data to supply the bit line when writing data to the memory cell. In addition, the register REG temporarily stores data sensed by the sense amplifier S / A, and re-stores the data in the memory cell during the write operation.

The input / output logic 210 reads data stored in the cell array 150 or stores data in the cell array 150 according to the output of the column decoder 170 and the read / write commands R and / W. Here, the input / output logic 210 preferably includes a column select signal C / S. The input / output logic 210 outputs data stored in the cell array 150 to the data I / O register 220 according to the output enable signal / OE.

The I / O buffer 230 buffers read data stored in the I / O register 220 or write data applied through the I / O pins 240 under the control of the refresh register 200. The I / O pins 240 output data applied from the I / O buffer 230 to the system controller 300 through the data bus, or output data applied from the system controller 300 through the data bus. Output to the buffer 230.

18 is a timing diagram of the read operation of the semiconductor memory device according to the present invention, and FIG. 19 is a timing diagram of the write operation of the semiconductor memory device according to the present invention.

An operation process of the present invention having the above-described configuration will now be described with reference to the operation timing diagrams of FIGS. 18 and 19.

First, the pad array 100 receives a row address and a column address through a plurality of pad PADs and outputs them to the row address register 120 and the column address register 180, respectively. Subsequently, the row address register 120 and the column address register 180 are controlled by the row timing logic 130 and the column timing logic 190 by a timing multiplexing method. Output the column address.

18 and 19, the row address register 120 temporarily stores the row address in synchronization with the ras signal / RAS and outputs the activated row address RADD to the row decoder 140. do. In the output operation of the row address RADD, the column address register 180 temporarily stores the input column address.

18 and 19, the column address register 180 temporarily stores the column address in synchronization with the cas signal / CAS and outputs the column address to the column decoder 170. In the output operation of the column address, the row address register 120 temporarily stores the input row address.

Subsequently, when the output enable signal / OE is activated while the read command R is activated in the read operation mode, data stored in the cell array 150 is output to the I / O register 220 according to the input / output logic 210. do. On the other hand, when the output enable signal / OE is deactivated while the write command / W is activated in the write operation mode, data is stored in the cell array 150 according to the input / output logic 210.

20 is a detailed configuration diagram illustrating the row address register 120 of FIG. 17.

The row address register 120 includes an address buffer, a latch 121, and a selector 122. Here, it is preferable that the selection unit consists of a multiplexer.

The address buffer and the latch 121 buffer and latch the row address applied from the pad array 100 according to the read / write control signal RWCON applied from the read / write control unit 160. The selector 122 may select any one of a count address CA or an output of the address buffer and the latch 121 applied from the refresh counter 112 according to the activation state of the refresh enable signal REF_EN applied from the refresh control unit 111. Select to output the activated row address RADD to the row decoder 140.

That is, the row address register 120 selects a row address applied from the pad array 100 and outputs the row address to the row decoder 140 in the normal operation. When the refresh enable signal REF_EN is activated in the refresh operation mode, the count address CA applied from the refresh counter 112 is selected and output to the row decoder 140.

21 is an operation timing diagram relating to a refresh method of a semiconductor memory device according to the present invention.

The refresh control unit 111 refreshes the refresh signal REF for performing the refresh operation when the refresh operation command is applied according to the combination of the ras signal / RAS, the cas signal / CAS, the read / write command R, / W and the refresh control signal REF_CON. The counter 112 outputs the refresh enable signal REF_EN to the row address register 120. In addition, the refresh counter 112 counts the refresh period according to the refresh signal REF and the refresh control signal REF_CON applied from the refresh control unit 111 and outputs the count address CA to the row address register 120.

The count address CA output from the refresh counter 112 is stored in the row address register 120. Thereafter, the column timing logic 190 outputs the data stored in the column address register 180 to the column decoder 170 in response to the cas signal / CAS. In the state where the sense amplifier S / A is activated, the refresh data stored in the register REG is written to the cell array 150 through the input / output logic 210.

Here, the refresh signal REF may be a control signal using the ras signal / RAS and the cas signal / CAS. That is, when the refresh signal REF is a control signal using the ras signal / RAS and the cas signal / CAS, the refresh operation is performed using a cas biphoras (/ CBR; / CAS Before / RAS) method.

For example, in the normal operation mode for performing the read or write operation, the ras signal / RAS is activated before the cas signal / CAS and the normal operation is performed according to the row timing logic 130 and the column timing logic 190. . That is, as in (A), when the ras signal / RAS is activated first, the external row address is activated to activate the sense amplifier S / A. After that, the external column address is activated when the cas signal / CAS is activated as in (B).

On the other hand, in the refresh mode, the refresh signal REF is activated by detecting that the cas signal / CAS is transitioned before the lath signal / RAS through the refresh control unit 111. That is, if the refresh control unit 111 detects that the cas signal / CAS is transitioned before the ras signal / RAS, the refresh control unit 111 determines the refresh mode and activates the refresh enable signal REF_EN.

When the refresh enable signal REF_EN is activated, the row address register 120 performs a refresh operation according to the count address CA generated by the refresh counter 112 while the path of the normal operation mode is blocked. Here, the refresh signal REF may be activated by detecting that the cas signal / CAS and the ras signal / RAS are simultaneously transitioned.

In the present invention, the refresh method using the cas biphoras (/ CBR; / CAS Before / RAS) method was described as an embodiment, the present invention is not limited to this, Self (Self) refresh, Auto (Auto) refresh Alternatively, the refresh operation may be performed through various methods similarly applicable using a clock or the like.

That is, in the refresh mode, the word line WL of the cell array 150 is selected according to the count address CA which is the output of the refresh counter 112. Accordingly, the cell array 150 senses and amplifies data of the corresponding cell having the 1T structure and stores the data in the sense amplifier register REG. Then, new data is written to the cell array 150 or data stored in the register REG is re-stored in the cell array 150.

22 and 23 are flowcharts for describing a method of refreshing a semiconductor memory device according to the present invention.

First, the DRAM, which is a volatile memory, uploads data in the memory (step S12) again when power is turned on (step S11) while the system power is turned off (step S10). The new refresh operation is started (step S13). In other words, when the system powers back on, the data in the memory must be uploaded unconditionally.

However, in the semiconductor memory device of the present invention, when the power is turned on (step S20) while the system power is turned off (step S21), the data is stored to determine what data is stored in the phase change resistance element PCR. After the refresh operation starts (step S23), it is determined whether the refresh time has been exceeded in the refresh register 200 (step S24).

As a result of the determination of the refresh register 200, when the preset refresh time is exceeded, data of the memory is uploaded again (step S25) to start a new refresh operation. (Step S27)

On the other hand, as a result of the determination of the refresh register 200, when the preset refresh time is not exceeded, it is determined that the refresh time is valid and continues the previous refresh operation. (Step S26) Accordingly, the phase change resistance element PCR Will restore the data from the memory cell array back to the memory cell array.

That is, the refresh register 200 stores parameters related to refresh in a nonvolatile register. The refresh register 200 stores the refresh count information, the power-off time of the system or the internal memory, and various other parameter information in a nonvolatile state. Here, the refresh register 200 may detect that the power of the system or the internal memory is turned on / off through a separate power sensing means (not shown).

Accordingly, data stored in the refresh register 200 is read at power-off to calculate the elapsed refresh time. Here, the refresh elapsed time may be pre-stored through a separate mode register set (MRS), and the refresh elapsed time may be controlled at the system level.

Thereafter, the refresh elapsed time calculated according to the refresh control signal REF_CON is transmitted to the refresh control unit 111 to control the refresh operation. Accordingly, the present invention does not need to upload the refresh related information even when the power is turned on in the power-off state.

24 is a view for explaining a refresh method of a semiconductor memory device according to the present invention. The refresh method according to the present invention is largely divided into a distributed refresh method and a burst refresh method.

First, the distributed refresh method is a method of performing a refresh operation at the same time allocation so that all cells can be refreshed within the refresh time according to the count address CA counted by the refresh counter 112. That is, if 8k rows are refreshed, the refresh operation is performed in a cycle in which each distributed refresh operation cycle is (refresh time) / 8k. Thus, data must be written for all word lines WL to be in an initialized state.

Second, the burst refresh method refers to a method of continuously performing an 8k refresh cycle during a burst refresh cycle time. Here, each pulse means each refresh cycle, and normal operation is performed in the read / write operation cycle section in which the pulse is inactive.

FIG. 25 is a diagram illustrating a timer control operation in the refresh method of the semiconductor memory device according to the present invention.

The refresh register 200 of the present invention determines whether the system power is off and stores the result. (Step S30) As a result of the determination of the refresh register 200, when the power is off, the internal memory timer is turned off. The refresh operation is controlled using a system timer possessed by the system (step S31). (Step S32) This system timer mainly stores a date, time, etc. using a battery, so that the power is always on.

On the other hand, as a result of the determination of the refresh register 200, when the power is not turned off, the internal refresh operation is controlled using an internal memory timer that operates independently (step S33).

Herein, the present invention allows the user to select either an external system timer or an internal memory timer according to the on / off state of the power through the input / output data pins 240. That is, the refresh register 200 of the memory device including the internal memory timer exchanges data with the data bus through the I / O buffer 230 and the I / O pins 240. In addition, a system (CPU) including a system timer exchanges data with a memory device through a data bus.

Accordingly, the refresh operation is performed using an external system timer that is always turned on when the power is turned off by exchanging data between the memory device and the system controller 300, and when the power is turned on, the internal memory timer is executed. The refresh operation is performed.

The present invention can effectively maintain the refresh period and the memory data irrespective of whether the power supply of the memory chip is turned on or off. Accordingly, the memory chip power may be turned off between the refresh periods to reduce the current consumed by the chip, and the chip power may be supplied only during the refresh period to perform the refresh operation.

26 is a graph illustrating data retention characteristics of the semiconductor memory device according to the present invention.

The memory cell of the conventional semiconductor memory device has a non-volatile characteristic, but the deterioration condition of the cell data occurs over time in an actual situation, and thus the data retention life is limited. Accordingly, as time passes, the bit line BL current corresponding to the non-cell data "1" and "0" decreases.

However, the present invention improves data retention characteristics by recovering deteriorated cell data by performing a refresh operation at a specific period at a specific time when the bit line BL current decreases.

That is, the present invention drives the refresh circuit to restore the cell data back to the initial state when the storage data holding characteristic of the memory cell is reduced to a predetermined target value or more. The deterioration threshold target time of the cell set as described above becomes the refresh time, and all the cells always operate within the refresh time.

Here, since the present invention has a nonvolatile characteristic, the power supply may be turned off. In addition, the sum of the on / off times of the power supply is set as the total data retention time, so that the refresh operation is not frequently performed, thereby reducing power consumption and improving operation performance.

As described above, the present invention has the following effects.

First, the present invention improves the structure of a cell by applying a phase change resistor (PCR) element to a DRAM, thereby reducing the size of the cell.

Second, the present invention implements a semiconductor memory device having one switching element and one phase change resistance element and performs a refresh operation to improve data retention characteristics.

Third, the present invention can preserve data when the power is turned off in the phase change memory device as it is, and at the same time, perform data refresh at a specific cycle to restore deteriorated cell data, thereby improving data retention characteristics.

Fourthly, the present invention maintains the refresh information even when the power supply is turned off by performing the refresh operation according to the parameter information stored in the nonvolatile register when the power supply is turned off.

Fifth, the present invention sets the total data holding time by adding the on / off time of the power supply so that the refresh operation is not frequently performed, thereby reducing power consumption and improving operation performance.

Sixth, the present invention controls the refresh operation according to the system timer when the power is off, thereby providing an effect of effectively maintaining the refresh period and the memory data regardless of the power on / off.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (34)

A cell array including read / write of data including phase change resistance cells; A register to store information of the cell array; And And refresh control means for performing a refresh operation at a specific refresh cycle by using information stored in the register to improve retention characteristics of data stored in the cell array. The method of claim 1, wherein the phase change resistance cell A phase change resistance element configured to store a data corresponding to a change in resistance by detecting a crystallization state that changes according to the magnitude of the current applied through the bit line; And And a switching element connected between the phase change resistance element and the source line and controlled by a word line. The method of claim 2, wherein the phase change resistance cell And a cell activation voltage is applied to the word line, a reset write voltage is applied to the bit line, and a ground voltage is applied to the source line during the write operation of the high data. The semiconductor memory device of claim 3, wherein the reset write voltage has a pumping voltage level. The method of claim 2, wherein the phase change resistance cell And a cell activation voltage is applied to the word line, a set write voltage is applied to the bit line, and a ground voltage is applied to the source line. 6. The semiconductor memory device as claimed in claim 5, wherein the set write voltage has a voltage level that is gradually lowered from a pumping voltage level. The method of claim 2, wherein the phase change resistance cell And a cell activation voltage is applied to the word line, a read voltage is applied to the bit line, and a ground voltage is applied to the source line during a data read operation. The method of claim 1, wherein the phase change resistance cell A phase change resistance element configured to store a data corresponding to a change in resistance by detecting a crystallization state that changes according to the magnitude of the current applied through the bit line; And And a diode device connected between the phase change resistance device and the word line. The method of claim 8, wherein the phase change resistance cell And a cell activation voltage is applied to the word line and a reset write voltage is applied to the bit line during the write operation of the high data. 10. The semiconductor memory device of claim 9, wherein the reset write voltage has a pumping voltage level. The method of claim 8, wherein the phase change resistance cell And a cell write voltage is applied to the word line and a set write voltage is applied to the bit line during a write operation of row data. 12. The semiconductor memory device of claim 11, wherein the set write voltage has a voltage level that is gradually lowered from a pumping voltage level. The method of claim 8, wherein the phase change resistance cell And a cell activation voltage is applied to the word line and a read voltage is applied to the bit line during a data read operation. The method of claim 1, wherein the refresh control means Refresh control means for controlling a refresh operation according to a refresh control signal, and outputting a count address for the refresh operation; A row address control means for latching and decoding a row address input according to a erase signal and an output of the refresh control means, outputting the row address to the cell array, and selecting the count address and outputting the count address to the cell array during a refresh operation; Column address control means for latching and decoding the column address input according to the CAS signal; And And input / output logic for controlling a read / write operation of the cell array according to an output enable signal and a read / write command. 15. The apparatus of claim 14, wherein the refresh control means A refresh register which stores various parameter information for controlling the refresh operation in a nonvolatile manner and outputs the refresh control signal during a refresh operation; A refresh controller configured to output a refresh signal and a refresh enable signal to perform a refresh operation according to the refresh control signal; And And a refresh counter for counting a refresh period according to the refresh signal and outputting the count address. 16. The semiconductor memory device according to claim 15, wherein the refresh register stores refresh count information and information on power-off time of the system / internal memory. The method of claim 15, wherein the row address control means A row timing logic to control latch timing of the row address according to the lath signal; A row address register configured to latch the row address according to the control of the row timing logic and to select and output one of the row address or the count address according to a refresh enable signal; And And a row decoder configured to decode an output of the row address register and output the decoded output to the cell array. 18. The register of claim 17 wherein the row address register is An address buffer and a latch for buffering and latching the row address; And And a selector configured to select one of an output of the address buffer and the latch and the count address according to the refresh enable signal. The method of claim 15, wherein the column address control means Column timing logic to control latch timing of the column address in response to the cas signal; A column address register for latching the column address according to the control of the column timing logic; And And a column decoder for decoding the output of the column address register. The method of claim 1, wherein the cell array A sense amplifier for sensing and amplifying data stored in the cell array; And And a write driver for supplying a driving voltage corresponding to write data to the cell array. A cell array including read / write of data including phase change resistance cells; And Refresh control means for performing a refresh operation at a specific refresh cycle using information stored in the register to improve retention characteristics of data stored in the cell array; The cell array A read / write bit line for supplying a cell driving voltage; A select switch connected to the read / write bit line and controlled by a word line; A plurality of phase change resistance cells connected in series between the selection switch and the source line to read / write data according to the cell driving voltage; And And a plurality of switching elements connected to the plurality of phase change resistance cells in parallel and selectively controlled by a plurality of bit lines. The method of claim 21, wherein the cell array Sense amplifier for sensing and amplifying data stored in the cell array A write driver selectively supplying a driving voltage to the plurality of bit lines; A global write driver configured to supply the cell driving voltage to the read / write bit line; A source driver supplying a ground voltage or a write voltage to the source line; And And a register for storing data of the sense amplifier. 22. The method of claim 21, wherein the read operation of the data With the selection switch turned on and a sensing voltage applied to the read / write bit line and the source line maintaining the ground voltage level, And a current read from a selected phase change resistor cell among the plurality of phase change resistor cells flows from the read / write bit line toward the source line. 24. The method of claim 23, wherein the switching elements corresponding to the selected phase change resistance cells are turned off according to the voltage levels of the plurality of bit lines, and the switching elements corresponding to the remaining unselected phase change resistance cells are turned on. A semiconductor memory device characterized by the above-mentioned. 22. The method of claim 21, wherein the write operation of the data is performed. With the selection switch turned on and a write voltage applied to the read / write bit line and the source line maintaining the ground voltage level, When the first data is written to the plurality of phase change resistance cells, the switching element corresponding to the phase change resistance cell is turned on, and when the second data is written, the switching element corresponding to the phase change resistance cell is turned off. A semiconductor memory device, characterized in that. The method of claim 21, wherein the refresh control means Refresh control means for controlling a refresh operation according to a refresh control signal, and outputting a count address for the refresh operation; A row address control means for latching and decoding a row address input according to a erase signal and an output of the refresh control means, outputting the row address to the cell array, and selecting the count address and outputting the count address to the cell array during a refresh operation; Column address control means for latching and decoding the column address input according to the CAS signal; And And input / output logic for controlling a read / write operation of the cell array according to an output enable signal and a read / write command. 27. The apparatus of claim 26, wherein the refresh control means A refresh register which stores various parameter information for controlling the refresh operation in a nonvolatile manner and outputs the refresh control signal during a refresh operation; A refresh controller configured to output a refresh signal and a refresh enable signal to perform a refresh operation according to the refresh control signal; And And a refresh counter for counting a refresh period according to the refresh signal to output the count address. 28. The semiconductor memory device according to claim 27, wherein the refresh register stores refresh count information and information on power-off time of the system / internal memory. 27. The system of claim 26, wherein the row address control means A row timing logic to control latch timing of the row address according to the lath signal; A row address register configured to latch the row address according to the control of the row timing logic and to select and output one of the row address or the count address according to a refresh enable signal; And And a row decoder configured to decode an output of the row address register and output the decoded output to the cell array. 30. The method of claim 29 wherein the row address register is An address buffer and a latch for buffering and latching the row address; And And a selector configured to select one of an output of the address buffer and the latch and the count address according to the refresh enable signal. 27. The apparatus of claim 26, wherein the column address control means Column timing logic to control latch timing of the column address in response to the cas signal; A column address register for latching the column address according to the control of the column timing logic; And And a column decoder for decoding the output of the column address register. Reading / writing data into a cell array including a phase change resistance element that senses a crystallization state that changes according to the magnitude of a current applied through the bit line and stores data corresponding to a change in resistance; And And refreshing the data of the cell array at a specific refresh cycle in order to improve the retention characteristics of the data stored in the cell array. The method of claim 32, wherein the refreshing step Reading refresh count information previously stored in a nonvolatile state and off time information of a power supply; Detecting an on state of a power supply; Reading data stored in the cell array and storing the data in a register; Determining whether the refresh time has been exceeded during the refresh operation; And And re-storing data stored in the register in the cell array. 34. The method of claim 33, wherein the determining of the refresh time The method of claim 1, further comprising uploading data in the memory when the refresh time is exceeded, and performing a previous refresh operation when the refresh time is not exceeded.

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