KR20080110382A - LCD and its manufacturing method - Google Patents

Abstract

The present invention relates to a liquid crystal display device and a manufacturing method thereof. The disclosed liquid crystal display device includes a substrate having a gate electrode, a gate insulating film formed on the substrate, a semiconductor layer formed on the gate insulating film, and subsequently formed of an amorphous silicon film and a silicon film doped with impurities, and a substrate having a semiconductor layer. It includes a source electrode and a drain electrode formed on and spaced apart at regular intervals.

According to the above configuration, the present invention provides a semiconductor layer composed of an amorphous silicon film and a silicon film doped with impurities in order. Accordingly, the present invention increases the linear mobility of the amorphous silicon thin film transistor, thereby making it easy to apply to large-area high-resolution products and to facilitate circuit integration.

Description

Liquid crystal display device and manufacturing method thereof {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME}

1 is an exploded perspective view schematically illustrating a configuration of a general liquid crystal display device.

2 is a cross-sectional view showing the configuration of an amorphous thin film transistor having a general inverted staggered type TFT structure.

3 illustrates an energy band of a semiconductor layer in a turn-on state.

4 is a graph showing a relationship between resistances according to drain voltages.

5 is a plan view showing a liquid crystal display device according to a first embodiment of the present invention.

6A to 6F are cross-sectional views of processes according to the cutting line taken along the line II-II ′ of FIG. 5.

7 is a cross-sectional view of a liquid crystal display device in which the source electrode and the drain electrode do not overlap with the gate electrode in the first embodiment of the present invention.

8 is a diagram showing conductivity with respect to impurity doping concentration in the first embodiment of the present invention.

9 is a view showing a band energy structure between a source electrode and a channel in the first embodiment of the present invention.

10 is a graph comparing with the conventional case when the semiconductor layer according to the first embodiment of the present invention is applied.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a method of forming the same, and more particularly, to a liquid crystal display device and a method of forming the same, which can increase the mobility of a thin film transistor.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, LCD is the most widely used as the substitute for CRT (Cathode Ray Tube) for mobile image display device because of its excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention has been developed in a variety of monitors, such as television and computer for receiving and displaying broadcast signals.

1 is an exploded perspective view schematically illustrating a configuration of a general liquid crystal display device. Hereinafter, a configuration of a general liquid crystal display device will be described with reference to FIG. 1.

As shown in FIG. 1, a general liquid crystal display device may be classified into a liquid crystal panel 11 displaying an image and a driver (not shown) for applying a driving signal to the liquid crystal panel 11. The liquid crystal panel 11 may include a liquid crystal layer injected between the first and second substrates B2 and B1 bonded to each other with a predetermined space and the first and second substrates B2 and B1. Not shown).

In this case, the first substrate (thin film transistor array substrate) B1 is disposed on one side of the gate line 13 at a predetermined interval on the transparent substrate 22, and is perpendicular to each of the gate lines 13. A plurality of data lines 15 arranged at regular intervals in one direction, and a plurality of pixel electrodes 17 formed in a matrix form in each pixel region defined by the crossing of the gate lines 13 and the data lines 15. And a plurality of thin film transistors T, which are switched by the signal of the gate line 1 and transfer the signal of the data line 15 to each pixel electrode 17, are formed.

In addition, the second substrate (color filter array substrate) includes a light shielding layer 6 for blocking light of portions except the pixel region on the transparent substrate 5, and R, G, and B colors for expressing color colors. Filter layers 8a, 8b and 8c and a common electrode 18 for realizing an image are formed.

Although not shown in the drawings, the first and second substrates B1 and B2 are bonded to each other by a seal material having a predetermined space by a spacer and having a liquid crystal injection hole. Liquid crystal is injected in between.

In the first substrate B2, the thin film transistor T uses a semiconductor layer as an active layer. The semiconductor layer is formed of amorphous silicon or crystalline silicon. In this case, when amorphous silicon is used as the semiconductor layer, it is relatively easy to be produced by vapor phase deposition at a low temperature and has a feature suitable for mass production.

FIG. 2 is a cross-sectional view showing the configuration of an amorphous thin film transistor having an inverted staggered type TFT structure. Hereinafter, an amorphous thin film transistor of a general liquid crystal display device will be described with reference to FIG. 2.

As shown in FIG. 2, a general thin film transistor forms a gate electrode 32 on a transparent insulating substrate 30. In this case, the gate electrode 32 may use a low resistance metal such as aluminum. Subsequently, a gate insulating layer 34 is formed on the substrate having the gate electrode 32. In this case, silicon nitride or silicon oxide may be used as the gate insulating layer 34.

Next, an amorphous silicon film (a-Si crystalline) and a silicon film doped with impurities are sequentially formed on the gate insulating film 34. At this time, the amorphous silicon film is used to form a semiconductor layer, and is formed to have a thickness of 1500 to 3000 GPa.

Subsequently, the semiconductor layer 36 made of an amorphous silicon film is formed by patterning the silicon film and the amorphous silicon film doped with the impurity. Next, a second metal film is formed on the substrate having the semiconductor layer 36. Thereafter, the second metal film is patterned to form a source electrode 40 and a drain electrode 42. Subsequently, the silicon film doped with impurities remaining in the semiconductor layer 36 is removed using the source electrode 40 and the drain electrode 42 as a mask. As a result, an ohmic contact layer 38 made of a silicon film doped with the impurity is formed between the source electrode 40 / the drain electrode 42 and the semiconductor layer 36.

Thereafter, source and drain electrodes 40 and 42 are formed on the substrate having the ohmic contact layer 38.

As described above, in the aforementioned thin film transistor of the liquid crystal display device, an amorphous silicon film is used as the semiconductor layer, and an ohmic contact layer is interposed between the semiconductor layer and the source electrode / drain electrode. At this time, in the process of forming the ohmic contact layer, the silicon film doped with the impurity is excessively etched so that the ohmic contact layer does not remain on the channel. Therefore, the amorphous silicon film for forming the semiconductor layer should be deposited sufficiently thick in advance in consideration of the channel thickness and the etching margin, and the deposition time should be long for this purpose. As a result, there exists a problem that productivity falls.

3 is a diagram showing energy bands between lines I-I` in a turn-on state. In FIG. 3, region A corresponds to a source electrode / drain electrode, region B corresponds to an ohmic contact layer, and region C corresponds to a semiconductor layer. 4 is a graph showing the relationship between the resistances according to the drain voltages. Part P of FIG. 4 corresponds to a resistive component by a semiconductor layer which is amorphous silicon.

Meanwhile, the channel is formed between the gate insulating film and the semiconductor layer interface. An amorphous semiconductor layer having a high resistance is positioned between the channel and the source electrode to increase the overall channel resistance. That is, as shown in FIG. 3 and FIG. 4, it acts as an energy barrier between the ohmic contact layer and the channel to increase the channel resistance (see P part in FIG. 4). Therefore, there is also a problem of lowering the linear mobility (corresponding to about 0.4 cm 2 / Vs) of the thin film transistor.

In order to solve the above problems, an object of the present invention is to apply an amorphous silicon film and an impurity doped silicon film structure sequentially stacked in a semiconductor layer, thereby increasing the linear mobility of the amorphous silicon thin film transistor and to ensure productivity SUMMARY To provide a display device and a method of forming the same.

In order to achieve the above object, the liquid crystal display device according to the present invention comprises a substrate having a gate electrode, a gate insulating film formed on the substrate, an amorphous silicon film formed on the gate insulating film and sequentially stacked and a silicon film doped with impurities And a source electrode and a drain electrode formed on the substrate having the semiconductor layer and the semiconductor layer and spaced apart at regular intervals.

The source electrode and the drain electrode are formed so that a portion thereof overlaps with the gate electrode, or is spaced apart from the gate electrode at a predetermined interval.

It is preferable that the said impurity is N2.

A protective film having an ohmic contact layer interposed between the semiconductor layer and the source electrode / drain electrode, a substrate having a source electrode and a drain electrode, and having a contact hole exposing the drain electrode; The semiconductor device may further include a pixel electrode covering the contact hole.

The gate electrode includes a first gate electrode and a second gate electrode disposed in parallel with the first gate electrode.

A method of manufacturing a liquid crystal display device according to the present invention comprises the steps of providing a substrate, forming a gate electrode on the substrate, forming a gate insulating film on the substrate having the gate electrode, an amorphous silicon film on the gate insulating film And sequentially forming an impurity doped silicon film, patterning an impurity doped silicon film and an amorphous silicon film, and forming a semiconductor layer at a predetermined interval on the substrate having the semiconductor layer. Forming an electrode.

 In the forming of the silicon film doped with the impurity, the dopant may be doped in-situ while growing the silicon film.

The impurity is preferably doped at 0.1 to 10%.

Preferably, the amorphous silicon film is formed to have a thickness of 100 to 800 GPa, and the silicon film doped with the impurity is formed to have a thickness of 500 to 2000 GPa.

It is preferable that the said impurity is N2.

Forming an ohmic contact layer between the semiconductor layer and the source electrode / drain electrode, and forming a passivation layer having a contact hole exposing the drain electrode on a substrate having the source electrode and the drain electrode; The method may further include forming a pixel electrode covering the contact hole on the passivation layer.

The gate electrode may include forming a metal film on the substrate, and patterning the metal film to form a first gate electrode and a second gate electrode disposed in parallel with the first gate electrode.

(Example)

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention.

5 is a plan view illustrating a liquid crystal display device according to a first embodiment of the present invention.

As shown in FIG. 5, the liquid crystal display according to the first exemplary embodiment of the present invention has a plurality of gate lines 121 in one direction at regular intervals to define pixel regions on a first substrate (not shown). The data lines 131 are arranged at regular intervals in a direction perpendicular to the gate line 121.

Each pixel region defined by crossing the gate line 121 and the data line 131 is switched by a pixel electrode 119 formed in a matrix form and a signal of the gate line 121 to be switched by the data line ( A plurality of thin film transistors T1 for transmitting the signal of 131 to the pixel electrodes 119 are formed.

The thin film transistor T1 may include a gate electrode 103 protruding from the gate line 121, a gate insulating film (not shown) formed on the entire surface of the substrate having the gate electrode 103, and The semiconductor layer 108 formed on the gate insulating layer above the gate electrode 103, the source electrode 113S protruding from the data line 131, and the source electrode 113S are formed at regular intervals. It is comprised including the drain electrode 113D. In this case, the semiconductor layer 108 is formed of an amorphous silicon film and a silicon film doped with impurities. Here, the silicon film doped with the impurity is doped with nitrogen as an impurity.

On the other hand, a protective film (not shown) is formed on the substrate having the thin film transistor T1. A contact hole 117H exposing the drain electrode 113D is formed in the passivation layer. A pixel electrode 119 is formed on the passivation layer to be electrically connected to the drain electrode 113D through the contact hole 117H.

The first substrate configured as described above is bonded to the second substrate (not shown). At this time, although not shown, the second substrate has a light blocking layer (corresponding to a black matrix) and an opening to correspond to the pixel regions formed on the substrate and serves as a light blocking layer, and to implement color. It is composed of a red / green / blue (R / G / B) color filter layer and a common electrode.

The first substrate and the second substrate have a predetermined space by a spacer (not shown), and are bonded by a seal member (not shown) having a liquid crystal injection hole (not shown). Meanwhile, liquid crystal is injected between the substrate and the second substrate through the liquid crystal injection hole.

6A to 6F are cross-sectional views of processes according to the cutting line taken along the line II-II ′ of FIG. 5. 6A to 6E illustrate the formation of a liquid crystal display device according to a first embodiment of the present invention by using an amorphous silicon thin film transistor having an inverted staggered structure as an example. 6A to 6F, a method of forming a thin film transistor of a liquid crystal display device according to a first exemplary embodiment of the present invention having the above configuration will be described below.

As shown in FIG. 6A, a first metal film is formed on the first substrate 100, and the gate metal 103 is formed by patterning the first metal film by a photolithography process. In this case, a gate line is also formed along with the gate electrode 103. In addition, a buffer layer 101 may be further formed between the first substrate 100 and the gate electrode 103.

Subsequently, as illustrated in FIG. 6B, a gate insulating layer 105 is formed on the first substrate having the gate electrode 103. In this case, the gate insulating layer 105 may use a silicon oxide film or a silicon nitride film.

6C, an amorphous silicon film 107 and a silicon film 109 doped with a first impurity are successively deposited on the gate insulating film 105. At this time, the amorphous silicon film 107 is formed to a thickness of 100 ~ 800Å, the silicon film 109 doped with the WP1 impurity is formed to a thickness of 500 ~ 2000Å. In addition, the silicon layer 109 doped with the first impurity is formed by doping impurities in-situ while growing silicon. In the impurity doping treatment step, the impurity doping concentration is 0.1 to 10%. Here, the impurity uses nitrogen.

A process of forming the amorphous silicon film 107 and the silicon film 109 doped with the first impurity will be described below.

In fact, while supplying the N2 and SiH4 into the deposition equipment, by supplying a gas such that the ratio of [N2] / [SiH4] to 20% to form the amorphous silicon film 107, the linear mobility is 0.55cm 2 Increased to / Vs.

Thereafter, as illustrated in FIG. 6D, the silicon film 111 doped with the second impurity is formed on the silicon film doped with the first impurity. In this case, the silicon film 111 doped with the second impurity is for forming an ohmic contact layer.

6E, the semiconductor layer 108 is formed by patterning the silicon film doped with the second impurity, the silicon film doped with the first impurity, and the amorphous silicon film. Here, the semiconductor layer 108 is composed of a silicon film and an amorphous silicon film doped with a first impurity stacked sequentially.

Next, a second metal film is formed on the first substrate having the semiconductor layer 108. In this case, the second metal film uses a conductive metal such as aluminum (Al), chromium (Cr), or molybdenum (Mo). Next, the second metal film is patterned to form a source electrode 113S and a drain electrode 113D. In this case, the source electrode 113S and the drain electrode 113D may be formed so that a portion thereof overlaps with the gate electrode 103.

7 is a cross-sectional view of a liquid crystal display device having a structure in which the source electrode 113S and the drain electrode 113D do not overlap with the gate electrode 103 in the first embodiment of the present invention.

In addition to the above, as shown in FIG. 7, the source electrode 113S and the drain electrode 113D may be formed to be spaced apart at regular intervals without overlapping the gate electrode 103. In this case, there is no capacitance Cgs between the gate electrode 103 and the source electrode 113S, so that no kickback voltage is generated.

Subsequently, the silicon film doped with the second impurity remaining on the semiconductor layer 108 is removed using the source electrode 113S and the drain electrode 113D as a mask. As a result, an ohmic contact layer 112 made of a silicon film doped with the second impurity is formed between the source electrode 113S / drain electrode 113D and the semiconductor layer 108.

Next, as shown in FIG. 6F, the passivation layer 117 is formed on the first substrate having the ohmic contact layer 112. In this case, the passivation layer 117 may be an inorganic passivation layer or an organic passivation layer. Subsequently, the passivation layer 117 is patterned to form a contact hole 117H exposing the drain electrode 113D. Thereafter, a transparent conductive film is formed on the first substrate having the contact hole 117H. In this case, the transparent conductive film uses a transparent conductive metal having a relatively high transmittance of light, such as indium-tin-oxide (ITO). Subsequently, the transparent conductive film is patterned to form a pixel electrode 119 covering the contact hole 117H.

In the liquid crystal display device according to the first embodiment of the present invention obtained by the above-described method, as shown in FIGS. 5 and 6F, the first substrate 100 having the gate electrode 55 and the first substrate are provided. A semiconductor layer 108 formed of a gate insulating film 101 formed on the substrate 100, an amorphous silicon film formed on the gate insulating film 101, and a silicon film doped with a first impurity, and the semiconductor layer 108. And a source electrode 113S1 and a drain electrode 113D1 formed on a first substrate having a distance between the semiconductor substrate 108 and the source electrode / drain electrode 113S and 113D and spaced apart from each other at regular intervals. It is configured to include an interposed ohmic contact layer 112.

In this case, a portion of the source electrode 113S and the drain electrode 113D may be formed to overlap the gate electrode 103 or may be formed to be spaced apart from the gate electrode 103 at a predetermined interval.

Preferably, the amorphous silicon film has a thickness of 100 to 800 GPa, and the silicon film doped with the first impurity has a thickness of 500 to 2000 GPa. Here, the first impurity may be nitrogen.

Meanwhile, a passivation layer 117 formed on the first substrate having the source electrode / drain electrode 113S and 113D, and a contact hole 117H penetrating the passivation layer 117 to expose the drain electrode 113D. And a pixel electrode 119 formed on the passivation layer 117 and covering the contact hole 117H.

FIG. 8 shows the conductivity with respect to the impurity doping concentration when applying a semiconductor layer composed of an amorphous silicon film and a first impurity doped silicon film, which are sequentially stacked as in the first embodiment of the present invention. In Fig. 8, r _p (P doping level) = [PH3] / [SiH4] and r _N (N doping level) = [N2] / [SiH4].

9 illustrates a band energy structure between a source electrode and a channel in the first embodiment of the present invention. In FIG. 9, the region A ′ corresponds to a source electrode / drain electrode, the region B ′ corresponds to an ohmic contact layer, and the region C ′ corresponds to a semiconductor layer.

As shown in FIG. 9, when the amorphous silicon film and the first impurity doped silicon film structure are sequentially applied to the semiconductor layer as in the first embodiment of the present invention, nitrogen is used as the first impurity. Electrons injected into the source electrode by doping have a lower energy wall than that of FIG. 2 and can be easily conducted beyond the low energy wall.

10 is a graph comparing the transfer characteristics with the conventional case when the semiconductor layer according to the first embodiment of the present invention is applied, and it can be seen that the transfer characteristics are excellent as compared with the conventional one.

As described above, in the first embodiment of the present invention, by applying the amorphous silicon film and the first impurity doped silicon film structure sequentially stacked in the semiconductor layer, the linear mobility of the amorphous silicon thin film transistor is increased to provide a large-area high-resolution product. It is possible to apply and make the circuit integration easier.

According to the present invention, there is provided a semiconductor layer comprising an amorphous silicon film and a silicon film doped with impurities in order. Accordingly, the present invention increases the linear mobility of the amorphous silicon thin film transistor, thereby making it easy to apply to large-area high-resolution products and to facilitate circuit integration.

In addition, in the present invention, when the semiconductor layer is formed, an impurity doped silicon film is further formed on the amorphous silicon film, so that the etching margin of the amorphous silicon film need not be considered in the subsequent etching process for forming the ohmic contact layer. That is, since the amorphous silicon film can be formed thinner than the conventional one, the productivity is increased by shortening the process time due to the deposition.

Claims (14)

A substrate having a gate electrode, A gate insulating film formed on the substrate; A semiconductor layer formed on the gate insulating film and sequentially formed of an amorphous silicon film and a silicon film doped with impurities; And a source electrode and a drain electrode formed on a substrate having the semiconductor layer and spaced apart at regular intervals. The liquid crystal display device according to claim 1, wherein the source electrode and the drain electrode are formed so that a portion thereof overlaps with the gate electrode. The liquid crystal display of claim 1, wherein the source electrode and the drain electrode are formed to be spaced apart from the gate electrode at a predetermined interval. The liquid crystal display device according to claim 1, wherein the impurity is N2. The semiconductor device of claim 1, further comprising: an ohmic contact layer interposed between the semiconductor layer and the source electrode / drain electrode; A protective film formed on a substrate having the source electrode and the drain electrode, the protective layer having a contact hole exposing the drain electrode; And a pixel electrode formed on the passivation layer and covering the contact hole. The liquid crystal display of claim 1, wherein the gate electrode includes a first gate electrode and a second gate electrode disposed in parallel with the first gate electrode. Providing a substrate, Forming a gate electrode on the substrate; Forming a gate insulating film on the substrate having the gate electrode; Sequentially forming an amorphous silicon film and a silicon film doped with impurities on the gate insulating film; Patterning the doped silicon film and the amorphous silicon film to form a semiconductor layer; Forming a source electrode and a drain electrode spaced apart at regular intervals on the substrate having the semiconductor layer. The method of claim 7, wherein the forming of the silicon film doped with the impurity comprises doping the impurity in-situ while growing the silicon film. 8. The method of claim 7, wherein the impurity is doped at 0.1 to 10%. 8. The method of claim 7, wherein the amorphous silicon film is formed to a thickness of 100 to 800 kPa, and the silicon film doped with the impurity is formed to a thickness of 500 to 2000 kPa. 8. The method of claim 7, wherein the impurity is N2. The method of claim 11, wherein the impurity-doped silicon film forming step supplies the N2 and SiH4 into the deposition equipment, wherein the ratio of [N2] / [SiH4] is 20%. Formation method. The method of claim 17, Forming an ohmic contact layer between the semiconductor layer and the source electrode / drain electrode, Forming a protective film having a contact hole exposing the drain electrode on a substrate having the source electrode and the drain electrode; And forming a pixel electrode covering the contact hole on the passivation layer. The method of claim 7, wherein the gate electrode Forming a metal film on the substrate; And patterning the metal film to form a first gate electrode and a second gate electrode disposed in parallel with the first gate electrode.

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